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540dfc26 1/** @file\r
4135253b 2 Main SAL API's defined in Intel Itanium Processor Family System Abstraction\r
3 Layer Specification Revision 3.2 (December 2003)\r
540dfc26 4\r
9095d37b 5Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
9344f092 6SPDX-License-Identifier: BSD-2-Clause-Patent\r
540dfc26 7\r
540dfc26 8**/\r
9\r
10#ifndef __SAL_API_H__\r
11#define __SAL_API_H__\r
12\r
1bc5d021 13///\r
9095d37b 14/// SAL return status type\r
1bc5d021 15///\r
13f0a970 16typedef INTN EFI_SAL_STATUS;\r
1bc5d021 17\r
18///\r
9095d37b 19/// Call completed without error.\r
1bc5d021 20///\r
4135253b 21#define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)\r
1bc5d021 22///\r
9095d37b 23/// Call completed without error, but some information was lost due to overflow.\r
1bc5d021 24///\r
4135253b 25#define EFI_SAL_OVERFLOW ((EFI_SAL_STATUS) 1)\r
1bc5d021 26///\r
4135253b 27/// Call completed without error; effect a warm boot of the system to complete the update.\r
28///\r
29#define EFI_SAL_WARM_BOOT_NEEDED ((EFI_SAL_STATUS) 2)\r
30///\r
9095d37b 31/// More information is available for retrieval.\r
1bc5d021 32///\r
540dfc26 33#define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)\r
4135253b 34///\r
35/// Not implemented.\r
36///\r
540dfc26 37#define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)\r
4135253b 38///\r
39/// Invalid Argument.\r
40///\r
540dfc26 41#define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)\r
4135253b 42///\r
9095d37b 43/// Call completed without error.\r
4135253b 44///\r
540dfc26 45#define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)\r
4135253b 46///\r
9095d37b 47/// Virtual address not registered.\r
4135253b 48///\r
540dfc26 49#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)\r
4135253b 50///\r
9095d37b 51/// No information available.\r
4135253b 52///\r
540dfc26 53#define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)\r
4135253b 54///\r
55/// Scratch buffer required.\r
56///\r
540dfc26 57#define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)\r
58\r
4135253b 59///\r
af2dc6a7 60/// Return registers from SAL.\r
4135253b 61///\r
540dfc26 62typedef struct {\r
4135253b 63 ///\r
af2dc6a7 64 /// SAL return status value in r8.\r
4135253b 65 ///\r
66 EFI_SAL_STATUS Status;\r
67 ///\r
af2dc6a7 68 /// SAL returned value in r9.\r
4135253b 69 ///\r
540dfc26 70 UINTN r9;\r
4135253b 71 ///\r
af2dc6a7 72 /// SAL returned value in r10.\r
4135253b 73 ///\r
540dfc26 74 UINTN r10;\r
4135253b 75 ///\r
af2dc6a7 76 /// SAL returned value in r11.\r
4135253b 77 ///\r
540dfc26 78 UINTN r11;\r
79} SAL_RETURN_REGS;\r
80\r
4135253b 81/**\r
82 Prototype of SAL procedures.\r
83\r
14996c96 84 @param FunctionId Functional identifier.\r
4135253b 85 The upper 32 bits are ignored and only the lower 32 bits\r
86 are used. The following functional identifiers are defined:\r
f7763aa4 87 0x01XXXXXX - Architected SAL functional group.\r
88 0x02XXXXXX to 0x03XXXXXX - OEM SAL functional group. Each OEM is\r
4135253b 89 allowed to use the entire range in the 0x02XXXXXX to 0x03XXXXXX range.\r
f7763aa4 90 0x04XXXXXX to 0xFFFFFFFF - Reserved.\r
4135253b 91 @param Arg1 The first parameter of the architected/OEM specific SAL functions.\r
92 @param Arg2 The second parameter of the architected/OEM specific SAL functions.\r
af2dc6a7 93 @param Arg3 The third parameter passed to the ESAL function based.\r
94 @param Arg4 The fourth parameter passed to the ESAL function based.\r
95 @param Arg5 The fifth parameter passed to the ESAL function based.\r
96 @param Arg6 The sixth parameter passed to the ESAL function.\r
97 @param Arg7 The seventh parameter passed to the ESAL function based.\r
4135253b 98\r
99 @return r8 Return status: positive number indicates successful,\r
100 negative number indicates failure.\r
101 r9 Other return parameter in r9.\r
102 r10 Other return parameter in r10.\r
103 r11 Other return parameter in r11.\r
104\r
105**/\r
106typedef\r
107SAL_RETURN_REGS\r
d1c810fc 108(EFIAPI *SAL_PROC)(\r
4135253b 109 IN UINT64 FunctionId,\r
14996c96 110 IN UINT64 Arg1,\r
4135253b 111 IN UINT64 Arg2,\r
112 IN UINT64 Arg3,\r
113 IN UINT64 Arg4,\r
114 IN UINT64 Arg5,\r
115 IN UINT64 Arg6,\r
14996c96 116 IN UINT64 Arg7\r
540dfc26 117 );\r
118\r
119//\r
120// SAL Procedure FunctionId definition\r
121//\r
4135253b 122\r
123///\r
124/// Register software code locations with SAL.\r
125///\r
540dfc26 126#define EFI_SAL_SET_VECTORS 0x01000000\r
4135253b 127///\r
128/// Return Machine State information obtained by SAL.\r
129///\r
540dfc26 130#define EFI_SAL_GET_STATE_INFO 0x01000001\r
4135253b 131///\r
132/// Obtain size of Machine State information.\r
133///\r
540dfc26 134#define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002\r
4135253b 135///\r
136/// Clear Machine State information.\r
137///\r
540dfc26 138#define EFI_SAL_CLEAR_STATE_INFO 0x01000003\r
4135253b 139///\r
140/// Cause the processor to go into a spin loop within SAL.\r
141///\r
540dfc26 142#define EFI_SAL_MC_RENDEZ 0x01000004\r
4135253b 143///\r
144/// Register the machine check interface layer with SAL.\r
145///\r
540dfc26 146#define EFI_SAL_MC_SET_PARAMS 0x01000005\r
4135253b 147///\r
148/// Register the physical addresses of locations needed by SAL.\r
149///\r
540dfc26 150#define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006\r
4135253b 151///\r
152/// Flush the instruction or data caches.\r
153///\r
540dfc26 154#define EFI_SAL_CACHE_FLUSH 0x01000008\r
4135253b 155///\r
156/// Initialize the instruction and data caches.\r
157///\r
540dfc26 158#define EFI_SAL_CACHE_INIT 0x01000009\r
4135253b 159///\r
160/// Read from the PCI configuration space.\r
161///\r
540dfc26 162#define EFI_SAL_PCI_CONFIG_READ 0x01000010\r
4135253b 163///\r
164/// Write to the PCI configuration space.\r
165///\r
540dfc26 166#define EFI_SAL_PCI_CONFIG_WRITE 0x01000011\r
4135253b 167///\r
168/// Return the base frequency of the platform.\r
169///\r
540dfc26 170#define EFI_SAL_FREQ_BASE 0x01000012\r
4135253b 171///\r
172/// Returns information on the physical processor mapping within the platform.\r
173///\r
9c8403b3 174#define EFI_SAL_PHYSICAL_ID_INFO 0x01000013\r
4135253b 175///\r
176/// Update the contents of firmware blocks.\r
177///\r
540dfc26 178#define EFI_SAL_UPDATE_PAL 0x01000020\r
179\r
180#define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff\r
181#define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021\r
182\r
183//\r
184// SAL Procedure parameter definitions\r
185// Not much point in using typedefs or enums because all params\r
186// are UINT64 and the entry point is common\r
187//\r
4135253b 188\r
189//\r
190// Parameter of EFI_SAL_SET_VECTORS\r
191//\r
192// Vector type\r
540dfc26 193//\r
194#define EFI_SAL_SET_MCA_VECTOR 0x0\r
195#define EFI_SAL_SET_INIT_VECTOR 0x1\r
196#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2\r
4135253b 197///\r
af2dc6a7 198/// The format of a length_cs_n argument.\r
4135253b 199///\r
540dfc26 200typedef struct {\r
201 UINT64 Length : 32;\r
202 UINT64 ChecksumValid : 1;\r
203 UINT64 Reserved1 : 7;\r
204 UINT64 ByteChecksum : 8;\r
205 UINT64 Reserved2 : 16;\r
206} SAL_SET_VECTORS_CS_N;\r
207\r
208//\r
4135253b 209// Parameter of EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE, and EFI_SAL_CLEAR_STATE_INFO\r
9095d37b 210//\r
4135253b 211// Type of information\r
540dfc26 212//\r
213#define EFI_SAL_MCA_STATE_INFO 0x0\r
214#define EFI_SAL_INIT_STATE_INFO 0x1\r
215#define EFI_SAL_CMC_STATE_INFO 0x2\r
216#define EFI_SAL_CP_STATE_INFO 0x3\r
217\r
218//\r
4135253b 219// Parameter of EFI_SAL_MC_SET_PARAMS\r
220//\r
221// Unsigned 64-bit integer value for the parameter type of the machine check interface\r
540dfc26 222//\r
223#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1\r
224#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2\r
225#define EFI_SAL_MC_SET_CPE_PARAM 0x3\r
4135253b 226//\r
227// Unsigned 64-bit integer value indicating whether interrupt vector or\r
228// memory address is specified\r
229//\r
540dfc26 230#define EFI_SAL_MC_SET_INTR_PARAM 0x1\r
231#define EFI_SAL_MC_SET_MEM_PARAM 0x2\r
232\r
233//\r
4135253b 234// Parameter of EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR\r
235//\r
236// The encoded value of the entity whose physical address is registered\r
540dfc26 237//\r
238#define EFI_SAL_REGISTER_PAL_ADDR 0x0\r
239\r
240//\r
4135253b 241// Parameter of EFI_SAL_CACHE_FLUSH\r
242//\r
243// Unsigned 64-bit integer denoting type of cache flush operation\r
540dfc26 244//\r
245#define EFI_SAL_FLUSH_I_CACHE 0x01\r
246#define EFI_SAL_FLUSH_D_CACHE 0x02\r
247#define EFI_SAL_FLUSH_BOTH_CACHE 0x03\r
248#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04\r
249\r
250//\r
4135253b 251// Parameter of EFI_SAL_PCI_CONFIG_READ and EFI_SAL_PCI_CONFIG_WRITE\r
252//\r
253// PCI config size\r
540dfc26 254//\r
255#define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1\r
256#define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2\r
257#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4\r
4135253b 258//\r
259// The type of PCI configuration address\r
260//\r
261#define EFI_SAL_PCI_COMPATIBLE_ADDRESS 0x0\r
262#define EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS 0x1\r
263///\r
af2dc6a7 264/// The format of PCI Compatible Address.\r
4135253b 265///\r
540dfc26 266typedef struct {\r
267 UINT64 Register : 8;\r
268 UINT64 Function : 3;\r
269 UINT64 Device : 5;\r
270 UINT64 Bus : 8;\r
271 UINT64 Segment : 8;\r
272 UINT64 Reserved : 32;\r
273} SAL_PCI_ADDRESS;\r
4135253b 274///\r
af2dc6a7 275/// The format of Extended Register Address.\r
4135253b 276///\r
277typedef struct {\r
278 UINT64 Register : 8;\r
279 UINT64 ExtendedRegister : 4;\r
280 UINT64 Function : 3;\r
281 UINT64 Device : 5;\r
282 UINT64 Bus : 8;\r
283 UINT64 Segment : 16;\r
284 UINT64 Reserved : 20;\r
285} SAL_PCI_EXTENDED_REGISTER_ADDRESS;\r
540dfc26 286\r
287//\r
4135253b 288// Parameter of EFI_SAL_FREQ_BASE\r
289//\r
290// Unsigned 64-bit integer specifying the type of clock source\r
540dfc26 291//\r
292#define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0\r
293#define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1\r
294#define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2\r
295\r
296//\r
4135253b 297// Parameter and return value of EFI_SAL_UPDATE_PAL\r
298//\r
299// Return parameter provides additional information on the\r
f7763aa4 300// failure when the status field contains a value of -3,\r
4135253b 301// returned in r9.\r
540dfc26 302//\r
303#define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)\r
304#define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)\r
305#define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)\r
306#define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)\r
307#define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)\r
308#define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)\r
309#define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)\r
310#define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)\r
4135253b 311///\r
312/// 64-byte header of update data block.\r
313///\r
540dfc26 314typedef struct {\r
315 UINT32 Size;\r
316 UINT32 MmddyyyyDate;\r
317 UINT16 Version;\r
318 UINT8 Type;\r
319 UINT8 Reserved[5];\r
320 UINT64 FwVendorId;\r
e1da91ad 321 UINT8 Reserved2[40];\r
540dfc26 322} SAL_UPDATE_PAL_DATA_BLOCK;\r
4135253b 323///\r
af2dc6a7 324/// Data structure pointed by the parameter param_buf.\r
4135253b 325/// It is a 16-byte aligned data structure in memory with a length of 32 bytes\r
326/// that describes the new firmware. This information is organized in the form\r
327/// of a linked list with each element describing one firmware component.\r
328///\r
540dfc26 329typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {\r
330 struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;\r
331 struct SAL_UPDATE_PAL_DATA_BLOCK *DataBlock;\r
332 UINT8 StoreChecksum;\r
333 UINT8 Reserved[15];\r
334} SAL_UPDATE_PAL_INFO_BLOCK;\r
335\r
4135253b 336///\r
af2dc6a7 337/// SAL System Table Definitions.\r
4135253b 338///\r
766f4bc1 339#pragma pack(1)\r
540dfc26 340typedef struct {\r
4135253b 341 ///\r
9095d37b
LG		 342 /// The ASCII string representation of "SST_" that confirms the presence of the table.\r
343 ///\r
540dfc26 344 UINT32 Signature;\r
4135253b 345 ///\r
346 /// The length of the entire table in bytes, starting from offset zero and including the\r
347 /// header and all entries indicated by the EntryCount field.\r
348 ///\r
540dfc26 349 UINT32 Length;\r
4135253b 350 ///\r
351 /// The revision number of the Itanium Processor Family System Abstraction Layer\r
af2dc6a7 352 /// Specification supported by the SAL implementation, in binary coded decimal (BCD) format.\r
4135253b 353 ///\r
540dfc26 354 UINT16 SalRevision;\r
4135253b 355 ///\r
356 /// The number of entries in the variable portion of the table.\r
357 ///\r
540dfc26 358 UINT16 EntryCount;\r
4135253b 359 ///\r
360 /// A modulo checksum of the entire table and the entries following this table.\r
361 ///\r
540dfc26 362 UINT8 CheckSum;\r
4135253b 363 ///\r
364 /// Unused, must be zero.\r
365 ///\r
540dfc26 366 UINT8 Reserved[7];\r
4135253b 367 ///\r
368 /// Version Number of the SAL_A firmware implementation in BCD format.\r
369 ///\r
540dfc26 370 UINT16 SalAVersion;\r
4135253b 371 ///\r
372 /// Version Number of the SAL_B firmware implementation in BCD format.\r
373 ///\r
540dfc26 374 UINT16 SalBVersion;\r
4135253b 375 ///\r
376 /// An ASCII identification string which uniquely identifies the manufacturer\r
377 /// of the system hardware.\r
378 ///\r
540dfc26 379 UINT8 OemId[32];\r
4135253b 380 ///\r
381 /// An ASCII identification string which uniquely identifies a family of\r
382 /// compatible products from the manufacturer.\r
383 ///\r
540dfc26 384 UINT8 ProductId[32];\r
4135253b 385 ///\r
386 /// Unused, must be zero.\r
387 ///\r
540dfc26 388 UINT8 Reserved2[8];\r
389} SAL_SYSTEM_TABLE_HEADER;\r
540dfc26 390\r
391#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"\r
4135253b 392#define EFI_SAL_REVISION 0x0320\r
540dfc26 393//\r
394// SAL System Types\r
395//\r
396#define EFI_SAL_ST_ENTRY_POINT 0\r
397#define EFI_SAL_ST_MEMORY_DESCRIPTOR 1\r
398#define EFI_SAL_ST_PLATFORM_FEATURES 2\r
399#define EFI_SAL_ST_TR_USAGE 3\r
400#define EFI_SAL_ST_PTC 4\r
401#define EFI_SAL_ST_AP_WAKEUP 5\r
402\r
809177f5 403//\r
404// SAL System Type Sizes\r
405//\r
406#define EFI_SAL_ST_ENTRY_POINT_SIZE 48\r
407#define EFI_SAL_ST_MEMORY_DESCRIPTOR_SIZE 32\r
408#define EFI_SAL_ST_PLATFORM_FEATURES_SIZE 16\r
409#define EFI_SAL_ST_TR_USAGE_SIZE 32\r
410#define EFI_SAL_ST_PTC_SIZE 16\r
411#define EFI_SAL_ST_AP_WAKEUP_SIZE 16\r
412\r
4135253b 413///\r
af2dc6a7 414/// Format of Entrypoint Descriptor Entry.\r
4135253b 415///\r
540dfc26 416typedef struct {\r
af2dc6a7 417 UINT8 Type; ///< Type here should be 0.\r
540dfc26 418 UINT8 Reserved[7];\r
419 UINT64 PalProcEntry;\r
420 UINT64 SalProcEntry;\r
421 UINT64 SalGlobalDataPointer;\r
422 UINT64 Reserved2[2];\r
423} SAL_ST_ENTRY_POINT_DESCRIPTOR;\r
424\r
4135253b 425///\r
af2dc6a7 426/// Format of Platform Features Descriptor Entry.\r
4135253b 427///\r
540dfc26 428typedef struct {\r
af2dc6a7 429 UINT8 Type; ///< Type here should be 2.\r
540dfc26 430 UINT8 PlatformFeatures;\r
431 UINT8 Reserved[14];\r
432} SAL_ST_PLATFORM_FEATURES;\r
1fc0ee17 433\r
4135253b 434//\r
435// Value of Platform Feature List\r
436//\r
540dfc26 437#define SAL_PLAT_FEAT_BUS_LOCK 0x01\r
438#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02\r
439#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04\r
440\r
4135253b 441///\r
af2dc6a7 442/// Format of Translation Register Descriptor Entry.\r
4135253b 443///\r
540dfc26 444typedef struct {\r
af2dc6a7 445 UINT8 Type; ///< Type here should be 3.\r
540dfc26 446 UINT8 TRType;\r
447 UINT8 TRNumber;\r
448 UINT8 Reserved[5];\r
449 UINT64 VirtualAddress;\r
450 UINT64 EncodedPageSize;\r
451 UINT64 Reserved1;\r
452} SAL_ST_TR_DECRIPTOR;\r
1fc0ee17 453\r
4135253b 454//\r
455// Type of Translation Register\r
456//\r
540dfc26 457#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00\r
458#define EFI_SAL_ST_TR_USAGE_DATA 01\r
459\r
4135253b 460///\r
af2dc6a7 461/// Definition of Coherence Domain Information.\r
4135253b 462///\r
540dfc26 463typedef struct {\r
464 UINT64 NumberOfProcessors;\r
465 UINT64 LocalIDRegister;\r
466} SAL_COHERENCE_DOMAIN_INFO;\r
9095d37b 467\r
4135253b 468///\r
af2dc6a7 469/// Format of Purge Translation Cache Coherence Domain Entry.\r
4135253b 470///\r
540dfc26 471typedef struct {\r
af2dc6a7 472 UINT8 Type; ///< Type here should be 4.\r
540dfc26 473 UINT8 Reserved[3];\r
474 UINT32 NumberOfDomains;\r
475 SAL_COHERENCE_DOMAIN_INFO *DomainInformation;\r
476} SAL_ST_CACHE_COHERENCE_DECRIPTOR;\r
540dfc26 477\r
4135253b 478///\r
af2dc6a7 479/// Format of Application Processor Wake-Up Descriptor Entry.\r
4135253b 480///\r
540dfc26 481typedef struct {\r
af2dc6a7 482 UINT8 Type; ///< Type here should be 5.\r
540dfc26 483 UINT8 WakeUpType;\r
484 UINT8 Reserved[6];\r
485 UINT64 ExternalInterruptVector;\r
486} SAL_ST_AP_WAKEUP_DECRIPTOR;\r
540dfc26 487\r
4135253b 488///\r
af2dc6a7 489/// Format of Firmware Interface Table (FIT) Entry.\r
4135253b 490///\r
540dfc26 491typedef struct {\r
492 UINT64 Address;\r
493 UINT8 Size[3];\r
494 UINT8 Reserved;\r
495 UINT16 Revision;\r
496 UINT8 Type : 7;\r
497 UINT8 CheckSumValid : 1;\r
498 UINT8 CheckSum;\r
499} EFI_SAL_FIT_ENTRY;\r
4135253b 500//\r
9095d37b 501// FIT Types\r
4135253b 502//\r
503#define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00\r
504#define EFI_SAL_FIT_PAL_B_TYPE 0x01\r
505//\r
506// Type from 0x02 to 0x0D is reserved.\r
507//\r
508#define EFI_SAL_FIT_PROCESSOR_SPECIFIC_PAL_A_TYPE 0x0E\r
509#define EFI_SAL_FIT_PAL_A_TYPE 0x0F\r
510//\r
511// OEM-defined type range is from 0x10 to 0x7E.\r
512// Here we defined the PEI_CORE type as 0x10\r
513//\r
514#define EFI_SAL_FIT_PEI_CORE_TYPE 0x10\r
515#define EFI_SAL_FIT_UNUSED_TYPE 0x7F\r
540dfc26 516\r
517//\r
4135253b 518// FIT Entry\r
540dfc26 519//\r
4135253b 520#define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24\r
521#define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32\r
522#define EFI_SAL_FIT_PALB_TYPE 01\r
540dfc26 523\r
4135253b 524//\r
525// Following definitions are for Error Record Structure\r
526//\r
527\r
528///\r
af2dc6a7 529/// Format of TimeStamp field in Record Header.\r
4135253b 530///\r
540dfc26 531typedef struct {\r
532 UINT8 Seconds;\r
533 UINT8 Minutes;\r
534 UINT8 Hours;\r
535 UINT8 Reserved;\r
536 UINT8 Day;\r
537 UINT8 Month;\r
538 UINT8 Year;\r
539 UINT8 Century;\r
540} SAL_TIME_STAMP;\r
4135253b 541///\r
af2dc6a7 542/// Definition of Record Header.\r
4135253b 543///\r
540dfc26 544typedef struct {\r
545 UINT64 RecordId;\r
546 UINT16 Revision;\r
547 UINT8 ErrorSeverity;\r
548 UINT8 ValidationBits;\r
549 UINT32 RecordLength;\r
550 SAL_TIME_STAMP TimeStamp;\r
551 UINT8 OemPlatformId[16];\r
552} SAL_RECORD_HEADER;\r
4135253b 553///\r
af2dc6a7 554/// Definition of Section Header.\r
4135253b 555///\r
540dfc26 556typedef struct {\r
4135253b 557 GUID Guid;\r
540dfc26 558 UINT16 Revision;\r
559 UINT8 ErrorRecoveryInfo;\r
560 UINT8 Reserved;\r
561 UINT32 SectionLength;\r
562} SAL_SEC_HEADER;\r
563\r
4135253b 564///\r
af2dc6a7 565/// GUID of Processor Machine Check Errors.\r
4135253b 566///\r
540dfc26 567#define SAL_PROCESSOR_ERROR_RECORD_INFO \\r
568 { \\r
569 0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
570 }\r
4135253b 571//\r
572// Bit masks for valid bits of MOD_ERROR_INFO\r
573//\r
540dfc26 574#define CHECK_INFO_VALID_BIT_MASK 0x1\r
575#define REQUESTOR_ID_VALID_BIT_MASK 0x2\r
576#define RESPONDER_ID_VALID_BIT_MASK 0x4\r
577#define TARGER_ID_VALID_BIT_MASK 0x8\r
578#define PRECISE_IP_VALID_BIT_MASK 0x10\r
4135253b 579///\r
af2dc6a7 580/// Definition of MOD_ERROR_INFO_STRUCT.\r
4135253b 581///\r
540dfc26 582typedef struct {\r
583 UINT64 InfoValid : 1;\r
584 UINT64 ReqValid : 1;\r
585 UINT64 RespValid : 1;\r
586 UINT64 TargetValid : 1;\r
587 UINT64 IpValid : 1;\r
588 UINT64 Reserved : 59;\r
589 UINT64 Info;\r
590 UINT64 Req;\r
591 UINT64 Resp;\r
592 UINT64 Target;\r
593 UINT64 Ip;\r
594} MOD_ERROR_INFO;\r
4135253b 595///\r
af2dc6a7 596/// Definition of CPUID_INFO_STRUCT.\r
4135253b 597///\r
540dfc26 598typedef struct {\r
599 UINT8 CpuidInfo[40];\r
600 UINT8 Reserved;\r
601} CPUID_INFO;\r
602\r
603typedef struct {\r
604 UINT64 FrLow;\r
605 UINT64 FrHigh;\r
606} FR_STRUCT;\r
4135253b 607//\r
608// Bit masks for PSI_STATIC_STRUCT.ValidFieldBits\r
609//\r
540dfc26 610#define MIN_STATE_VALID_BIT_MASK 0x1\r
611#define BR_VALID_BIT_MASK 0x2\r
612#define CR_VALID_BIT_MASK 0x4\r
613#define AR_VALID_BIT_MASK 0x8\r
614#define RR_VALID_BIT_MASK 0x10\r
615#define FR_VALID_BIT_MASK 0x20\r
4135253b 616///\r
af2dc6a7 617/// Definition of PSI_STATIC_STRUCT.\r
4135253b 618///\r
540dfc26 619typedef struct {\r
620 UINT64 ValidFieldBits;\r
621 UINT8 MinStateInfo[1024];\r
622 UINT64 Br[8];\r
623 UINT64 Cr[128];\r
624 UINT64 Ar[128];\r
625 UINT64 Rr[8];\r
626 FR_STRUCT Fr[128];\r
627} PSI_STATIC_STRUCT;\r
4135253b 628//\r
629// Bit masks for SAL_PROCESSOR_ERROR_RECORD.ValidationBits\r
630//\r
540dfc26 631#define PROC_ERROR_MAP_VALID_BIT_MASK 0x1\r
632#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2\r
633#define PROC_CR_LID_VALID_BIT_MASK 0x4\r
634#define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8\r
635#define CPU_INFO_VALID_BIT_MASK 0x1000000\r
4135253b 636///\r
af2dc6a7 637/// Definition of Processor Machine Check Error Record.\r
4135253b 638///\r
540dfc26 639typedef struct {\r
640 SAL_SEC_HEADER SectionHeader;\r
641 UINT64 ValidationBits;\r
642 UINT64 ProcErrorMap;\r
643 UINT64 ProcStateParameter;\r
644 UINT64 ProcCrLid;\r
645 MOD_ERROR_INFO CacheError[15];\r
646 MOD_ERROR_INFO TlbError[15];\r
647 MOD_ERROR_INFO BusError[15];\r
648 MOD_ERROR_INFO RegFileCheck[15];\r
649 MOD_ERROR_INFO MsCheck[15];\r
650 CPUID_INFO CpuInfo;\r
651 PSI_STATIC_STRUCT PsiValidData;\r
652} SAL_PROCESSOR_ERROR_RECORD;\r
653\r
4135253b 654///\r
af2dc6a7 655/// GUID of Platform Memory Device Error Info.\r
4135253b 656///\r
540dfc26 657#define SAL_MEMORY_ERROR_RECORD_INFO \\r
658 { \\r
659 0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
660 }\r
4135253b 661//\r
662// Bit masks for SAL_MEMORY_ERROR_RECORD.ValidationBits\r
663//\r
540dfc26 664#define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1\r
665#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2\r
666#define MEMORY_ADDR_BIT_MASK 0x4\r
667#define MEMORY_NODE_VALID_BIT_MASK 0x8\r
668#define MEMORY_CARD_VALID_BIT_MASK 0x10\r
669#define MEMORY_MODULE_VALID_BIT_MASK 0x20\r
670#define MEMORY_BANK_VALID_BIT_MASK 0x40\r
671#define MEMORY_DEVICE_VALID_BIT_MASK 0x80\r
672#define MEMORY_ROW_VALID_BIT_MASK 0x100\r
673#define MEMORY_COLUMN_VALID_BIT_MASK 0x200\r
674#define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400\r
675#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800\r
676#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000\r
677#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000\r
678#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000\r
679#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000\r
680#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000\r
4135253b 681///\r
af2dc6a7 682/// Definition of Platform Memory Device Error Info Record.\r
4135253b 683///\r
540dfc26 684typedef struct {\r
685 SAL_SEC_HEADER SectionHeader;\r
686 UINT64 ValidationBits;\r
687 UINT64 MemErrorStatus;\r
688 UINT64 MemPhysicalAddress;\r
689 UINT64 MemPhysicalAddressMask;\r
690 UINT16 MemNode;\r
691 UINT16 MemCard;\r
692 UINT16 MemModule;\r
693 UINT16 MemBank;\r
694 UINT16 MemDevice;\r
695 UINT16 MemRow;\r
696 UINT16 MemColumn;\r
697 UINT16 MemBitPosition;\r
698 UINT64 ModRequestorId;\r
699 UINT64 ModResponderId;\r
700 UINT64 ModTargetId;\r
701 UINT64 BusSpecificData;\r
702 UINT8 MemPlatformOemId[16];\r
703} SAL_MEMORY_ERROR_RECORD;\r
704\r
4135253b 705///\r
af2dc6a7 706/// GUID of Platform PCI Bus Error Info.\r
4135253b 707///\r
540dfc26 708#define SAL_PCI_BUS_ERROR_RECORD_INFO \\r
709 { \\r
710 0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
711 }\r
4135253b 712//\r
713// Bit masks for SAL_PCI_BUS_ERROR_RECORD.ValidationBits\r
714//\r
540dfc26 715#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1\r
716#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2\r
717#define PCI_BUS_ID_VALID_BIT_MASK 0x4\r
718#define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8\r
719#define PCI_BUS_DATA_VALID_BIT_MASK 0x10\r
720#define PCI_BUS_CMD_VALID_BIT_MASK 0x20\r
721#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40\r
722#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80\r
723#define PCI_BUS_TARGET_VALID_BIT_MASK 0x100\r
724#define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200\r
725#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400\r
726\r
bf7ea009 727///\r
af2dc6a7 728/// Designated PCI Bus identifier.\r
bf7ea009 729///\r
540dfc26 730typedef struct {\r
731 UINT8 BusNumber;\r
732 UINT8 SegmentNumber;\r
733} PCI_BUS_ID;\r
bf7ea009 734\r
4135253b 735///\r
af2dc6a7 736/// Definition of Platform PCI Bus Error Info Record.\r
4135253b 737///\r
540dfc26 738typedef struct {\r
739 SAL_SEC_HEADER SectionHeader;\r
740 UINT64 ValidationBits;\r
741 UINT64 PciBusErrorStatus;\r
742 UINT16 PciBusErrorType;\r
743 PCI_BUS_ID PciBusId;\r
744 UINT32 Reserved;\r
745 UINT64 PciBusAddress;\r
746 UINT64 PciBusData;\r
747 UINT64 PciBusCommand;\r
748 UINT64 PciBusRequestorId;\r
749 UINT64 PciBusResponderId;\r
750 UINT64 PciBusTargetId;\r
751 UINT8 PciBusOemId[16];\r
752} SAL_PCI_BUS_ERROR_RECORD;\r
753\r
4135253b 754///\r
af2dc6a7 755/// GUID of Platform PCI Component Error Info.\r
4135253b 756///\r
540dfc26 757#define SAL_PCI_COMP_ERROR_RECORD_INFO \\r
758 { \\r
759 0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
760 }\r
4135253b 761//\r
762// Bit masks for SAL_PCI_COMPONENT_ERROR_RECORD.ValidationBits\r
763//\r
540dfc26 764#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1\r
765#define PCI_COMP_INFO_VALID_BIT_MASK 0x2\r
766#define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4\r
767#define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8\r
768#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10\r
769#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20\r
4135253b 770///\r
af2dc6a7 771/// Format of PCI Component Information to identify the device.\r
4135253b 772///\r
540dfc26 773typedef struct {\r
774 UINT16 VendorId;\r
775 UINT16 DeviceId;\r
776 UINT8 ClassCode[3];\r
777 UINT8 FunctionNumber;\r
778 UINT8 DeviceNumber;\r
779 UINT8 BusNumber;\r
780 UINT8 SegmentNumber;\r
781 UINT8 Reserved[5];\r
782} PCI_COMP_INFO;\r
4135253b 783///\r
af2dc6a7 784/// Definition of Platform PCI Component Error Info.\r
4135253b 785///\r
540dfc26 786typedef struct {\r
787 SAL_SEC_HEADER SectionHeader;\r
788 UINT64 ValidationBits;\r
789 UINT64 PciComponentErrorStatus;\r
790 PCI_COMP_INFO PciComponentInfo;\r
791 UINT32 PciComponentMemNum;\r
792 UINT32 PciComponentIoNum;\r
793 UINT8 PciBusOemId[16];\r
794} SAL_PCI_COMPONENT_ERROR_RECORD;\r
795\r
4135253b 796///\r
af2dc6a7 797/// Platform SEL Device Error Info.\r
4135253b 798///\r
799#define SAL_SEL_DEVICE_ERROR_RECORD_INFO \\r
540dfc26 800 { \\r
801 0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
802 }\r
4135253b 803//\r
804// Bit masks for SAL_SEL_DEVICE_ERROR_RECORD.ValidationBits\r
805//\r
540dfc26 806#define SEL_RECORD_ID_VALID_BIT_MASK 0x1;\r
807#define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;\r
808#define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;\r
809#define SEL_EVM_REV_VALID_BIT_MASK 0x8;\r
810#define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;\r
811#define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;\r
812#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;\r
813#define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;\r
814#define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;\r
815#define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;\r
4135253b 816///\r
af2dc6a7 817/// Definition of Platform SEL Device Error Info Record.\r
4135253b 818///\r
540dfc26 819typedef struct {\r
820 SAL_SEC_HEADER SectionHeader;\r
821 UINT64 ValidationBits;\r
822 UINT16 SelRecordId;\r
823 UINT8 SelRecordType;\r
824 UINT32 TimeStamp;\r
825 UINT16 GeneratorId;\r
826 UINT8 EvmRevision;\r
827 UINT8 SensorType;\r
828 UINT8 SensorNum;\r
829 UINT8 EventDirType;\r
830 UINT8 Data1;\r
831 UINT8 Data2;\r
832 UINT8 Data3;\r
4135253b 833} SAL_SEL_DEVICE_ERROR_RECORD;\r
540dfc26 834\r
4135253b 835///\r
af2dc6a7 836/// GUID of Platform SMBIOS Device Error Info.\r
4135253b 837///\r
540dfc26 838#define SAL_SMBIOS_ERROR_RECORD_INFO \\r
839 { \\r
840 0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
841 }\r
4135253b 842//\r
843// Bit masks for SAL_SMBIOS_DEVICE_ERROR_RECORD.ValidationBits\r
844//\r
540dfc26 845#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1\r
846#define SMBIOS_LENGTH_VALID_BIT_MASK 0x2\r
847#define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4\r
848#define SMBIOS_DATA_VALID_BIT_MASK 0x8\r
4135253b 849///\r
af2dc6a7 850/// Definition of Platform SMBIOS Device Error Info Record.\r
4135253b 851///\r
540dfc26 852typedef struct {\r
853 SAL_SEC_HEADER SectionHeader;\r
854 UINT64 ValidationBits;\r
855 UINT8 SmbiosEventType;\r
856 UINT8 SmbiosLength;\r
857 UINT8 SmbiosBcdTimeStamp[6];\r
858} SAL_SMBIOS_DEVICE_ERROR_RECORD;\r
859\r
1bc5d021 860///\r
af2dc6a7 861/// GUID of Platform Specific Error Info.\r
1bc5d021 862///\r
540dfc26 863#define SAL_PLATFORM_ERROR_RECORD_INFO \\r
864 { \\r
865 0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
866 }\r
4135253b 867//\r
868// Bit masks for SAL_PLATFORM_SPECIFIC_ERROR_RECORD.ValidationBits\r
869//\r
540dfc26 870#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1\r
871#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2\r
872#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4\r
873#define PLATFORM_TARGET_VALID_BIT_MASK 0x8\r
874#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10\r
875#define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20\r
876#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40\r
877#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80\r
4135253b 878///\r
af2dc6a7 879/// Definition of Platform Specific Error Info Record.\r
4135253b 880///\r
540dfc26 881typedef struct {\r
882 SAL_SEC_HEADER SectionHeader;\r
883 UINT64 ValidationBits;\r
884 UINT64 PlatformErrorStatus;\r
885 UINT64 PlatformRequestorId;\r
886 UINT64 PlatformResponderId;\r
887 UINT64 PlatformTargetId;\r
888 UINT64 PlatformBusSpecificData;\r
889 UINT8 OemComponentId[16];\r
890} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;\r
891\r
1bc5d021 892///\r
af2dc6a7 893/// Union of all the possible SAL Error Record Types.\r
1bc5d021 894///\r
540dfc26 895typedef union {\r
896 SAL_RECORD_HEADER *RecordHeader;\r
897 SAL_PROCESSOR_ERROR_RECORD *SalProcessorRecord;\r
898 SAL_PCI_BUS_ERROR_RECORD *SalPciBusRecord;\r
899 SAL_PCI_COMPONENT_ERROR_RECORD *SalPciComponentRecord;\r
4135253b 900 SAL_SEL_DEVICE_ERROR_RECORD *ImpiRecord;\r
540dfc26 901 SAL_SMBIOS_DEVICE_ERROR_RECORD *SmbiosRecord;\r
902 SAL_PLATFORM_SPECIFIC_ERROR_RECORD *PlatformRecord;\r
903 SAL_MEMORY_ERROR_RECORD *MemoryRecord;\r
904 UINT8 *Raw;\r
905} SAL_ERROR_RECORDS_POINTERS;\r
906\r
766f4bc1 907#pragma pack()\r
908\r
540dfc26 909#endif\r
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