[mirror_edk2.git] / MdePkg / Include / IndustryStandard / SmBios.h

/** @file\r
  Industry Standard Definitions of SMBIOS Table Specification v3.0.0.\r
\r
Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials are licensed and made available under \r
the terms and conditions of the BSD License that accompanies this distribution.  \r
The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php.                                          \r
    \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
**/\r
\r
#ifndef __SMBIOS_STANDARD_H__\r
#define __SMBIOS_STANDARD_H__\r
\r
///\r
/// Reference SMBIOS 2.6, chapter 3.1.2.\r
/// For v2.1 and later, handle values in the range 0FF00h to 0FFFFh are reserved for\r
/// use by this specification.\r
///\r
#define SMBIOS_HANDLE_RESERVED_BEGIN 0xFF00\r
\r
///\r
/// Reference SMBIOS 2.7, chapter 6.1.2.\r
/// The UEFI Platform Initialization Specification reserves handle number FFFEh for its\r
/// EFI_SMBIOS_PROTOCOL.Add() function to mean "assign an unused handle number automatically."\r
/// This number is not used for any other purpose by the SMBIOS specification.\r
///\r
#define SMBIOS_HANDLE_PI_RESERVED 0xFFFE\r
\r
///\r
/// Reference SMBIOS 2.6, chapter 3.1.3.\r
/// Each text string is limited to 64 significant characters due to system MIF limitations.\r
/// Reference SMBIOS 2.7, chapter 6.1.3.\r
/// It will have no limit on the length of each individual text string.\r
///\r
#define SMBIOS_STRING_MAX_LENGTH     64\r
\r
///\r
/// Inactive type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.43.\r
/// Upper-level software that interprets the SMBIOS structure-table should bypass an \r
/// Inactive structure just like a structure type that the software does not recognize.\r
///\r
#define SMBIOS_TYPE_INACTIVE         0x007E    \r
\r
///\r
/// End-of-table type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.44.\r
/// The end-of-table indicator is used in the last physical structure in a table\r
///\r
#define SMBIOS_TYPE_END_OF_TABLE     0x007F\r
\r
///\r
/// Smbios Table Entry Point Structure.\r
///\r
#pragma pack(1)\r
typedef struct {\r
  UINT8   AnchorString[4];\r
  UINT8   EntryPointStructureChecksum;\r
  UINT8   EntryPointLength;\r
  UINT8   MajorVersion;\r
  UINT8   MinorVersion;\r
  UINT16  MaxStructureSize;\r
  UINT8   EntryPointRevision;\r
  UINT8   FormattedArea[5];\r
  UINT8   IntermediateAnchorString[5];\r
  UINT8   IntermediateChecksum;\r
  UINT16  TableLength;\r
  UINT32  TableAddress;\r
  UINT16  NumberOfSmbiosStructures;\r
  UINT8   SmbiosBcdRevision;\r
} SMBIOS_TABLE_ENTRY_POINT;\r
\r
typedef struct {\r
  UINT8   AnchorString[5];\r
  UINT8   EntryPointStructureChecksum;\r
  UINT8   EntryPointLength;\r
  UINT8   MajorVersion;\r
  UINT8   MinorVersion;\r
  UINT8   DocRev;\r
  UINT8   EntryPointRevision;\r
  UINT8   Reserved;\r
  UINT32  TableMaximumSize;\r
  UINT64  TableAddress;\r
} SMBIOS_TABLE_3_0_ENTRY_POINT;\r
\r
///\r
/// The Smbios structure header.\r
///\r
typedef struct {\r
  UINT8   Type;\r
  UINT8   Length;\r
  UINT16  Handle;\r
} SMBIOS_STRUCTURE;\r
\r
///\r
/// String Number for a Null terminated string, 00h stands for no string available.\r
///\r
typedef UINT8 SMBIOS_TABLE_STRING;\r
\r
///\r
/// BIOS Characteristics\r
/// Defines which functions the BIOS supports. PCI, PCMCIA, Flash, etc.\r
///\r
typedef struct {\r
  UINT32  Reserved                          :2;  ///< Bits 0-1.\r
  UINT32  Unknown                           :1;\r
  UINT32  BiosCharacteristicsNotSupported   :1;\r
  UINT32  IsaIsSupported                    :1;\r
  UINT32  McaIsSupported                    :1;\r
  UINT32  EisaIsSupported                   :1;\r
  UINT32  PciIsSupported                    :1;\r
  UINT32  PcmciaIsSupported                 :1;\r
  UINT32  PlugAndPlayIsSupported            :1;\r
  UINT32  ApmIsSupported                    :1;\r
  UINT32  BiosIsUpgradable                  :1;\r
  UINT32  BiosShadowingAllowed              :1;\r
  UINT32  VlVesaIsSupported                 :1;\r
  UINT32  EscdSupportIsAvailable            :1;\r
  UINT32  BootFromCdIsSupported             :1;\r
  UINT32  SelectableBootIsSupported         :1;\r
  UINT32  RomBiosIsSocketed                 :1;\r
  UINT32  BootFromPcmciaIsSupported         :1;\r
  UINT32  EDDSpecificationIsSupported       :1;\r
  UINT32  JapaneseNecFloppyIsSupported      :1;\r
  UINT32  JapaneseToshibaFloppyIsSupported  :1;\r
  UINT32  Floppy525_360IsSupported          :1;\r
  UINT32  Floppy525_12IsSupported           :1;\r
  UINT32  Floppy35_720IsSupported           :1;\r
  UINT32  Floppy35_288IsSupported           :1;\r
  UINT32  PrintScreenIsSupported            :1;\r
  UINT32  Keyboard8042IsSupported           :1;\r
  UINT32  SerialIsSupported                 :1;\r
  UINT32  PrinterIsSupported                :1;\r
  UINT32  CgaMonoIsSupported                :1;\r
  UINT32  NecPc98                           :1;\r
  UINT32  ReservedForVendor                 :32; ///< Bits 32-63. Bits 32-47 reserved for BIOS vendor \r
                                                 ///< and bits 48-63 reserved for System Vendor. \r
} MISC_BIOS_CHARACTERISTICS;\r
\r
///\r
/// BIOS Characteristics Extension Byte 1.\r
/// This information, available for SMBIOS version 2.1 and later, appears at offset 12h\r
/// within the BIOS Information structure.\r
///\r
typedef struct {\r
  UINT8  AcpiIsSupported                   :1;\r
  UINT8  UsbLegacyIsSupported              :1;\r
  UINT8  AgpIsSupported                    :1;\r
  UINT8  I2OBootIsSupported                :1;\r
  UINT8  Ls120BootIsSupported              :1;\r
  UINT8  AtapiZipDriveBootIsSupported      :1;\r
  UINT8  Boot1394IsSupported               :1;\r
  UINT8  SmartBatteryIsSupported           :1;\r
} MBCE_BIOS_RESERVED;\r
\r
///\r
/// BIOS Characteristics Extension Byte 2.\r
/// This information, available for SMBIOS version 2.3 and later, appears at offset 13h\r
/// within the BIOS Information structure.\r
///\r
typedef struct {\r
  UINT8  BiosBootSpecIsSupported              :1;\r
  UINT8  FunctionKeyNetworkBootIsSupported    :1;\r
  UINT8  TargetContentDistributionEnabled     :1;\r
  UINT8  UefiSpecificationSupported           :1;\r
  UINT8  VirtualMachineSupported              :1;\r
  UINT8  ExtensionByte2Reserved               :3;\r
} MBCE_SYSTEM_RESERVED;\r
\r
///\r
/// BIOS Characteristics Extension Bytes.\r
///\r
typedef struct {\r
  MBCE_BIOS_RESERVED    BiosReserved;\r
  MBCE_SYSTEM_RESERVED  SystemReserved;\r
} MISC_BIOS_CHARACTERISTICS_EXTENSION;\r
\r
///\r
/// BIOS Information (Type 0).\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE          Hdr;\r
  SMBIOS_TABLE_STRING       Vendor;\r
  SMBIOS_TABLE_STRING       BiosVersion;\r
  UINT16                    BiosSegment;\r
  SMBIOS_TABLE_STRING       BiosReleaseDate;\r
  UINT8                     BiosSize;\r
  MISC_BIOS_CHARACTERISTICS BiosCharacteristics;\r
  UINT8                     BIOSCharacteristicsExtensionBytes[2];\r
  UINT8                     SystemBiosMajorRelease;\r
  UINT8                     SystemBiosMinorRelease;\r
  UINT8                     EmbeddedControllerFirmwareMajorRelease;\r
  UINT8                     EmbeddedControllerFirmwareMinorRelease;\r
} SMBIOS_TABLE_TYPE0;\r
\r
///\r
///  System Wake-up Type.\r
///\r
typedef enum {  \r
  SystemWakeupTypeReserved         = 0x00,\r
  SystemWakeupTypeOther            = 0x01,\r
  SystemWakeupTypeUnknown          = 0x02,\r
  SystemWakeupTypeApmTimer         = 0x03,\r
  SystemWakeupTypeModemRing        = 0x04,\r
  SystemWakeupTypeLanRemote        = 0x05,\r
  SystemWakeupTypePowerSwitch      = 0x06,\r
  SystemWakeupTypePciPme           = 0x07,\r
  SystemWakeupTypeAcPowerRestored  = 0x08\r
} MISC_SYSTEM_WAKEUP_TYPE;\r
\r
///\r
/// System Information (Type 1).\r
/// \r
/// The information in this structure defines attributes of the overall system and is \r
/// intended to be associated with the Component ID group of the system's MIF.\r
/// An SMBIOS implementation is associated with a single system instance and contains \r
/// one and only one System Information (Type 1) structure.\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE        Hdr;\r
  SMBIOS_TABLE_STRING     Manufacturer;\r
  SMBIOS_TABLE_STRING     ProductName;\r
  SMBIOS_TABLE_STRING     Version;\r
  SMBIOS_TABLE_STRING     SerialNumber;\r
  GUID                    Uuid;\r
  UINT8                   WakeUpType;           ///< The enumeration value from MISC_SYSTEM_WAKEUP_TYPE.\r
  SMBIOS_TABLE_STRING     SKUNumber;\r
  SMBIOS_TABLE_STRING     Family;\r
} SMBIOS_TABLE_TYPE1;\r
\r
///\r
///  Base Board - Feature Flags. \r
///\r
typedef struct {\r
  UINT8  Motherboard           :1;\r
  UINT8  RequiresDaughterCard  :1;\r
  UINT8  Removable             :1;\r
  UINT8  Replaceable           :1;\r
  UINT8  HotSwappable          :1;\r
  UINT8  Reserved              :3;\r
} BASE_BOARD_FEATURE_FLAGS;\r
\r
///\r
///  Base Board - Board Type.\r
///\r
typedef enum {  \r
  BaseBoardTypeUnknown                  = 0x1,\r
  BaseBoardTypeOther                    = 0x2,\r
  BaseBoardTypeServerBlade              = 0x3,\r
  BaseBoardTypeConnectivitySwitch       = 0x4,\r
  BaseBoardTypeSystemManagementModule   = 0x5,\r
  BaseBoardTypeProcessorModule          = 0x6,\r
  BaseBoardTypeIOModule                 = 0x7,\r
  BaseBoardTypeMemoryModule             = 0x8,\r
  BaseBoardTypeDaughterBoard            = 0x9,\r
  BaseBoardTypeMotherBoard              = 0xA,\r
  BaseBoardTypeProcessorMemoryModule    = 0xB,\r
  BaseBoardTypeProcessorIOModule        = 0xC,\r
  BaseBoardTypeInterconnectBoard        = 0xD\r
} BASE_BOARD_TYPE;\r
\r
///\r
/// Base Board (or Module) Information (Type 2).\r
///\r
/// The information in this structure defines attributes of a system baseboard - \r
/// for example a motherboard, planar, or server blade or other standard system module.\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE          Hdr;\r
  SMBIOS_TABLE_STRING       Manufacturer;\r
  SMBIOS_TABLE_STRING       ProductName;\r
  SMBIOS_TABLE_STRING       Version;\r
  SMBIOS_TABLE_STRING       SerialNumber;\r
  SMBIOS_TABLE_STRING       AssetTag;\r
  BASE_BOARD_FEATURE_FLAGS  FeatureFlag;\r
  SMBIOS_TABLE_STRING       LocationInChassis;\r
  UINT16                    ChassisHandle;\r
  UINT8                     BoardType;              ///< The enumeration value from BASE_BOARD_TYPE.\r
  UINT8                     NumberOfContainedObjectHandles;\r
  UINT16                    ContainedObjectHandles[1];\r
} SMBIOS_TABLE_TYPE2;\r
\r
///\r
/// System Enclosure or Chassis Types\r
///\r
typedef enum {  \r
  MiscChassisTypeOther                = 0x01,\r
  MiscChassisTypeUnknown              = 0x02,\r
  MiscChassisTypeDeskTop              = 0x03,\r
  MiscChassisTypeLowProfileDesktop    = 0x04,\r
  MiscChassisTypePizzaBox             = 0x05,\r
  MiscChassisTypeMiniTower            = 0x06,\r
  MiscChassisTypeTower                = 0x07,\r
  MiscChassisTypePortable             = 0x08,\r
  MiscChassisTypeLapTop               = 0x09,\r
  MiscChassisTypeNotebook             = 0x0A,\r
  MiscChassisTypeHandHeld             = 0x0B,\r
  MiscChassisTypeDockingStation       = 0x0C,\r
  MiscChassisTypeAllInOne             = 0x0D,\r
  MiscChassisTypeSubNotebook          = 0x0E,\r
  MiscChassisTypeSpaceSaving          = 0x0F,\r
  MiscChassisTypeLunchBox             = 0x10,\r
  MiscChassisTypeMainServerChassis    = 0x11,\r
  MiscChassisTypeExpansionChassis     = 0x12,\r
  MiscChassisTypeSubChassis           = 0x13,\r
  MiscChassisTypeBusExpansionChassis  = 0x14,\r
  MiscChassisTypePeripheralChassis    = 0x15,\r
  MiscChassisTypeRaidChassis          = 0x16,\r
  MiscChassisTypeRackMountChassis     = 0x17,\r
  MiscChassisTypeSealedCasePc         = 0x18,\r
  MiscChassisMultiSystemChassis       = 0x19,\r
  MiscChassisCompactPCI               = 0x1A,\r
  MiscChassisAdvancedTCA              = 0x1B,\r
  MiscChassisBlade                    = 0x1C,\r
  MiscChassisBladeEnclosure           = 0x1D,\r
  MiscChassisTablet                   = 0x1E,\r
  MiscChassisConvertible              = 0x1F,\r
  MiscChassisDetachable               = 0x20\r
} MISC_CHASSIS_TYPE;\r
\r
///\r
/// System Enclosure or Chassis States .\r
///\r
typedef enum {  \r
  ChassisStateOther           = 0x01,\r
  ChassisStateUnknown         = 0x02,\r
  ChassisStateSafe            = 0x03,\r
  ChassisStateWarning         = 0x04,\r
  ChassisStateCritical        = 0x05,\r
  ChassisStateNonRecoverable  = 0x06\r
} MISC_CHASSIS_STATE;\r
\r
///\r
/// System Enclosure or Chassis Security Status.\r
///\r
typedef enum {  \r
  ChassisSecurityStatusOther                          = 0x01,\r
  ChassisSecurityStatusUnknown                        = 0x02,\r
  ChassisSecurityStatusNone                           = 0x03,\r
  ChassisSecurityStatusExternalInterfaceLockedOut     = 0x04,\r
  ChassisSecurityStatusExternalInterfaceLockedEnabled = 0x05\r
} MISC_CHASSIS_SECURITY_STATE;\r
\r
///\r
/// Contained Element record\r
///\r
typedef struct {\r
  UINT8                 ContainedElementType;\r
  UINT8                 ContainedElementMinimum;\r
  UINT8                 ContainedElementMaximum;\r
} CONTAINED_ELEMENT;\r
\r
\r
///\r
/// System Enclosure or Chassis (Type 3).\r
///\r
/// The information in this structure defines attributes of the system's mechanical enclosure(s).  \r
/// For example, if a system included a separate enclosure for its peripheral devices, \r
/// two structures would be returned: one for the main, system enclosure and the second for\r
/// the peripheral device enclosure.  The additions to this structure in v2.1 of this specification\r
/// support the population of the CIM_Chassis class. \r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE            Hdr;\r
  SMBIOS_TABLE_STRING         Manufacturer;\r
  UINT8                       Type;\r
  SMBIOS_TABLE_STRING         Version;\r
  SMBIOS_TABLE_STRING         SerialNumber;\r
  SMBIOS_TABLE_STRING         AssetTag;\r
  UINT8                       BootupState;            ///< The enumeration value from MISC_CHASSIS_STATE.\r
  UINT8                       PowerSupplyState;       ///< The enumeration value from MISC_CHASSIS_STATE.\r
  UINT8                       ThermalState;           ///< The enumeration value from MISC_CHASSIS_STATE.\r
  UINT8                       SecurityStatus;         ///< The enumeration value from MISC_CHASSIS_SECURITY_STATE.\r
  UINT8                       OemDefined[4];\r
  UINT8                       Height;\r
  UINT8                       NumberofPowerCords;\r
  UINT8                       ContainedElementCount;\r
  UINT8                       ContainedElementRecordLength;\r
  CONTAINED_ELEMENT           ContainedElements[1];\r
} SMBIOS_TABLE_TYPE3;\r
\r
///\r
/// Processor Information - Processor Type.\r
///\r
typedef enum {\r
  ProcessorOther   = 0x01,\r
  ProcessorUnknown = 0x02,\r
  CentralProcessor = 0x03,\r
  MathProcessor    = 0x04,\r
  DspProcessor     = 0x05,\r
  VideoProcessor   = 0x06\r
} PROCESSOR_TYPE_DATA;\r
\r
///\r
/// Processor Information - Processor Family.\r
///\r
typedef enum {\r
  ProcessorFamilyOther                  = 0x01, \r
  ProcessorFamilyUnknown                = 0x02,\r
  ProcessorFamily8086                   = 0x03, \r
  ProcessorFamily80286                  = 0x04,\r
  ProcessorFamilyIntel386               = 0x05, \r
  ProcessorFamilyIntel486               = 0x06,\r
  ProcessorFamily8087                   = 0x07,\r
  ProcessorFamily80287                  = 0x08,\r
  ProcessorFamily80387                  = 0x09, \r
  ProcessorFamily80487                  = 0x0A,\r
  ProcessorFamilyPentium                = 0x0B, \r
  ProcessorFamilyPentiumPro             = 0x0C,\r
  ProcessorFamilyPentiumII              = 0x0D,\r
  ProcessorFamilyPentiumMMX             = 0x0E,\r
  ProcessorFamilyCeleron                = 0x0F,\r
  ProcessorFamilyPentiumIIXeon          = 0x10,\r
  ProcessorFamilyPentiumIII             = 0x11, \r
  ProcessorFamilyM1                     = 0x12,\r
  ProcessorFamilyM2                     = 0x13,\r
  ProcessorFamilyIntelCeleronM          = 0x14,\r
  ProcessorFamilyIntelPentium4Ht        = 0x15,\r
  ProcessorFamilyAmdDuron               = 0x18,\r
  ProcessorFamilyK5                     = 0x19, \r
  ProcessorFamilyK6                     = 0x1A,\r
  ProcessorFamilyK6_2                   = 0x1B,\r
  ProcessorFamilyK6_3                   = 0x1C,\r
  ProcessorFamilyAmdAthlon              = 0x1D,\r
  ProcessorFamilyAmd29000               = 0x1E,\r
  ProcessorFamilyK6_2Plus               = 0x1F,\r
  ProcessorFamilyPowerPC                = 0x20,\r
  ProcessorFamilyPowerPC601             = 0x21,\r
  ProcessorFamilyPowerPC603             = 0x22,\r
  ProcessorFamilyPowerPC603Plus         = 0x23,\r
  ProcessorFamilyPowerPC604             = 0x24,\r
  ProcessorFamilyPowerPC620             = 0x25,\r
  ProcessorFamilyPowerPCx704            = 0x26,\r
  ProcessorFamilyPowerPC750             = 0x27,\r
  ProcessorFamilyIntelCoreDuo           = 0x28,\r
  ProcessorFamilyIntelCoreDuoMobile     = 0x29,\r
  ProcessorFamilyIntelCoreSoloMobile    = 0x2A,\r
  ProcessorFamilyIntelAtom              = 0x2B,\r
  ProcessorFamilyIntelCoreM             = 0x2C,\r
  ProcessorFamilyAlpha                  = 0x30,\r
  ProcessorFamilyAlpha21064             = 0x31,\r
  ProcessorFamilyAlpha21066             = 0x32,\r
  ProcessorFamilyAlpha21164             = 0x33,\r
  ProcessorFamilyAlpha21164PC           = 0x34,\r
  ProcessorFamilyAlpha21164a            = 0x35,\r
  ProcessorFamilyAlpha21264             = 0x36,\r
  ProcessorFamilyAlpha21364             = 0x37,\r
  ProcessorFamilyAmdTurionIIUltraDualCoreMobileM    = 0x38,\r
  ProcessorFamilyAmdTurionIIDualCoreMobileM         = 0x39,\r
  ProcessorFamilyAmdAthlonIIDualCoreM   = 0x3A,\r
  ProcessorFamilyAmdOpteron6100Series   = 0x3B,\r
  ProcessorFamilyAmdOpteron4100Series   = 0x3C,\r
  ProcessorFamilyAmdOpteron6200Series   = 0x3D,\r
  ProcessorFamilyAmdOpteron4200Series   = 0x3E,\r
  ProcessorFamilyAmdFxSeries            = 0x3F,\r
  ProcessorFamilyMips                   = 0x40,\r
  ProcessorFamilyMIPSR4000              = 0x41,\r
  ProcessorFamilyMIPSR4200              = 0x42,\r
  ProcessorFamilyMIPSR4400              = 0x43,\r
  ProcessorFamilyMIPSR4600              = 0x44,\r
  ProcessorFamilyMIPSR10000             = 0x45,\r
  ProcessorFamilyAmdCSeries             = 0x46,\r
  ProcessorFamilyAmdESeries             = 0x47,\r
  ProcessorFamilyAmdASeries             = 0x48,    ///< SMBIOS spec 2.8.0 updated the name\r
  ProcessorFamilyAmdGSeries             = 0x49,\r
  ProcessorFamilyAmdZSeries             = 0x4A,\r
  ProcessorFamilyAmdRSeries             = 0x4B,\r
  ProcessorFamilyAmdOpteron4300         = 0x4C,\r
  ProcessorFamilyAmdOpteron6300         = 0x4D,\r
  ProcessorFamilyAmdOpteron3300         = 0x4E,\r
  ProcessorFamilyAmdFireProSeries       = 0x4F,\r
  ProcessorFamilySparc                  = 0x50,\r
  ProcessorFamilySuperSparc             = 0x51,\r
  ProcessorFamilymicroSparcII           = 0x52,\r
  ProcessorFamilymicroSparcIIep         = 0x53,\r
  ProcessorFamilyUltraSparc             = 0x54,\r
  ProcessorFamilyUltraSparcII           = 0x55,\r
  ProcessorFamilyUltraSparcIii          = 0x56,\r
  ProcessorFamilyUltraSparcIII          = 0x57,\r
  ProcessorFamilyUltraSparcIIIi         = 0x58,\r
  ProcessorFamily68040                  = 0x60,\r
  ProcessorFamily68xxx                  = 0x61,\r
  ProcessorFamily68000                  = 0x62,\r
  ProcessorFamily68010                  = 0x63,\r
  ProcessorFamily68020                  = 0x64,\r
  ProcessorFamily68030                  = 0x65,\r
  ProcessorFamilyAmdAthlonX4QuadCore    = 0x66,\r
  ProcessorFamilyAmdOpteronX1000Series  = 0x67,\r
  ProcessorFamilyAmdOpteronX2000Series  = 0x68,\r
  ProcessorFamilyHobbit                 = 0x70,\r
  ProcessorFamilyCrusoeTM5000           = 0x78,\r
  ProcessorFamilyCrusoeTM3000           = 0x79,\r
  ProcessorFamilyEfficeonTM8000         = 0x7A,\r
  ProcessorFamilyWeitek                 = 0x80,\r
  ProcessorFamilyItanium                = 0x82,\r
  ProcessorFamilyAmdAthlon64            = 0x83,\r
  ProcessorFamilyAmdOpteron             = 0x84,\r
  ProcessorFamilyAmdSempron             = 0x85,\r
  ProcessorFamilyAmdTurion64Mobile      = 0x86,\r
  ProcessorFamilyDualCoreAmdOpteron     = 0x87,\r
  ProcessorFamilyAmdAthlon64X2DualCore  = 0x88,\r
  ProcessorFamilyAmdTurion64X2Mobile    = 0x89,\r
  ProcessorFamilyQuadCoreAmdOpteron     = 0x8A,\r
  ProcessorFamilyThirdGenerationAmdOpteron = 0x8B,\r
  ProcessorFamilyAmdPhenomFxQuadCore    = 0x8C,\r
  ProcessorFamilyAmdPhenomX4QuadCore    = 0x8D,\r
  ProcessorFamilyAmdPhenomX2DualCore    = 0x8E,\r
  ProcessorFamilyAmdAthlonX2DualCore    = 0x8F,  \r
  ProcessorFamilyPARISC                 = 0x90,\r
  ProcessorFamilyPaRisc8500             = 0x91,\r
  ProcessorFamilyPaRisc8000             = 0x92,\r
  ProcessorFamilyPaRisc7300LC           = 0x93,\r
  ProcessorFamilyPaRisc7200             = 0x94,\r
  ProcessorFamilyPaRisc7100LC           = 0x95,\r
  ProcessorFamilyPaRisc7100             = 0x96,\r
  ProcessorFamilyV30                    = 0xA0,\r
  ProcessorFamilyQuadCoreIntelXeon3200Series  = 0xA1,\r
  ProcessorFamilyDualCoreIntelXeon3000Series  = 0xA2,\r
  ProcessorFamilyQuadCoreIntelXeon5300Series  = 0xA3,\r
  ProcessorFamilyDualCoreIntelXeon5100Series  = 0xA4,\r
  ProcessorFamilyDualCoreIntelXeon5000Series  = 0xA5,\r
  ProcessorFamilyDualCoreIntelXeonLV          = 0xA6,\r
  ProcessorFamilyDualCoreIntelXeonULV         = 0xA7,\r
  ProcessorFamilyDualCoreIntelXeon7100Series  = 0xA8,\r
  ProcessorFamilyQuadCoreIntelXeon5400Series  = 0xA9,\r
  ProcessorFamilyQuadCoreIntelXeon            = 0xAA,\r
  ProcessorFamilyDualCoreIntelXeon5200Series  = 0xAB,\r
  ProcessorFamilyDualCoreIntelXeon7200Series  = 0xAC,\r
  ProcessorFamilyQuadCoreIntelXeon7300Series  = 0xAD,\r
  ProcessorFamilyQuadCoreIntelXeon7400Series  = 0xAE,\r
  ProcessorFamilyMultiCoreIntelXeon7400Series = 0xAF,\r
  ProcessorFamilyPentiumIIIXeon         = 0xB0,\r
  ProcessorFamilyPentiumIIISpeedStep    = 0xB1,\r
  ProcessorFamilyPentium4               = 0xB2,\r
  ProcessorFamilyIntelXeon              = 0xB3,\r
  ProcessorFamilyAS400                  = 0xB4,\r
  ProcessorFamilyIntelXeonMP            = 0xB5,\r
  ProcessorFamilyAMDAthlonXP            = 0xB6,\r
  ProcessorFamilyAMDAthlonMP            = 0xB7,\r
  ProcessorFamilyIntelItanium2          = 0xB8,\r
  ProcessorFamilyIntelPentiumM          = 0xB9,\r
  ProcessorFamilyIntelCeleronD          = 0xBA,\r
  ProcessorFamilyIntelPentiumD          = 0xBB,\r
  ProcessorFamilyIntelPentiumEx         = 0xBC,\r
  ProcessorFamilyIntelCoreSolo          = 0xBD,  ///< SMBIOS spec 2.6 updated this value\r
  ProcessorFamilyReserved               = 0xBE,\r
  ProcessorFamilyIntelCore2             = 0xBF,\r
  ProcessorFamilyIntelCore2Solo         = 0xC0,\r
  ProcessorFamilyIntelCore2Extreme      = 0xC1,\r
  ProcessorFamilyIntelCore2Quad         = 0xC2,\r
  ProcessorFamilyIntelCore2ExtremeMobile = 0xC3,\r
  ProcessorFamilyIntelCore2DuoMobile    = 0xC4,\r
  ProcessorFamilyIntelCore2SoloMobile   = 0xC5,\r
  ProcessorFamilyIntelCoreI7            = 0xC6,\r
  ProcessorFamilyDualCoreIntelCeleron   = 0xC7,  \r
  ProcessorFamilyIBM390                 = 0xC8,\r
  ProcessorFamilyG4                     = 0xC9,\r
  ProcessorFamilyG5                     = 0xCA,\r
  ProcessorFamilyG6                     = 0xCB,\r
  ProcessorFamilyzArchitecture          = 0xCC,\r
  ProcessorFamilyIntelCoreI5            = 0xCD,\r
  ProcessorFamilyIntelCoreI3            = 0xCE,\r
  ProcessorFamilyViaC7M                 = 0xD2,\r
  ProcessorFamilyViaC7D                 = 0xD3,\r
  ProcessorFamilyViaC7                  = 0xD4,\r
  ProcessorFamilyViaEden                = 0xD5,\r
  ProcessorFamilyMultiCoreIntelXeon           = 0xD6,\r
  ProcessorFamilyDualCoreIntelXeon3Series     = 0xD7,\r
  ProcessorFamilyQuadCoreIntelXeon3Series     = 0xD8,\r
  ProcessorFamilyViaNano                      = 0xD9,\r
  ProcessorFamilyDualCoreIntelXeon5Series     = 0xDA,\r
  ProcessorFamilyQuadCoreIntelXeon5Series     = 0xDB,\r
  ProcessorFamilyDualCoreIntelXeon7Series     = 0xDD,\r
  ProcessorFamilyQuadCoreIntelXeon7Series     = 0xDE,\r
  ProcessorFamilyMultiCoreIntelXeon7Series    = 0xDF,\r
  ProcessorFamilyMultiCoreIntelXeon3400Series = 0xE0,\r
  ProcessorFamilyAmdOpteron3000Series         = 0xE4,\r
  ProcessorFamilyAmdSempronII                 = 0xE5,\r
  ProcessorFamilyEmbeddedAmdOpteronQuadCore   = 0xE6,\r
  ProcessorFamilyAmdPhenomTripleCore          = 0xE7,\r
  ProcessorFamilyAmdTurionUltraDualCoreMobile = 0xE8,\r
  ProcessorFamilyAmdTurionDualCoreMobile      = 0xE9,\r
  ProcessorFamilyAmdAthlonDualCore            = 0xEA,\r
  ProcessorFamilyAmdSempronSI                 = 0xEB,\r
  ProcessorFamilyAmdPhenomII                  = 0xEC,\r
  ProcessorFamilyAmdAthlonII                  = 0xED,\r
  ProcessorFamilySixCoreAmdOpteron            = 0xEE,\r
  ProcessorFamilyAmdSempronM                  = 0xEF,\r
  ProcessorFamilyi860                   = 0xFA,\r
  ProcessorFamilyi960                   = 0xFB,\r
  ProcessorFamilyIndicatorFamily2       = 0xFE,\r
  ProcessorFamilyReserved1              = 0xFF\r
} PROCESSOR_FAMILY_DATA;\r
\r
///\r
/// Processor Information2 - Processor Family2.\r
///\r
typedef enum {\r
  ProcessorFamilySH3                   = 0x0104,\r
  ProcessorFamilySH4                   = 0x0105,\r
  ProcessorFamilyARM                   = 0x0118,\r
  ProcessorFamilyStrongARM             = 0x0119,\r
  ProcessorFamily6x86                  = 0x012C,\r
  ProcessorFamilyMediaGX               = 0x012D,\r
  ProcessorFamilyMII                   = 0x012E,\r
  ProcessorFamilyWinChip               = 0x0140,\r
  ProcessorFamilyDSP                   = 0x015E,\r
  ProcessorFamilyVideoProcessor        = 0x01F4\r
} PROCESSOR_FAMILY2_DATA;\r
\r
///\r
/// Processor Information - Voltage. \r
///\r
typedef struct {\r
  UINT8  ProcessorVoltageCapability5V        :1; \r
  UINT8  ProcessorVoltageCapability3_3V      :1;  \r
  UINT8  ProcessorVoltageCapability2_9V      :1;  \r
  UINT8  ProcessorVoltageCapabilityReserved  :1; ///< Bit 3, must be zero.\r
  UINT8  ProcessorVoltageReserved            :3; ///< Bits 4-6, must be zero.\r
  UINT8  ProcessorVoltageIndicateLegacy      :1;\r
} PROCESSOR_VOLTAGE;\r
\r
///\r
/// Processor Information - Processor Upgrade.\r
///\r
typedef enum {\r
  ProcessorUpgradeOther         = 0x01,\r
  ProcessorUpgradeUnknown       = 0x02,\r
  ProcessorUpgradeDaughterBoard = 0x03,\r
  ProcessorUpgradeZIFSocket     = 0x04,\r
  ProcessorUpgradePiggyBack     = 0x05, ///< Replaceable.\r
  ProcessorUpgradeNone          = 0x06,\r
  ProcessorUpgradeLIFSocket     = 0x07,\r
  ProcessorUpgradeSlot1         = 0x08,\r
  ProcessorUpgradeSlot2         = 0x09,\r
  ProcessorUpgrade370PinSocket  = 0x0A,\r
  ProcessorUpgradeSlotA         = 0x0B,\r
  ProcessorUpgradeSlotM         = 0x0C,\r
  ProcessorUpgradeSocket423     = 0x0D,\r
  ProcessorUpgradeSocketA       = 0x0E, ///< Socket 462.\r
  ProcessorUpgradeSocket478     = 0x0F,\r
  ProcessorUpgradeSocket754     = 0x10,\r
  ProcessorUpgradeSocket940     = 0x11,\r
  ProcessorUpgradeSocket939     = 0x12,\r
  ProcessorUpgradeSocketmPGA604 = 0x13,\r
  ProcessorUpgradeSocketLGA771  = 0x14,\r
  ProcessorUpgradeSocketLGA775  = 0x15,\r
  ProcessorUpgradeSocketS1      = 0x16,\r
  ProcessorUpgradeAM2           = 0x17,\r
  ProcessorUpgradeF1207         = 0x18,\r
  ProcessorSocketLGA1366        = 0x19,\r
  ProcessorUpgradeSocketG34     = 0x1A,\r
  ProcessorUpgradeSocketAM3     = 0x1B,\r
  ProcessorUpgradeSocketC32     = 0x1C,\r
  ProcessorUpgradeSocketLGA1156 = 0x1D,\r
  ProcessorUpgradeSocketLGA1567 = 0x1E,\r
  ProcessorUpgradeSocketPGA988A = 0x1F,\r
  ProcessorUpgradeSocketBGA1288 = 0x20,\r
  ProcessorUpgradeSocketrPGA988B = 0x21,\r
  ProcessorUpgradeSocketBGA1023 = 0x22,\r
  ProcessorUpgradeSocketBGA1224 = 0x23,\r
  ProcessorUpgradeSocketLGA1155 = 0x24,  ///< SMBIOS spec 2.8.0 updated the name\r
  ProcessorUpgradeSocketLGA1356 = 0x25,\r
  ProcessorUpgradeSocketLGA2011 = 0x26,\r
  ProcessorUpgradeSocketFS1     = 0x27,\r
  ProcessorUpgradeSocketFS2     = 0x28,\r
  ProcessorUpgradeSocketFM1     = 0x29,\r
  ProcessorUpgradeSocketFM2     = 0x2A,\r
  ProcessorUpgradeSocketLGA2011_3 = 0x2B,\r
  ProcessorUpgradeSocketLGA1356_3 = 0x2C,\r
  ProcessorUpgradeSocketLGA1150   = 0x2D,\r
  ProcessorUpgradeSocketBGA1168   = 0x2E,\r
  ProcessorUpgradeSocketBGA1234   = 0x2F,\r
  ProcessorUpgradeSocketBGA1364   = 0x30\r
} PROCESSOR_UPGRADE;\r
\r
///\r
/// Processor ID Field Description\r
///\r
typedef struct {\r
  UINT32  ProcessorSteppingId:4;\r
  UINT32  ProcessorModel:     4;\r
  UINT32  ProcessorFamily:    4;\r
  UINT32  ProcessorType:      2;\r
  UINT32  ProcessorReserved1: 2;\r
  UINT32  ProcessorXModel:    4;\r
  UINT32  ProcessorXFamily:   8;\r
  UINT32  ProcessorReserved2: 4;\r
} PROCESSOR_SIGNATURE;\r
\r
typedef struct {\r
  UINT32  ProcessorFpu       :1;\r
  UINT32  ProcessorVme       :1;\r
  UINT32  ProcessorDe        :1;\r
  UINT32  ProcessorPse       :1;\r
  UINT32  ProcessorTsc       :1;\r
  UINT32  ProcessorMsr       :1;\r
  UINT32  ProcessorPae       :1;\r
  UINT32  ProcessorMce       :1;\r
  UINT32  ProcessorCx8       :1;\r
  UINT32  ProcessorApic      :1;\r
  UINT32  ProcessorReserved1 :1;\r
  UINT32  ProcessorSep       :1;\r
  UINT32  ProcessorMtrr      :1;\r
  UINT32  ProcessorPge       :1;\r
  UINT32  ProcessorMca       :1;\r
  UINT32  ProcessorCmov      :1;\r
  UINT32  ProcessorPat       :1;\r
  UINT32  ProcessorPse36     :1;\r
  UINT32  ProcessorPsn       :1;\r
  UINT32  ProcessorClfsh     :1;\r
  UINT32  ProcessorReserved2 :1;\r
  UINT32  ProcessorDs        :1;\r
  UINT32  ProcessorAcpi      :1;\r
  UINT32  ProcessorMmx       :1;\r
  UINT32  ProcessorFxsr      :1;\r
  UINT32  ProcessorSse       :1;\r
  UINT32  ProcessorSse2      :1;\r
  UINT32  ProcessorSs        :1;\r
  UINT32  ProcessorReserved3 :1;\r
  UINT32  ProcessorTm        :1;\r
  UINT32  ProcessorReserved4 :2;\r
} PROCESSOR_FEATURE_FLAGS;\r
\r
typedef struct {\r
  PROCESSOR_SIGNATURE     Signature;\r
  PROCESSOR_FEATURE_FLAGS FeatureFlags;\r
} PROCESSOR_ID_DATA;\r
\r
///\r
/// Processor Information (Type 4).\r
///\r
/// The information in this structure defines the attributes of a single processor; \r
/// a separate structure instance is provided for each system processor socket/slot. \r
/// For example, a system with an IntelDX2 processor would have a single \r
/// structure instance, while a system with an IntelSX2 processor would have a structure\r
/// to describe the main CPU, and a second structure to describe the 80487 co-processor. \r
///\r
typedef struct { \r
  SMBIOS_STRUCTURE      Hdr;\r
  SMBIOS_TABLE_STRING   Socket;\r
  UINT8                 ProcessorType;          ///< The enumeration value from PROCESSOR_TYPE_DATA.\r
  UINT8                 ProcessorFamily;        ///< The enumeration value from PROCESSOR_FAMILY_DATA.\r
  SMBIOS_TABLE_STRING   ProcessorManufacture;\r
  PROCESSOR_ID_DATA     ProcessorId;\r
  SMBIOS_TABLE_STRING   ProcessorVersion;\r
  PROCESSOR_VOLTAGE     Voltage;\r
  UINT16                ExternalClock;\r
  UINT16                MaxSpeed;\r
  UINT16                CurrentSpeed;\r
  UINT8                 Status;\r
  UINT8                 ProcessorUpgrade;      ///< The enumeration value from PROCESSOR_UPGRADE.\r
  UINT16                L1CacheHandle;\r
  UINT16                L2CacheHandle;\r
  UINT16                L3CacheHandle;\r
  SMBIOS_TABLE_STRING   SerialNumber;\r
  SMBIOS_TABLE_STRING   AssetTag;\r
  SMBIOS_TABLE_STRING   PartNumber;\r
  //\r
  // Add for smbios 2.5\r
  //\r
  UINT8                 CoreCount;\r
  UINT8                 EnabledCoreCount;\r
  UINT8                 ThreadCount;\r
  UINT16                ProcessorCharacteristics;\r
  //\r
  // Add for smbios 2.6\r
  //\r
  UINT16                ProcessorFamily2;\r
  //\r
  // Add for smbios 3.0\r
  //\r
  UINT16                CoreCount2;\r
  UINT16                EnabledCoreCount2;\r
  UINT16                ThreadCount2;\r
} SMBIOS_TABLE_TYPE4;\r
\r
///\r
/// Memory Controller Error Detecting Method.\r
///\r
typedef enum {  \r
  ErrorDetectingMethodOther   = 0x01,\r
  ErrorDetectingMethodUnknown = 0x02,\r
  ErrorDetectingMethodNone    = 0x03,\r
  ErrorDetectingMethodParity  = 0x04,\r
  ErrorDetectingMethod32Ecc   = 0x05,\r
  ErrorDetectingMethod64Ecc   = 0x06,\r
  ErrorDetectingMethod128Ecc  = 0x07,\r
  ErrorDetectingMethodCrc     = 0x08\r
} MEMORY_ERROR_DETECT_METHOD;\r
\r
///\r
/// Memory Controller Error Correcting Capability.\r
///\r
typedef struct {\r
  UINT8  Other                 :1;\r
  UINT8  Unknown               :1;\r
  UINT8  None                  :1;\r
  UINT8  SingleBitErrorCorrect :1;\r
  UINT8  DoubleBitErrorCorrect :1;\r
  UINT8  ErrorScrubbing        :1;\r
  UINT8  Reserved              :2;\r
} MEMORY_ERROR_CORRECT_CAPABILITY;\r
\r
///\r
/// Memory Controller Information - Interleave Support.\r
///\r
typedef enum {  \r
  MemoryInterleaveOther      = 0x01,\r
  MemoryInterleaveUnknown    = 0x02,\r
  MemoryInterleaveOneWay     = 0x03,\r
  MemoryInterleaveTwoWay     = 0x04,\r
  MemoryInterleaveFourWay    = 0x05,\r
  MemoryInterleaveEightWay   = 0x06,\r
  MemoryInterleaveSixteenWay = 0x07\r
} MEMORY_SUPPORT_INTERLEAVE_TYPE;\r
\r
///\r
/// Memory Controller Information - Memory Speeds.\r
///\r
typedef struct {\r
  UINT16     Other    :1;\r
  UINT16     Unknown  :1;\r
  UINT16     SeventyNs:1;\r
  UINT16     SixtyNs  :1;\r
  UINT16     FiftyNs  :1;\r
  UINT16     Reserved :11;\r
} MEMORY_SPEED_TYPE;\r
\r
///\r
/// Memory Controller Information (Type 5, Obsolete).\r
///\r
/// The information in this structure defines the attributes of the system's memory controller(s) \r
/// and the supported attributes of any memory-modules present in the sockets controlled by \r
/// this controller. \r
/// Note: This structure, and its companion Memory Module Information (Type 6, Obsolete), \r
/// are obsolete starting with version 2.1 of this specification. The Physical Memory Array (Type 16)\r
/// and Memory Device (Type 17) structures should be used instead.  BIOS providers might\r
/// choose to implement both memory description types to allow existing DMI browsers\r
/// to properly display the system's memory attributes.\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE                Hdr;\r
  UINT8                           ErrDetectMethod;            ///< The enumeration value from MEMORY_ERROR_DETECT_METHOD.\r
  MEMORY_ERROR_CORRECT_CAPABILITY ErrCorrectCapability;\r
  UINT8                           SupportInterleave;          ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE.\r
  UINT8                           CurrentInterleave;          ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE .     \r
  UINT8                           MaxMemoryModuleSize;\r
  MEMORY_SPEED_TYPE               SupportSpeed;\r
  UINT16                          SupportMemoryType;\r
  UINT8                           MemoryModuleVoltage;\r
  UINT8                           AssociatedMemorySlotNum;\r
  UINT16                          MemoryModuleConfigHandles[1];\r
} SMBIOS_TABLE_TYPE5;\r
\r
///\r
/// Memory Module Information - Memory Types\r
///\r
typedef struct {\r
  UINT16  Other       :1;\r
  UINT16  Unknown     :1;\r
  UINT16  Standard    :1;\r
  UINT16  FastPageMode:1;\r
  UINT16  Edo         :1;\r
  UINT16  Parity      :1;\r
  UINT16  Ecc         :1;\r
  UINT16  Simm        :1;\r
  UINT16  Dimm        :1;\r
  UINT16  BurstEdo    :1;\r
  UINT16  Sdram       :1;\r
  UINT16  Reserved    :5;\r
} MEMORY_CURRENT_TYPE;\r
\r
///\r
/// Memory Module Information - Memory Size.\r
///\r
typedef struct {\r
  UINT8   InstalledOrEnabledSize  :7; ///< Size (n), where 2**n is the size in MB.\r
  UINT8   SingleOrDoubleBank      :1;\r
} MEMORY_INSTALLED_ENABLED_SIZE;\r
\r
///\r
/// Memory Module Information (Type 6, Obsolete)\r
///\r
/// One Memory Module Information structure is included for each memory-module socket \r
/// in the system.  The structure describes the speed, type, size, and error status\r
/// of each system memory module.  The supported attributes of each module are described \r
/// by the "owning" Memory Controller Information structure.  \r
/// Note:  This structure, and its companion Memory Controller Information (Type 5, Obsolete), \r
/// are obsolete starting with version 2.1 of this specification. The Physical Memory Array (Type 16)\r
/// and Memory Device (Type 17) structures should be used instead.\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE              Hdr;\r
  SMBIOS_TABLE_STRING           SocketDesignation;\r
  UINT8                         BankConnections;\r
  UINT8                         CurrentSpeed;\r
  MEMORY_CURRENT_TYPE           CurrentMemoryType;\r
  MEMORY_INSTALLED_ENABLED_SIZE InstalledSize;\r
  MEMORY_INSTALLED_ENABLED_SIZE EnabledSize;\r
  UINT8                         ErrorStatus;\r
} SMBIOS_TABLE_TYPE6;\r
\r
///\r
/// Cache Information - SRAM Type.\r
///\r
typedef struct {\r
  UINT16  Other         :1;\r
  UINT16  Unknown       :1;\r
  UINT16  NonBurst      :1;\r
  UINT16  Burst         :1;\r
  UINT16  PipelineBurst :1;\r
  UINT16  Synchronous   :1;\r
  UINT16  Asynchronous  :1;\r
  UINT16  Reserved      :9;\r
} CACHE_SRAM_TYPE_DATA;\r
\r
///\r
/// Cache Information - Error Correction Type.\r
///\r
typedef enum {\r
  CacheErrorOther     = 0x01,\r
  CacheErrorUnknown   = 0x02,\r
  CacheErrorNone      = 0x03,\r
  CacheErrorParity    = 0x04,\r
  CacheErrorSingleBit = 0x05, ///< ECC\r
  CacheErrorMultiBit  = 0x06  ///< ECC\r
} CACHE_ERROR_TYPE_DATA;\r
\r
///\r
/// Cache Information - System Cache Type. \r
///\r
typedef enum {\r
  CacheTypeOther       = 0x01,\r
  CacheTypeUnknown     = 0x02,\r
  CacheTypeInstruction = 0x03,\r
  CacheTypeData        = 0x04,\r
  CacheTypeUnified     = 0x05\r
} CACHE_TYPE_DATA;\r
\r
///\r
/// Cache Information - Associativity. \r
///\r
typedef enum {\r
  CacheAssociativityOther        = 0x01,\r
  CacheAssociativityUnknown      = 0x02,\r
  CacheAssociativityDirectMapped = 0x03,\r
  CacheAssociativity2Way         = 0x04,\r
  CacheAssociativity4Way         = 0x05,\r
  CacheAssociativityFully        = 0x06,\r
  CacheAssociativity8Way         = 0x07,\r
  CacheAssociativity16Way        = 0x08,\r
  CacheAssociativity12Way        = 0x09,\r
  CacheAssociativity24Way        = 0x0A,\r
  CacheAssociativity32Way        = 0x0B,\r
  CacheAssociativity48Way        = 0x0C,\r
  CacheAssociativity64Way        = 0x0D,\r
  CacheAssociativity20Way        = 0x0E\r
} CACHE_ASSOCIATIVITY_DATA;\r
\r
///\r
/// Cache Information (Type 7).\r
///\r
/// The information in this structure defines the attributes of CPU cache device in the system. \r
/// One structure is specified for each such device, whether the device is internal to\r
/// or external to the CPU module.  Cache modules can be associated with a processor structure\r
/// in one or two ways, depending on the SMBIOS version.\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE          Hdr;\r
  SMBIOS_TABLE_STRING       SocketDesignation;\r
  UINT16                    CacheConfiguration;\r
  UINT16                    MaximumCacheSize;\r
  UINT16                    InstalledSize;\r
  CACHE_SRAM_TYPE_DATA      SupportedSRAMType;\r
  CACHE_SRAM_TYPE_DATA      CurrentSRAMType;\r
  UINT8                     CacheSpeed;\r
  UINT8                     ErrorCorrectionType;            ///< The enumeration value from CACHE_ERROR_TYPE_DATA.\r
  UINT8                     SystemCacheType;                ///< The enumeration value from CACHE_TYPE_DATA.\r
  UINT8                     Associativity;                  ///< The enumeration value from CACHE_ASSOCIATIVITY_DATA.\r
} SMBIOS_TABLE_TYPE7;\r
\r
///\r
/// Port Connector Information - Connector Types. \r
///\r
typedef enum {\r
  PortConnectorTypeNone                   = 0x00,\r
  PortConnectorTypeCentronics             = 0x01,\r
  PortConnectorTypeMiniCentronics         = 0x02,\r
  PortConnectorTypeProprietary            = 0x03,\r
  PortConnectorTypeDB25Male               = 0x04,\r
  PortConnectorTypeDB25Female             = 0x05,\r
  PortConnectorTypeDB15Male               = 0x06,\r
  PortConnectorTypeDB15Female             = 0x07,\r
  PortConnectorTypeDB9Male                = 0x08,\r
  PortConnectorTypeDB9Female              = 0x09,\r
  PortConnectorTypeRJ11                   = 0x0A,\r
  PortConnectorTypeRJ45                   = 0x0B,\r
  PortConnectorType50PinMiniScsi          = 0x0C,\r
  PortConnectorTypeMiniDin                = 0x0D,\r
  PortConnectorTypeMicroDin               = 0x0E,\r
  PortConnectorTypePS2                    = 0x0F,\r
  PortConnectorTypeInfrared               = 0x10,\r
  PortConnectorTypeHpHil                  = 0x11,\r
  PortConnectorTypeUsb                    = 0x12,\r
  PortConnectorTypeSsaScsi                = 0x13,\r
  PortConnectorTypeCircularDin8Male       = 0x14,\r
  PortConnectorTypeCircularDin8Female     = 0x15,\r
  PortConnectorTypeOnboardIde             = 0x16,\r
  PortConnectorTypeOnboardFloppy          = 0x17,\r
  PortConnectorType9PinDualInline         = 0x18,\r
  PortConnectorType25PinDualInline        = 0x19,\r
  PortConnectorType50PinDualInline        = 0x1A,\r
  PortConnectorType68PinDualInline        = 0x1B,\r
  PortConnectorTypeOnboardSoundInput      = 0x1C,\r
  PortConnectorTypeMiniCentronicsType14   = 0x1D,\r
  PortConnectorTypeMiniCentronicsType26   = 0x1E,\r
  PortConnectorTypeHeadPhoneMiniJack      = 0x1F,\r
  PortConnectorTypeBNC                    = 0x20,\r
  PortConnectorType1394                   = 0x21,\r
  PortConnectorTypeSasSata                = 0x22,\r
  PortConnectorTypePC98                   = 0xA0,\r
  PortConnectorTypePC98Hireso             = 0xA1,\r
  PortConnectorTypePCH98                  = 0xA2,\r
  PortConnectorTypePC98Note               = 0xA3,\r
  PortConnectorTypePC98Full               = 0xA4,\r
  PortConnectorTypeOther                  = 0xFF\r
} MISC_PORT_CONNECTOR_TYPE;\r
\r
///\r
/// Port Connector Information - Port Types \r
///\r
typedef enum {\r
  PortTypeNone                      = 0x00,\r
  PortTypeParallelXtAtCompatible    = 0x01,\r
  PortTypeParallelPortPs2           = 0x02,\r
  PortTypeParallelPortEcp           = 0x03,\r
  PortTypeParallelPortEpp           = 0x04,\r
  PortTypeParallelPortEcpEpp        = 0x05,\r
  PortTypeSerialXtAtCompatible      = 0x06,\r
  PortTypeSerial16450Compatible     = 0x07,\r
  PortTypeSerial16550Compatible     = 0x08,\r
  PortTypeSerial16550ACompatible    = 0x09,\r
  PortTypeScsi                      = 0x0A,\r
  PortTypeMidi                      = 0x0B,\r
  PortTypeJoyStick                  = 0x0C,\r
  PortTypeKeyboard                  = 0x0D,\r
  PortTypeMouse                     = 0x0E,\r
  PortTypeSsaScsi                   = 0x0F,\r
  PortTypeUsb                       = 0x10,\r
  PortTypeFireWire                  = 0x11,\r
  PortTypePcmciaTypeI               = 0x12,\r
  PortTypePcmciaTypeII              = 0x13,\r
  PortTypePcmciaTypeIII             = 0x14,\r
  PortTypeCardBus                   = 0x15,\r
  PortTypeAccessBusPort             = 0x16,\r
  PortTypeScsiII                    = 0x17,\r
  PortTypeScsiWide                  = 0x18,\r
  PortTypePC98                      = 0x19,\r
  PortTypePC98Hireso                = 0x1A,\r
  PortTypePCH98                     = 0x1B,\r
  PortTypeVideoPort                 = 0x1C,\r
  PortTypeAudioPort                 = 0x1D,\r
  PortTypeModemPort                 = 0x1E,\r
  PortTypeNetworkPort               = 0x1F,\r
  PortType8251Compatible            = 0xA0,\r
  PortType8251FifoCompatible        = 0xA1,\r
  PortTypeOther                     = 0xFF\r
} MISC_PORT_TYPE;\r
\r
///\r
/// Port Connector Information (Type 8).\r
///\r
/// The information in this structure defines the attributes of a system port connector, \r
/// e.g. parallel, serial, keyboard, or mouse ports.  The port's type and connector information \r
/// are provided. One structure is present for each port provided by the system.\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE          Hdr;\r
  SMBIOS_TABLE_STRING       InternalReferenceDesignator;\r
  UINT8                     InternalConnectorType;          ///< The enumeration value from MISC_PORT_CONNECTOR_TYPE.\r
  SMBIOS_TABLE_STRING       ExternalReferenceDesignator;\r
  UINT8                     ExternalConnectorType;          ///< The enumeration value from MISC_PORT_CONNECTOR_TYPE.\r
  UINT8                     PortType;                       ///< The enumeration value from MISC_PORT_TYPE.\r
} SMBIOS_TABLE_TYPE8;\r
\r
///\r
/// System Slots - Slot Type\r
///\r
typedef enum {\r
  SlotTypeOther                        = 0x01,\r
  SlotTypeUnknown                      = 0x02,\r
  SlotTypeIsa                          = 0x03,\r
  SlotTypeMca                          = 0x04,\r
  SlotTypeEisa                         = 0x05,\r
  SlotTypePci                          = 0x06,\r
  SlotTypePcmcia                       = 0x07,\r
  SlotTypeVlVesa                       = 0x08,\r
  SlotTypeProprietary                  = 0x09,\r
  SlotTypeProcessorCardSlot            = 0x0A,\r
  SlotTypeProprietaryMemoryCardSlot    = 0x0B,\r
  SlotTypeIORiserCardSlot              = 0x0C,\r
  SlotTypeNuBus                        = 0x0D,\r
  SlotTypePci66MhzCapable              = 0x0E,\r
  SlotTypeAgp                          = 0x0F,\r
  SlotTypeApg2X                        = 0x10,\r
  SlotTypeAgp4X                        = 0x11,\r
  SlotTypePciX                         = 0x12,\r
  SlotTypeAgp8X                        = 0x13,\r
  SlotTypeM2Socket1_DP                 = 0x14,\r
  SlotTypeM2Socket1_SD                 = 0x15,\r
  SlotTypeM2Socket2                    = 0x16,\r
  SlotTypeM2Socket3                    = 0x17,\r
  SlotTypeMxmTypeI                     = 0x18,\r
  SlotTypeMxmTypeII                    = 0x19,\r
  SlotTypeMxmTypeIIIStandard           = 0x1A,\r
  SlotTypeMxmTypeIIIHe                 = 0x1B,\r
  SlotTypeMxmTypeIV                    = 0x1C,\r
  SlotTypeMxm30TypeA                   = 0x1D,\r
  SlotTypeMxm30TypeB                   = 0x1E,\r
  SlotTypePciExpressGen2Sff_8639       = 0x1F,\r
  SlotTypePciExpressGen3Sff_8639       = 0x20,\r
  SlotTypePC98C20                      = 0xA0,\r
  SlotTypePC98C24                      = 0xA1,\r
  SlotTypePC98E                        = 0xA2,\r
  SlotTypePC98LocalBus                 = 0xA3,\r
  SlotTypePC98Card                     = 0xA4,\r
  SlotTypePciExpress                   = 0xA5,\r
  SlotTypePciExpressX1                 = 0xA6,\r
  SlotTypePciExpressX2                 = 0xA7,\r
  SlotTypePciExpressX4                 = 0xA8,\r
  SlotTypePciExpressX8                 = 0xA9,\r
  SlotTypePciExpressX16                = 0xAA,\r
  SlotTypePciExpressGen2               = 0xAB,\r
  SlotTypePciExpressGen2X1             = 0xAC,\r
  SlotTypePciExpressGen2X2             = 0xAD,\r
  SlotTypePciExpressGen2X4             = 0xAE,\r
  SlotTypePciExpressGen2X8             = 0xAF,\r
  SlotTypePciExpressGen2X16            = 0xB0,\r
  SlotTypePciExpressGen3               = 0xB1,\r
  SlotTypePciExpressGen3X1             = 0xB2,\r
  SlotTypePciExpressGen3X2             = 0xB3,\r
  SlotTypePciExpressGen3X4             = 0xB4,\r
  SlotTypePciExpressGen3X8             = 0xB5,\r
  SlotTypePciExpressGen3X16            = 0xB6\r
} MISC_SLOT_TYPE;\r
\r
///\r
/// System Slots - Slot Data Bus Width.\r
///\r
typedef enum {\r
  SlotDataBusWidthOther      = 0x01,\r
  SlotDataBusWidthUnknown    = 0x02,\r
  SlotDataBusWidth8Bit       = 0x03,\r
  SlotDataBusWidth16Bit      = 0x04,\r
  SlotDataBusWidth32Bit      = 0x05,\r
  SlotDataBusWidth64Bit      = 0x06,\r
  SlotDataBusWidth128Bit     = 0x07,\r
  SlotDataBusWidth1X         = 0x08, ///< Or X1\r
  SlotDataBusWidth2X         = 0x09, ///< Or X2\r
  SlotDataBusWidth4X         = 0x0A, ///< Or X4\r
  SlotDataBusWidth8X         = 0x0B, ///< Or X8\r
  SlotDataBusWidth12X        = 0x0C, ///< Or X12\r
  SlotDataBusWidth16X        = 0x0D, ///< Or X16\r
  SlotDataBusWidth32X        = 0x0E  ///< Or X32\r
} MISC_SLOT_DATA_BUS_WIDTH;\r
\r
///\r
/// System Slots - Current Usage.\r
///\r
typedef enum {\r
  SlotUsageOther     = 0x01,\r
  SlotUsageUnknown   = 0x02,\r
  SlotUsageAvailable = 0x03,\r
  SlotUsageInUse     = 0x04\r
} MISC_SLOT_USAGE;\r
\r
///\r
/// System Slots - Slot Length. \r
///\r
typedef enum {\r
  SlotLengthOther   = 0x01,\r
  SlotLengthUnknown = 0x02,\r
  SlotLengthShort   = 0x03,\r
  SlotLengthLong    = 0x04\r
} MISC_SLOT_LENGTH;\r
\r
///\r
/// System Slots - Slot Characteristics 1. \r
///\r
typedef struct {\r
  UINT8  CharacteristicsUnknown  :1;\r
  UINT8  Provides50Volts         :1;\r
  UINT8  Provides33Volts         :1;\r
  UINT8  SharedSlot              :1;\r
  UINT8  PcCard16Supported       :1;\r
  UINT8  CardBusSupported        :1;\r
  UINT8  ZoomVideoSupported      :1;\r
  UINT8  ModemRingResumeSupported:1;\r
} MISC_SLOT_CHARACTERISTICS1;\r
///\r
/// System Slots - Slot Characteristics 2.  \r
///\r
typedef struct {\r
  UINT8  PmeSignalSupported      :1;\r
  UINT8  HotPlugDevicesSupported :1;\r
  UINT8  SmbusSignalSupported    :1;\r
  UINT8  Reserved                :5;  ///< Set to 0.\r
} MISC_SLOT_CHARACTERISTICS2;\r
\r
///\r
/// System Slots (Type 9)\r
///\r
/// The information in this structure defines the attributes of a system slot. \r
/// One structure is provided for each slot in the system.\r
///\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE            Hdr;\r
  SMBIOS_TABLE_STRING         SlotDesignation;\r
  UINT8                       SlotType;                 ///< The enumeration value from MISC_SLOT_TYPE.\r
  UINT8                       SlotDataBusWidth;         ///< The enumeration value from MISC_SLOT_DATA_BUS_WIDTH.\r
  UINT8                       CurrentUsage;             ///< The enumeration value from MISC_SLOT_USAGE.\r
  UINT8                       SlotLength;               ///< The enumeration value from MISC_SLOT_LENGTH.\r
  UINT16                      SlotID;\r
  MISC_SLOT_CHARACTERISTICS1  SlotCharacteristics1;\r
  MISC_SLOT_CHARACTERISTICS2  SlotCharacteristics2;\r
  //\r
  // Add for smbios 2.6\r
  //\r
  UINT16                      SegmentGroupNum;\r
  UINT8                       BusNum;\r
  UINT8                       DevFuncNum;\r
} SMBIOS_TABLE_TYPE9;\r
\r
///\r
/// On Board Devices Information - Device Types. \r
///\r
typedef enum {\r
  OnBoardDeviceTypeOther          = 0x01,\r
  OnBoardDeviceTypeUnknown        = 0x02,\r
  OnBoardDeviceTypeVideo          = 0x03,\r
  OnBoardDeviceTypeScsiController = 0x04,\r
  OnBoardDeviceTypeEthernet       = 0x05,\r
  OnBoardDeviceTypeTokenRing      = 0x06,\r
  OnBoardDeviceTypeSound          = 0x07,\r
  OnBoardDeviceTypePATAController = 0x08,\r
  OnBoardDeviceTypeSATAController = 0x09,\r
  OnBoardDeviceTypeSASController  = 0x0A\r
} MISC_ONBOARD_DEVICE_TYPE;\r
\r
///\r
/// Device Item Entry\r
///\r
typedef struct {\r
  UINT8                     DeviceType;             ///< Bit [6:0] - enumeration type of device from MISC_ONBOARD_DEVICE_TYPE.\r
                                                    ///< Bit 7     - 1 : device enabled, 0 : device disabled.\r
  SMBIOS_TABLE_STRING       DescriptionString;\r
} DEVICE_STRUCT;\r
\r
///\r
/// On Board Devices Information (Type 10, obsolete).\r
///\r
/// Note: This structure is obsolete starting with version 2.6 specification; the Onboard Devices Extended \r
/// Information (Type 41) structure should be used instead . BIOS providers can choose to implement both \r
/// types to allow existing SMBIOS browsers to properly display the system's onboard devices information.  \r
/// The information in this structure defines the attributes of devices that are onboard (soldered onto) \r
/// a system element, usually the baseboard.  In general, an entry in this table implies that the BIOS\r
/// has some level of control over the enabling of the associated device for use by the system.\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE      Hdr;\r
  DEVICE_STRUCT         Device[1];\r
} SMBIOS_TABLE_TYPE10;\r
\r
///\r
/// OEM Strings (Type 11).\r
/// This structure contains free form strings defined by the OEM. Examples of this are: \r
/// Part Numbers for Reference Documents for the system, contact information for the manufacturer, etc. \r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE      Hdr;\r
  UINT8                 StringCount;\r
} SMBIOS_TABLE_TYPE11;\r
\r
///\r
/// System Configuration Options (Type 12).\r
///\r
/// This structure contains information required to configure the base board's Jumpers and Switches. \r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE      Hdr;\r
  UINT8                 StringCount;\r
} SMBIOS_TABLE_TYPE12;\r
\r
\r
///\r
/// BIOS Language Information (Type 13).\r
///\r
/// The information in this structure defines the installable language attributes of the BIOS.  \r
/// \r
typedef struct {\r
  SMBIOS_STRUCTURE      Hdr;\r
  UINT8                 InstallableLanguages;\r
  UINT8                 Flags;\r
  UINT8                 Reserved[15];\r
  SMBIOS_TABLE_STRING   CurrentLanguages;\r
} SMBIOS_TABLE_TYPE13;\r
\r
///\r
/// Group Item Entry\r
///\r
typedef struct {\r
  UINT8                 ItemType;\r
  UINT16                ItemHandle;\r
} GROUP_STRUCT;\r
\r
///\r
/// Group Associations (Type 14).\r
///\r
/// The Group Associations structure is provided for OEMs who want to specify \r
/// the arrangement or hierarchy of certain components (including other Group Associations) \r
/// within the system. \r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE      Hdr;\r
  SMBIOS_TABLE_STRING   GroupName;\r
  GROUP_STRUCT          Group[1];\r
} SMBIOS_TABLE_TYPE14;\r
\r
///\r
/// System Event Log - Event Log Types.\r
/// \r
typedef enum {\r
  EventLogTypeReserved         = 0x00,\r
  EventLogTypeSingleBitECC     = 0x01,\r
  EventLogTypeMultiBitECC      = 0x02,\r
  EventLogTypeParityMemErr     = 0x03,\r
  EventLogTypeBusTimeOut       = 0x04,\r
  EventLogTypeIOChannelCheck   = 0x05,\r
  EventLogTypeSoftwareNMI      = 0x06,\r
  EventLogTypePOSTMemResize    = 0x07,\r
  EventLogTypePOSTErr          = 0x08,\r
  EventLogTypePCIParityErr     = 0x09,\r
  EventLogTypePCISystemErr     = 0x0A,\r
  EventLogTypeCPUFailure       = 0x0B,\r
  EventLogTypeEISATimeOut      = 0x0C,\r
  EventLogTypeMemLogDisabled   = 0x0D,\r
  EventLogTypeLoggingDisabled  = 0x0E,\r
  EventLogTypeSysLimitExce     = 0x10,\r
  EventLogTypeAsyncHWTimer     = 0x11,\r
  EventLogTypeSysConfigInfo    = 0x12,\r
  EventLogTypeHDInfo           = 0x13,\r
  EventLogTypeSysReconfig      = 0x14,\r
  EventLogTypeUncorrectCPUErr  = 0x15,\r
  EventLogTypeAreaResetAndClr  = 0x16,\r
  EventLogTypeSystemBoot       = 0x17,\r
  EventLogTypeUnused           = 0x18, ///< 0x18 - 0x7F\r
  EventLogTypeAvailForSys      = 0x80, ///< 0x80 - 0xFE\r
  EventLogTypeEndOfLog         = 0xFF\r
} EVENT_LOG_TYPE_DATA;\r
\r
///\r
/// System Event Log - Variable Data Format Types. \r
/// \r
typedef enum {\r
  EventLogVariableNone                        = 0x00,\r
  EventLogVariableHandle                      = 0x01,\r
  EventLogVariableMutilEvent                  = 0x02,\r
  EventLogVariableMutilEventHandle            = 0x03,\r
  EventLogVariablePOSTResultBitmap            = 0x04,\r
  EventLogVariableSysManagementType           = 0x05,\r
  EventLogVariableMutliEventSysManagmentType  = 0x06,                               \r
  EventLogVariableUnused                      = 0x07,\r
  EventLogVariableOEMAssigned                 = 0x80\r
} EVENT_LOG_VARIABLE_DATA;\r
\r
///\r
/// Event Log Type Descriptors\r
///\r
typedef struct {\r
  UINT8                 LogType;                    ///< The enumeration value from EVENT_LOG_TYPE_DATA.\r
  UINT8                 DataFormatType;\r
} EVENT_LOG_TYPE;\r
\r
///\r
/// System Event Log (Type 15).\r
///\r
/// The presence of this structure within the SMBIOS data returned for a system indicates \r
/// that the system supports an event log.  An event log is a fixed-length area within a \r
/// non-volatile storage element, starting with a fixed-length (and vendor-specific) header \r
/// record, followed by one or more variable-length log records. \r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE      Hdr;\r
  UINT16                LogAreaLength;\r
  UINT16                LogHeaderStartOffset;\r
  UINT16                LogDataStartOffset;\r
  UINT8                 AccessMethod;\r
  UINT8                 LogStatus;\r
  UINT32                LogChangeToken;\r
  UINT32                AccessMethodAddress;\r
  UINT8                 LogHeaderFormat;\r
  UINT8                 NumberOfSupportedLogTypeDescriptors;\r
  UINT8                 LengthOfLogTypeDescriptor;\r
  EVENT_LOG_TYPE        EventLogTypeDescriptors[1];\r
} SMBIOS_TABLE_TYPE15;\r
\r
///\r
/// Physical Memory Array - Location.\r
///\r
typedef enum {\r
  MemoryArrayLocationOther                 = 0x01,\r
  MemoryArrayLocationUnknown               = 0x02,\r
  MemoryArrayLocationSystemBoard           = 0x03,\r
  MemoryArrayLocationIsaAddonCard          = 0x04,\r
  MemoryArrayLocationEisaAddonCard         = 0x05,\r
  MemoryArrayLocationPciAddonCard          = 0x06,\r
  MemoryArrayLocationMcaAddonCard          = 0x07,\r
  MemoryArrayLocationPcmciaAddonCard       = 0x08,\r
  MemoryArrayLocationProprietaryAddonCard  = 0x09,\r
  MemoryArrayLocationNuBus                 = 0x0A,\r
  MemoryArrayLocationPc98C20AddonCard      = 0xA0,\r
  MemoryArrayLocationPc98C24AddonCard      = 0xA1,\r
  MemoryArrayLocationPc98EAddonCard        = 0xA2,\r
  MemoryArrayLocationPc98LocalBusAddonCard = 0xA3\r
} MEMORY_ARRAY_LOCATION;\r
\r
///\r
/// Physical Memory Array - Use.\r
///\r
typedef enum {\r
  MemoryArrayUseOther                      = 0x01,\r
  MemoryArrayUseUnknown                    = 0x02,\r
  MemoryArrayUseSystemMemory               = 0x03,\r
  MemoryArrayUseVideoMemory                = 0x04,\r
  MemoryArrayUseFlashMemory                = 0x05,\r
  MemoryArrayUseNonVolatileRam             = 0x06,\r
  MemoryArrayUseCacheMemory                = 0x07\r
} MEMORY_ARRAY_USE;\r
\r
///\r
/// Physical Memory Array - Error Correction Types. \r
///\r
typedef enum {\r
  MemoryErrorCorrectionOther               = 0x01,\r
  MemoryErrorCorrectionUnknown             = 0x02,\r
  MemoryErrorCorrectionNone                = 0x03,\r
  MemoryErrorCorrectionParity              = 0x04,\r
  MemoryErrorCorrectionSingleBitEcc        = 0x05,\r
  MemoryErrorCorrectionMultiBitEcc         = 0x06,\r
  MemoryErrorCorrectionCrc                 = 0x07\r
} MEMORY_ERROR_CORRECTION;\r
\r
///\r
/// Physical Memory Array (Type 16).\r
///\r
/// This structure describes a collection of memory devices that operate \r
/// together to form a memory address space. \r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE          Hdr;\r
  UINT8                     Location;                       ///< The enumeration value from MEMORY_ARRAY_LOCATION.\r
  UINT8                     Use;                            ///< The enumeration value from MEMORY_ARRAY_USE.\r
  UINT8                     MemoryErrorCorrection;          ///< The enumeration value from MEMORY_ERROR_CORRECTION.\r
  UINT32                    MaximumCapacity;\r
  UINT16                    MemoryErrorInformationHandle;\r
  UINT16                    NumberOfMemoryDevices;\r
  //\r
  // Add for smbios 2.7\r
  //\r
  UINT64                    ExtendedMaximumCapacity;\r
} SMBIOS_TABLE_TYPE16;\r
\r
///\r
/// Memory Device - Form Factor.\r
///\r
typedef enum {\r
  MemoryFormFactorOther                    = 0x01,\r
  MemoryFormFactorUnknown                  = 0x02,\r
  MemoryFormFactorSimm                     = 0x03,\r
  MemoryFormFactorSip                      = 0x04,\r
  MemoryFormFactorChip                     = 0x05,\r
  MemoryFormFactorDip                      = 0x06,\r
  MemoryFormFactorZip                      = 0x07,\r
  MemoryFormFactorProprietaryCard          = 0x08,\r
  MemoryFormFactorDimm                     = 0x09,\r
  MemoryFormFactorTsop                     = 0x0A,\r
  MemoryFormFactorRowOfChips               = 0x0B,\r
  MemoryFormFactorRimm                     = 0x0C,\r
  MemoryFormFactorSodimm                   = 0x0D,\r
  MemoryFormFactorSrimm                    = 0x0E,\r
  MemoryFormFactorFbDimm                   = 0x0F\r
} MEMORY_FORM_FACTOR;\r
\r
///\r
/// Memory Device - Type\r
///\r
typedef enum {\r
  MemoryTypeOther                          = 0x01,\r
  MemoryTypeUnknown                        = 0x02,\r
  MemoryTypeDram                           = 0x03,\r
  MemoryTypeEdram                          = 0x04,\r
  MemoryTypeVram                           = 0x05,\r
  MemoryTypeSram                           = 0x06,\r
  MemoryTypeRam                            = 0x07,\r
  MemoryTypeRom                            = 0x08,\r
  MemoryTypeFlash                          = 0x09,\r
  MemoryTypeEeprom                         = 0x0A,\r
  MemoryTypeFeprom                         = 0x0B,\r
  MemoryTypeEprom                          = 0x0C,\r
  MemoryTypeCdram                          = 0x0D,\r
  MemoryType3Dram                          = 0x0E,\r
  MemoryTypeSdram                          = 0x0F,\r
  MemoryTypeSgram                          = 0x10,\r
  MemoryTypeRdram                          = 0x11,\r
  MemoryTypeDdr                            = 0x12,\r
  MemoryTypeDdr2                           = 0x13,\r
  MemoryTypeDdr2FbDimm                     = 0x14,\r
  MemoryTypeDdr3                           = 0x18,\r
  MemoryTypeFbd2                           = 0x19,\r
  MemoryTypeDdr4                           = 0x1A,\r
  MemoryTypeLpddr                          = 0x1B,\r
  MemoryTypeLpddr2                         = 0x1C,\r
  MemoryTypeLpddr3                         = 0x1D,\r
  MemoryTypeLpddr4                         = 0x1E\r
} MEMORY_DEVICE_TYPE;\r
\r
typedef struct {\r
  UINT16    Reserved        :1;\r
  UINT16    Other           :1;\r
  UINT16    Unknown         :1;\r
  UINT16    FastPaged       :1;\r
  UINT16    StaticColumn    :1;\r
  UINT16    PseudoStatic    :1;\r
  UINT16    Rambus          :1;\r
  UINT16    Synchronous     :1;\r
  UINT16    Cmos            :1;\r
  UINT16    Edo             :1;\r
  UINT16    WindowDram      :1;\r
  UINT16    CacheDram       :1;\r
  UINT16    Nonvolatile     :1;\r
  UINT16    Registered      :1;\r
  UINT16    Unbuffered      :1;\r
  UINT16    LrDimm          :1;\r
} MEMORY_DEVICE_TYPE_DETAIL;\r
\r
///\r
/// Memory Device (Type 17).\r
///\r
/// This structure describes a single memory device that is part of \r
/// a larger Physical Memory Array (Type 16).\r
/// Note:  If a system includes memory-device sockets, the SMBIOS implementation \r
/// includes a Memory Device structure instance for each slot, whether or not the \r
/// socket is currently populated.\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE          Hdr;\r
  UINT16                    MemoryArrayHandle;\r
  UINT16                    MemoryErrorInformationHandle;\r
  UINT16                    TotalWidth;\r
  UINT16                    DataWidth;\r
  UINT16                    Size;\r
  UINT8                     FormFactor;                     ///< The enumeration value from MEMORY_FORM_FACTOR.\r
  UINT8                     DeviceSet;\r
  SMBIOS_TABLE_STRING       DeviceLocator;\r
  SMBIOS_TABLE_STRING       BankLocator;\r
  UINT8                     MemoryType;                     ///< The enumeration value from MEMORY_DEVICE_TYPE.\r
  MEMORY_DEVICE_TYPE_DETAIL TypeDetail;\r
  UINT16                    Speed;\r
  SMBIOS_TABLE_STRING       Manufacturer;\r
  SMBIOS_TABLE_STRING       SerialNumber;\r
  SMBIOS_TABLE_STRING       AssetTag;\r
  SMBIOS_TABLE_STRING       PartNumber;\r
  //\r
  // Add for smbios 2.6\r
  //  \r
  UINT8                     Attributes;\r
  //\r
  // Add for smbios 2.7\r
  //\r
  UINT32                    ExtendedSize;\r
  UINT16                    ConfiguredMemoryClockSpeed;\r
  //\r
  // Add for smbios 2.8.0\r
  //\r
  UINT16                    MinimumVoltage;\r
  UINT16                    MaximumVoltage;\r
  UINT16                    ConfiguredVoltage;\r
} SMBIOS_TABLE_TYPE17;\r
\r
///\r
/// 32-bit Memory Error Information - Error Type. \r
///\r
typedef enum {  \r
  MemoryErrorOther             = 0x01,\r
  MemoryErrorUnknown           = 0x02,\r
  MemoryErrorOk                = 0x03,\r
  MemoryErrorBadRead           = 0x04,\r
  MemoryErrorParity            = 0x05,\r
  MemoryErrorSigleBit          = 0x06,\r
  MemoryErrorDoubleBit         = 0x07,\r
  MemoryErrorMultiBit          = 0x08,\r
  MemoryErrorNibble            = 0x09,\r
  MemoryErrorChecksum          = 0x0A,\r
  MemoryErrorCrc               = 0x0B,\r
  MemoryErrorCorrectSingleBit  = 0x0C,\r
  MemoryErrorCorrected         = 0x0D,\r
  MemoryErrorUnCorrectable     = 0x0E\r
} MEMORY_ERROR_TYPE;\r
\r
///\r
/// 32-bit Memory Error Information - Error Granularity. \r
///\r
typedef enum {  \r
  MemoryGranularityOther               = 0x01,\r
  MemoryGranularityOtherUnknown        = 0x02,\r
  MemoryGranularityDeviceLevel         = 0x03,\r
  MemoryGranularityMemPartitionLevel   = 0x04\r
} MEMORY_ERROR_GRANULARITY;\r
\r
///\r
/// 32-bit Memory Error Information - Error Operation. \r
///\r
typedef enum {  \r
  MemoryErrorOperationOther            = 0x01,\r
  MemoryErrorOperationUnknown          = 0x02,\r
  MemoryErrorOperationRead             = 0x03,\r
  MemoryErrorOperationWrite            = 0x04,\r
  MemoryErrorOperationPartialWrite     = 0x05\r
} MEMORY_ERROR_OPERATION;\r
\r
///\r
/// 32-bit Memory Error Information (Type 18).\r
/// \r
/// This structure identifies the specifics of an error that might be detected \r
/// within a Physical Memory Array.\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE          Hdr;\r
  UINT8                     ErrorType;                  ///< The enumeration value from MEMORY_ERROR_TYPE.\r
  UINT8                     ErrorGranularity;           ///< The enumeration value from MEMORY_ERROR_GRANULARITY.\r
  UINT8                     ErrorOperation;             ///< The enumeration value from MEMORY_ERROR_OPERATION.\r
  UINT32                    VendorSyndrome;\r
  UINT32                    MemoryArrayErrorAddress;\r
  UINT32                    DeviceErrorAddress;\r
  UINT32                    ErrorResolution;\r
} SMBIOS_TABLE_TYPE18;\r
\r
///\r
/// Memory Array Mapped Address (Type 19).\r
///\r
/// This structure provides the address mapping for a Physical Memory Array.  \r
/// One structure is present for each contiguous address range described.\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE      Hdr;\r
  UINT32                StartingAddress;\r
  UINT32                EndingAddress;\r
  UINT16                MemoryArrayHandle;\r
  UINT8                 PartitionWidth;\r
  //\r
  // Add for smbios 2.7\r
  //\r
  UINT64                ExtendedStartingAddress;\r
  UINT64                ExtendedEndingAddress;\r
} SMBIOS_TABLE_TYPE19;\r
\r
///\r
/// Memory Device Mapped Address (Type 20).\r
///\r
/// This structure maps memory address space usually to a device-level granularity.  \r
/// One structure is present for each contiguous address range described. \r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE      Hdr;\r
  UINT32                StartingAddress;\r
  UINT32                EndingAddress;\r
  UINT16                MemoryDeviceHandle;\r
  UINT16                MemoryArrayMappedAddressHandle;\r
  UINT8                 PartitionRowPosition;\r
  UINT8                 InterleavePosition;\r
  UINT8                 InterleavedDataDepth;\r
  //\r
  // Add for smbios 2.7\r
  //\r
  UINT64                ExtendedStartingAddress;\r
  UINT64                ExtendedEndingAddress;\r
} SMBIOS_TABLE_TYPE20;\r
\r
///\r
/// Built-in Pointing Device - Type\r
///\r
typedef enum {\r
  PointingDeviceTypeOther         = 0x01,\r
  PointingDeviceTypeUnknown       = 0x02,\r
  PointingDeviceTypeMouse         = 0x03,\r
  PointingDeviceTypeTrackBall     = 0x04,\r
  PointingDeviceTypeTrackPoint    = 0x05,\r
  PointingDeviceTypeGlidePoint    = 0x06,\r
  PointingDeviceTouchPad          = 0x07,\r
  PointingDeviceTouchScreen       = 0x08,\r
  PointingDeviceOpticalSensor     = 0x09\r
} BUILTIN_POINTING_DEVICE_TYPE;\r
\r
///\r
/// Built-in Pointing Device - Interface.\r
///\r
typedef enum {\r
  PointingDeviceInterfaceOther              = 0x01,\r
  PointingDeviceInterfaceUnknown            = 0x02,\r
  PointingDeviceInterfaceSerial             = 0x03,\r
  PointingDeviceInterfacePs2                = 0x04,\r
  PointingDeviceInterfaceInfrared           = 0x05,\r
  PointingDeviceInterfaceHpHil              = 0x06,\r
  PointingDeviceInterfaceBusMouse           = 0x07,\r
  PointingDeviceInterfaceADB                = 0x08,\r
  PointingDeviceInterfaceBusMouseDB9        = 0xA0,\r
  PointingDeviceInterfaceBusMouseMicroDin   = 0xA1,\r
  PointingDeviceInterfaceUsb                = 0xA2\r
} BUILTIN_POINTING_DEVICE_INTERFACE;\r
\r
///\r
/// Built-in Pointing Device (Type 21).\r
///\r
/// This structure describes the attributes of the built-in pointing device for the \r
/// system. The presence of this structure does not imply that the built-in\r
/// pointing device is active for the system's use! \r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE                  Hdr;\r
  UINT8                             Type;                   ///< The enumeration value from BUILTIN_POINTING_DEVICE_TYPE.\r
  UINT8                             Interface;              ///< The enumeration value from BUILTIN_POINTING_DEVICE_INTERFACE.\r
  UINT8                             NumberOfButtons;\r
} SMBIOS_TABLE_TYPE21;\r
\r
///\r
/// Portable Battery - Device Chemistry\r
///\r
typedef enum {  \r
  PortableBatteryDeviceChemistryOther               = 0x01,\r
  PortableBatteryDeviceChemistryUnknown             = 0x02,\r
  PortableBatteryDeviceChemistryLeadAcid            = 0x03,\r
  PortableBatteryDeviceChemistryNickelCadmium       = 0x04,\r
  PortableBatteryDeviceChemistryNickelMetalHydride  = 0x05,\r
  PortableBatteryDeviceChemistryLithiumIon          = 0x06,\r
  PortableBatteryDeviceChemistryZincAir             = 0x07,\r
  PortableBatteryDeviceChemistryLithiumPolymer      = 0x08\r
} PORTABLE_BATTERY_DEVICE_CHEMISTRY;\r
\r
///\r
/// Portable Battery (Type 22).\r
///\r
/// This structure describes the attributes of the portable battery(s) for the system.  \r
/// The structure contains the static attributes for the group.  Each structure describes \r
/// a single battery pack's attributes.\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE                  Hdr;\r
  SMBIOS_TABLE_STRING               Location;\r
  SMBIOS_TABLE_STRING               Manufacturer;\r
  SMBIOS_TABLE_STRING               ManufactureDate;\r
  SMBIOS_TABLE_STRING               SerialNumber;\r
  SMBIOS_TABLE_STRING               DeviceName;\r
  UINT8                             DeviceChemistry;              ///< The enumeration value from PORTABLE_BATTERY_DEVICE_CHEMISTRY.\r
  UINT16                            DeviceCapacity;\r
  UINT16                            DesignVoltage;\r
  SMBIOS_TABLE_STRING               SBDSVersionNumber;\r
  UINT8                             MaximumErrorInBatteryData;\r
  UINT16                            SBDSSerialNumber;\r
  UINT16                            SBDSManufactureDate;\r
  SMBIOS_TABLE_STRING               SBDSDeviceChemistry;\r
  UINT8                             DesignCapacityMultiplier;\r
  UINT32                            OEMSpecific;\r
} SMBIOS_TABLE_TYPE22;\r
\r
///\r
/// System Reset (Type 23)\r
///\r
/// This structure describes whether Automatic System Reset functions enabled (Status).  \r
/// If the system has a watchdog Timer and the timer is not reset (Timer Reset)\r
/// before the Interval elapses, an automatic system reset will occur. The system will re-boot \r
/// according to the Boot Option. This function may repeat until the Limit is reached, at which time \r
/// the system will re-boot according to the Boot Option at Limit.  \r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE      Hdr;\r
  UINT8                 Capabilities;\r
  UINT16                ResetCount;\r
  UINT16                ResetLimit;\r
  UINT16                TimerInterval;\r
  UINT16                Timeout;\r
} SMBIOS_TABLE_TYPE23;\r
\r
///\r
/// Hardware Security (Type 24).\r
///\r
/// This structure describes the system-wide hardware security settings. \r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE      Hdr;\r
  UINT8                 HardwareSecuritySettings;\r
} SMBIOS_TABLE_TYPE24;\r
\r
///\r
/// System Power Controls (Type 25).\r
///\r
/// This structure describes the attributes for controlling the main power supply to the system. \r
/// Software that interprets this structure uses the month, day, hour, minute, and second values \r
/// to determine the number of seconds until the next power-on of the system.  The presence of  \r
/// this structure implies that a timed power-on facility is available for the system. \r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE      Hdr;\r
  UINT8                 NextScheduledPowerOnMonth;\r
  UINT8                 NextScheduledPowerOnDayOfMonth;\r
  UINT8                 NextScheduledPowerOnHour;\r
  UINT8                 NextScheduledPowerOnMinute;\r
  UINT8                 NextScheduledPowerOnSecond;\r
} SMBIOS_TABLE_TYPE25;\r
\r
///\r
/// Voltage Probe - Location and Status.\r
///\r
typedef struct {\r
  UINT8 VoltageProbeSite      :5;\r
  UINT8  VoltageProbeStatus   :3;\r
} MISC_VOLTAGE_PROBE_LOCATION;\r
\r
///\r
/// Voltage Probe (Type 26)\r
///\r
/// This describes the attributes for a voltage probe in the system.   \r
/// Each structure describes a single voltage probe.\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE              Hdr;\r
  SMBIOS_TABLE_STRING           Description;\r
  MISC_VOLTAGE_PROBE_LOCATION   LocationAndStatus;\r
  UINT16                        MaximumValue;\r
  UINT16                        MinimumValue;\r
  UINT16                        Resolution;\r
  UINT16                        Tolerance;\r
  UINT16                        Accuracy;\r
  UINT32                        OEMDefined;\r
  UINT16                        NominalValue;\r
} SMBIOS_TABLE_TYPE26;\r
\r
///\r
/// Cooling Device - Device Type and Status.\r
///\r
typedef struct {\r
  UINT8 CoolingDevice       :5;\r
  UINT8 CoolingDeviceStatus :3;\r
} MISC_COOLING_DEVICE_TYPE;\r
\r
///\r
/// Cooling Device (Type 27)\r
///\r
/// This structure describes the attributes for a cooling device in the system.  \r
/// Each structure describes a single cooling device. \r
/// \r
typedef struct {\r
  SMBIOS_STRUCTURE                  Hdr;\r
  UINT16                            TemperatureProbeHandle;\r
  MISC_COOLING_DEVICE_TYPE          DeviceTypeAndStatus;\r
  UINT8                             CoolingUnitGroup;\r
  UINT32                            OEMDefined;\r
  UINT16                            NominalSpeed;\r
  //\r
  // Add for smbios 2.7\r
  //\r
  SMBIOS_TABLE_STRING               Description;\r
} SMBIOS_TABLE_TYPE27;\r
\r
///\r
/// Temperature Probe - Location and Status.\r
///\r
typedef struct {\r
  UINT8 TemperatureProbeSite   :5;\r
  UINT8 TemperatureProbeStatus :3;\r
} MISC_TEMPERATURE_PROBE_LOCATION;\r
\r
///\r
/// Temperature Probe (Type 28).\r
///\r
/// This structure describes the attributes for a temperature probe in the system.  \r
/// Each structure describes a single temperature probe. \r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE                  Hdr;\r
  SMBIOS_TABLE_STRING               Description;\r
  MISC_TEMPERATURE_PROBE_LOCATION   LocationAndStatus;\r
  UINT16                            MaximumValue;\r
  UINT16                            MinimumValue;\r
  UINT16                            Resolution;\r
  UINT16                            Tolerance;\r
  UINT16                            Accuracy;\r
  UINT32                            OEMDefined;\r
  UINT16                            NominalValue;\r
} SMBIOS_TABLE_TYPE28;\r
\r
///\r
/// Electrical Current Probe - Location and Status.\r
///\r
typedef struct {\r
  UINT8 ElectricalCurrentProbeSite   :5;\r
  UINT8 ElectricalCurrentProbeStatus :3;\r
} MISC_ELECTRICAL_CURRENT_PROBE_LOCATION;\r
\r
///\r
/// Electrical Current Probe (Type 29).\r
///\r
/// This structure describes the attributes for an electrical current probe in the system.\r
/// Each structure describes a single electrical current probe. \r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE                        Hdr;\r
  SMBIOS_TABLE_STRING                     Description;\r
  MISC_ELECTRICAL_CURRENT_PROBE_LOCATION  LocationAndStatus;\r
  UINT16                                  MaximumValue;\r
  UINT16                                  MinimumValue;\r
  UINT16                                  Resolution;\r
  UINT16                                  Tolerance;\r
  UINT16                                  Accuracy;\r
  UINT32                                  OEMDefined;\r
  UINT16                                  NominalValue;\r
} SMBIOS_TABLE_TYPE29;\r
\r
///\r
/// Out-of-Band Remote Access (Type 30).\r
///\r
/// This structure describes the attributes and policy settings of a hardware facility \r
/// that may be used to gain remote access to a hardware system when the operating system \r
/// is not available due to power-down status, hardware failures, or boot failures. \r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE      Hdr;\r
  SMBIOS_TABLE_STRING   ManufacturerName;\r
  UINT8                 Connections;\r
} SMBIOS_TABLE_TYPE30;\r
\r
///\r
/// Boot Integrity Services (BIS) Entry Point (Type 31).\r
///\r
/// Structure type 31 (decimal) is reserved for use by the Boot Integrity Services (BIS). \r
/// \r
typedef struct {\r
  SMBIOS_STRUCTURE      Hdr;\r
  UINT8                 Checksum;\r
  UINT8                 Reserved1;\r
  UINT16                Reserved2;\r
  UINT32                BisEntry16;\r
  UINT32                BisEntry32;\r
  UINT64                Reserved3;\r
  UINT32                Reserved4;\r
} SMBIOS_TABLE_TYPE31;\r
\r
///\r
/// System Boot Information - System Boot Status.\r
///\r
typedef enum {\r
  BootInformationStatusNoError                  = 0x00,\r
  BootInformationStatusNoBootableMedia          = 0x01,\r
  BootInformationStatusNormalOSFailedLoading    = 0x02,\r
  BootInformationStatusFirmwareDetectedFailure  = 0x03,\r
  BootInformationStatusOSDetectedFailure        = 0x04,\r
  BootInformationStatusUserRequestedBoot        = 0x05,\r
  BootInformationStatusSystemSecurityViolation  = 0x06,\r
  BootInformationStatusPreviousRequestedImage   = 0x07,\r
  BootInformationStatusWatchdogTimerExpired     = 0x08,\r
  BootInformationStatusStartReserved            = 0x09,\r
  BootInformationStatusStartOemSpecific         = 0x80,\r
  BootInformationStatusStartProductSpecific     = 0xC0\r
} MISC_BOOT_INFORMATION_STATUS_DATA_TYPE;\r
\r
///\r
/// System Boot Information (Type 32).\r
///\r
/// The client system firmware, e.g. BIOS, communicates the System Boot Status to the \r
/// client's Pre-boot Execution Environment (PXE) boot image or OS-present management \r
/// application via this structure. When used in the PXE environment, for example, \r
/// this code identifies the reason the PXE was initiated and can be used by boot-image \r
/// software to further automate an enterprise's PXE sessions.  For example, an enterprise  \r
/// could choose to automatically download a hardware-diagnostic image to a client whose \r
/// reason code indicated either a firmware- or operating system-detected hardware failure.\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE                        Hdr;\r
  UINT8                                   Reserved[6];\r
  UINT8                                   BootStatus;     ///< The enumeration value from MISC_BOOT_INFORMATION_STATUS_DATA_TYPE.\r
} SMBIOS_TABLE_TYPE32;\r
\r
///\r
/// 64-bit Memory Error Information (Type 33).\r
///\r
/// This structure describes an error within a Physical Memory Array, \r
/// when the error address is above 4G (0xFFFFFFFF).\r
///    \r
typedef struct {\r
  SMBIOS_STRUCTURE          Hdr;\r
  UINT8                     ErrorType;                    ///< The enumeration value from MEMORY_ERROR_TYPE.\r
  UINT8                     ErrorGranularity;             ///< The enumeration value from MEMORY_ERROR_GRANULARITY.\r
  UINT8                     ErrorOperation;               ///< The enumeration value from MEMORY_ERROR_OPERATION.\r
  UINT32                    VendorSyndrome;\r
  UINT64                    MemoryArrayErrorAddress;\r
  UINT64                    DeviceErrorAddress;\r
  UINT32                    ErrorResolution;\r
} SMBIOS_TABLE_TYPE33;\r
\r
///\r
/// Management Device -  Type. \r
///\r
typedef enum {\r
  ManagementDeviceTypeOther      = 0x01,\r
  ManagementDeviceTypeUnknown    = 0x02,\r
  ManagementDeviceTypeLm75       = 0x03,\r
  ManagementDeviceTypeLm78       = 0x04,\r
  ManagementDeviceTypeLm79       = 0x05,\r
  ManagementDeviceTypeLm80       = 0x06,\r
  ManagementDeviceTypeLm81       = 0x07,\r
  ManagementDeviceTypeAdm9240    = 0x08,\r
  ManagementDeviceTypeDs1780     = 0x09,\r
  ManagementDeviceTypeMaxim1617  = 0x0A,\r
  ManagementDeviceTypeGl518Sm    = 0x0B,\r
  ManagementDeviceTypeW83781D    = 0x0C,\r
  ManagementDeviceTypeHt82H791   = 0x0D\r
} MISC_MANAGEMENT_DEVICE_TYPE;\r
\r
///\r
/// Management Device -  Address Type. \r
///\r
typedef enum {\r
  ManagementDeviceAddressTypeOther   = 0x01,\r
  ManagementDeviceAddressTypeUnknown = 0x02,\r
  ManagementDeviceAddressTypeIOPort  = 0x03,\r
  ManagementDeviceAddressTypeMemory  = 0x04,\r
  ManagementDeviceAddressTypeSmbus   = 0x05\r
} MISC_MANAGEMENT_DEVICE_ADDRESS_TYPE;\r
\r
///\r
/// Management Device (Type 34).\r
///\r
/// The information in this structure defines the attributes of a Management Device.  \r
/// A Management Device might control one or more fans or voltage, current, or temperature\r
/// probes as defined by one or more Management Device Component structures.\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE                      Hdr;\r
  SMBIOS_TABLE_STRING                   Description;\r
  UINT8                                 Type;                     ///< The enumeration value from MISC_MANAGEMENT_DEVICE_TYPE.\r
  UINT32                                Address;\r
  UINT8                                 AddressType;              ///< The enumeration value from MISC_MANAGEMENT_DEVICE_ADDRESS_TYPE.\r
} SMBIOS_TABLE_TYPE34;\r
\r
///\r
/// Management Device Component (Type 35)\r
///\r
/// This structure associates a cooling device or environmental probe with structures \r
/// that define the controlling hardware device and (optionally) the component's thresholds. \r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE      Hdr;\r
  SMBIOS_TABLE_STRING   Description;\r
  UINT16                ManagementDeviceHandle;\r
  UINT16                ComponentHandle;\r
  UINT16                ThresholdHandle;\r
} SMBIOS_TABLE_TYPE35;\r
\r
///\r
/// Management Device Threshold Data (Type 36).\r
///\r
/// The information in this structure defines threshold information for \r
/// a component (probe or cooling-unit) contained within a Management Device.  \r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE      Hdr;\r
  UINT16                LowerThresholdNonCritical;\r
  UINT16                UpperThresholdNonCritical;\r
  UINT16                LowerThresholdCritical;\r
  UINT16                UpperThresholdCritical;\r
  UINT16                LowerThresholdNonRecoverable;\r
  UINT16                UpperThresholdNonRecoverable;\r
} SMBIOS_TABLE_TYPE36;\r
\r
///\r
/// Memory Channel Entry.\r
///\r
typedef struct {\r
  UINT8                 DeviceLoad;\r
  UINT16                DeviceHandle;\r
} MEMORY_DEVICE;\r
\r
///\r
/// Memory Channel - Channel Type.\r
///\r
typedef enum {\r
  MemoryChannelTypeOther       = 0x01,\r
  MemoryChannelTypeUnknown     = 0x02,\r
  MemoryChannelTypeRambus      = 0x03,\r
  MemoryChannelTypeSyncLink    = 0x04\r
} MEMORY_CHANNEL_TYPE;\r
\r
///\r
/// Memory Channel (Type 37)\r
///\r
/// The information in this structure provides the correlation between a Memory Channel\r
/// and its associated Memory Devices.  Each device presents one or more loads to the channel. \r
/// The sum of all device loads cannot exceed the channel's defined maximum.\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE      Hdr;\r
  UINT8                 ChannelType;\r
  UINT8                 MaximumChannelLoad;\r
  UINT8                 MemoryDeviceCount;\r
  MEMORY_DEVICE         MemoryDevice[1];\r
} SMBIOS_TABLE_TYPE37;\r
\r
///\r
/// IPMI Device Information - BMC Interface Type\r
///\r
typedef enum {\r
  IPMIDeviceInfoInterfaceTypeUnknown       = 0x00,\r
  IPMIDeviceInfoInterfaceTypeKCS           = 0x01, ///< The Keyboard Controller Style.\r
  IPMIDeviceInfoInterfaceTypeSMIC          = 0x02, ///< The Server Management Interface Chip.\r
  IPMIDeviceInfoInterfaceTypeBT            = 0x03, ///< The Block Transfer\r
  IPMIDeviceInfoInterfaceTypeReserved      = 0x04\r
} BMC_INTERFACE_TYPE;\r
\r
///\r
/// IPMI Device Information (Type 38).\r
///\r
/// The information in this structure defines the attributes of an\r
/// Intelligent Platform Management Interface (IPMI) Baseboard Management Controller (BMC).\r
///\r
/// The Type 42 structure can also be used to describe a physical management controller\r
/// host interface and one or more protocols that share that interface. If IPMI is not\r
/// shared with other protocols, either the Type 38 or Type 42 structures can be used.\r
/// Providing Type 38 is recommended for backward compatibility.\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE      Hdr;\r
  UINT8                 InterfaceType;              ///< The enumeration value from BMC_INTERFACE_TYPE.\r
  UINT8                 IPMISpecificationRevision;\r
  UINT8                 I2CSlaveAddress;\r
  UINT8                 NVStorageDeviceAddress;\r
  UINT64                BaseAddress;\r
  UINT8                 BaseAddressModifier_InterruptInfo;\r
  UINT8                 InterruptNumber;\r
} SMBIOS_TABLE_TYPE38;\r
\r
///\r
/// System Power Supply - Power Supply Characteristics.\r
///\r
typedef struct {\r
  UINT16                        PowerSupplyHotReplaceable:1;\r
  UINT16                        PowerSupplyPresent       :1;\r
  UINT16                        PowerSupplyUnplugged     :1;\r
  UINT16                        InputVoltageRangeSwitch  :4;\r
  UINT16                        PowerSupplyStatus        :3;\r
  UINT16                        PowerSupplyType          :4;\r
  UINT16                        Reserved                 :2;\r
} SYS_POWER_SUPPLY_CHARACTERISTICS;\r
\r
///\r
/// System Power Supply (Type 39).\r
///\r
/// This structure identifies attributes of a system power supply. One instance\r
/// of this record is present for each possible power supply in a system.\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE                  Hdr;\r
  UINT8                             PowerUnitGroup;\r
  SMBIOS_TABLE_STRING               Location;\r
  SMBIOS_TABLE_STRING               DeviceName;\r
  SMBIOS_TABLE_STRING               Manufacturer;\r
  SMBIOS_TABLE_STRING               SerialNumber;\r
  SMBIOS_TABLE_STRING               AssetTagNumber;\r
  SMBIOS_TABLE_STRING               ModelPartNumber;\r
  SMBIOS_TABLE_STRING               RevisionLevel;\r
  UINT16                            MaxPowerCapacity;\r
  SYS_POWER_SUPPLY_CHARACTERISTICS  PowerSupplyCharacteristics;\r
  UINT16                            InputVoltageProbeHandle;\r
  UINT16                            CoolingDeviceHandle;\r
  UINT16                            InputCurrentProbeHandle;\r
} SMBIOS_TABLE_TYPE39;\r
\r
///\r
/// Additional Information Entry Format. \r
///\r
typedef struct {                       \r
  UINT8                   EntryLength; \r
  UINT16                  ReferencedHandle;\r
  UINT8                   ReferencedOffset;\r
  SMBIOS_TABLE_STRING     EntryString;\r
  UINT8                   Value[1];\r
}ADDITIONAL_INFORMATION_ENTRY;\r
\r
///\r
/// Additional Information (Type 40).\r
///\r
/// This structure is intended to provide additional information for handling unspecified \r
/// enumerated values and interim field updates in another structure. \r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE                      Hdr;\r
  UINT8                                 NumberOfAdditionalInformationEntries;\r
  ADDITIONAL_INFORMATION_ENTRY          AdditionalInfoEntries[1];  \r
} SMBIOS_TABLE_TYPE40;\r
\r
///\r
/// Onboard Devices Extended Information - Onboard Device Types.\r
///\r
typedef enum{\r
  OnBoardDeviceExtendedTypeOther          = 0x01,\r
  OnBoardDeviceExtendedTypeUnknown        = 0x02,\r
  OnBoardDeviceExtendedTypeVideo          = 0x03,\r
  OnBoardDeviceExtendedTypeScsiController = 0x04,\r
  OnBoardDeviceExtendedTypeEthernet       = 0x05,\r
  OnBoardDeviceExtendedTypeTokenRing      = 0x06,\r
  OnBoardDeviceExtendedTypeSound          = 0x07,\r
  OnBoardDeviceExtendedTypePATAController = 0x08,\r
  OnBoardDeviceExtendedTypeSATAController = 0x09,\r
  OnBoardDeviceExtendedTypeSASController  = 0x0A\r
} ONBOARD_DEVICE_EXTENDED_INFO_TYPE;\r
\r
///\r
/// Onboard Devices Extended Information (Type 41).\r
///\r
/// The information in this structure defines the attributes of devices that \r
/// are onboard (soldered onto) a system element, usually the baseboard.  \r
/// In general, an entry in this table implies that the BIOS has some level of \r
/// control over the enabling of the associated device for use by the system. \r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE                  Hdr;\r
  SMBIOS_TABLE_STRING               ReferenceDesignation;\r
  UINT8                             DeviceType;             ///< The enumeration value from ONBOARD_DEVICE_EXTENDED_INFO_TYPE\r
  UINT8                             DeviceTypeInstance;\r
  UINT16                            SegmentGroupNum;\r
  UINT8                             BusNum;\r
  UINT8                             DevFuncNum;\r
} SMBIOS_TABLE_TYPE41;\r
\r
///\r
/// Management Controller Host Interface (Type 42).\r
///\r
/// The information in this structure defines the attributes of a Management\r
/// Controller Host Interface that is not discoverable by "Plug and Play" mechanisms.\r
///\r
/// Type 42 should be used for management controller host interfaces that use protocols\r
/// other than IPMI or that use multiple protocols on a single host interface type.\r
///\r
/// This structure should also be provided if IPMI is shared with other protocols\r
/// over the same interface hardware. If IPMI is not shared with other protocols,\r
/// either the Type 38 or Type 42 structures can be used. Providing Type 38 is\r
/// recommended for backward compatibility. The structures are not required to\r
/// be mutually exclusive. Type 38 and Type 42 structures may be implemented\r
/// simultaneously to provide backward compatibility with IPMI applications or drivers\r
/// that do not yet recognize the Type 42 structure.\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE                  Hdr;\r
  UINT8                             InterfaceType;\r
  UINT8                             MCHostInterfaceData[1]; ///< This field has a minimum of four bytes\r
} SMBIOS_TABLE_TYPE42;\r
\r
///\r
/// Inactive (Type 126)\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE   Hdr;\r
} SMBIOS_TABLE_TYPE126;\r
\r
///\r
/// End-of-Table (Type 127)\r
///\r
typedef struct {\r
  SMBIOS_STRUCTURE   Hdr;\r
} SMBIOS_TABLE_TYPE127;\r
\r
///\r
/// Union of all the possible SMBIOS record types.\r
///\r
typedef union {\r
  SMBIOS_STRUCTURE      *Hdr;\r
  SMBIOS_TABLE_TYPE0    *Type0;\r
  SMBIOS_TABLE_TYPE1    *Type1;\r
  SMBIOS_TABLE_TYPE2    *Type2;\r
  SMBIOS_TABLE_TYPE3    *Type3;\r
  SMBIOS_TABLE_TYPE4    *Type4;\r
  SMBIOS_TABLE_TYPE5    *Type5;\r
  SMBIOS_TABLE_TYPE6    *Type6;\r
  SMBIOS_TABLE_TYPE7    *Type7;\r
  SMBIOS_TABLE_TYPE8    *Type8;\r
  SMBIOS_TABLE_TYPE9    *Type9;\r
  SMBIOS_TABLE_TYPE10   *Type10;\r
  SMBIOS_TABLE_TYPE11   *Type11;\r
  SMBIOS_TABLE_TYPE12   *Type12;\r
  SMBIOS_TABLE_TYPE13   *Type13;\r
  SMBIOS_TABLE_TYPE14   *Type14;\r
  SMBIOS_TABLE_TYPE15   *Type15;\r
  SMBIOS_TABLE_TYPE16   *Type16;\r
  SMBIOS_TABLE_TYPE17   *Type17;\r
  SMBIOS_TABLE_TYPE18   *Type18;\r
  SMBIOS_TABLE_TYPE19   *Type19;\r
  SMBIOS_TABLE_TYPE20   *Type20;\r
  SMBIOS_TABLE_TYPE21   *Type21;\r
  SMBIOS_TABLE_TYPE22   *Type22;\r
  SMBIOS_TABLE_TYPE23   *Type23;\r
  SMBIOS_TABLE_TYPE24   *Type24;\r
  SMBIOS_TABLE_TYPE25   *Type25;\r
  SMBIOS_TABLE_TYPE26   *Type26;\r
  SMBIOS_TABLE_TYPE27   *Type27;\r
  SMBIOS_TABLE_TYPE28   *Type28;\r
  SMBIOS_TABLE_TYPE29   *Type29;\r
  SMBIOS_TABLE_TYPE30   *Type30;\r
  SMBIOS_TABLE_TYPE31   *Type31;\r
  SMBIOS_TABLE_TYPE32   *Type32;\r
  SMBIOS_TABLE_TYPE33   *Type33;\r
  SMBIOS_TABLE_TYPE34   *Type34;\r
  SMBIOS_TABLE_TYPE35   *Type35;\r
  SMBIOS_TABLE_TYPE36   *Type36;\r
  SMBIOS_TABLE_TYPE37   *Type37;\r
  SMBIOS_TABLE_TYPE38   *Type38;\r
  SMBIOS_TABLE_TYPE39   *Type39;\r
  SMBIOS_TABLE_TYPE40   *Type40;\r
  SMBIOS_TABLE_TYPE41   *Type41;\r
  SMBIOS_TABLE_TYPE42   *Type42;\r
  SMBIOS_TABLE_TYPE126  *Type126;\r
  SMBIOS_TABLE_TYPE127  *Type127;\r
  UINT8                 *Raw;\r
} SMBIOS_STRUCTURE_POINTER;\r
\r
#pragma pack()\r
\r
#endif\r