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1 | /** @file\r |
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2 | Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.\r |
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3 | \r |
| 4 | This library is identical to the PCI Library, except the access method for performing PCI \r |
| 5 | configuration cycles must be though I/O ports 0xCF8 and 0xCFC. This library only allows \r |
| 6 | access to PCI Segment #0.\r |
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7 | \r |
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8 | Copyright (c) 2006 - 2008, Intel Corporation<BR>\r |
| 50a64e5b |
9 | All rights reserved. This program and the accompanying materials\r |
| 10 | are licensed and made available under the terms and conditions of the BSD License\r |
| 11 | which accompanies this distribution. The full text of the license may be found at\r |
| 12 | http://opensource.org/licenses/bsd-license.php\r |
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13 | \r |
| 50a64e5b |
14 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 15 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| fb3df220 |
16 | \r |
| fb3df220 |
17 | **/\r |
| 18 | \r |
| 19 | #ifndef __PCI_CF8_LIB_H__\r |
| 20 | #define __PCI_CF8_LIB_H__\r |
| 21 | \r |
| 22 | \r |
| 23 | /**\r |
| 24 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r |
| 25 | address that can be passed to the PCI Library functions.\r |
| 26 | \r |
| 27 | Computes an address that is compatible with the PCI Library functions. The\r |
| 28 | unused upper bits of Bus, Device, Function and Register are stripped prior to\r |
| 29 | the generation of the address.\r |
| 30 | \r |
| 31 | @param Bus PCI Bus number. Range 0..255.\r |
| 32 | @param Device PCI Device number. Range 0..31.\r |
| 33 | @param Function PCI Function number. Range 0..7.\r |
| 34 | @param Register PCI Register number. Range 0..255.\r |
| 35 | \r |
| 36 | @return The encode PCI address.\r |
| 37 | \r |
| 38 | **/\r |
| 39 | #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \\r |
| 40 | (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r |
| 41 | \r |
| f926e538 |
42 | /**\r |
| d11195a3 |
43 | Registers a PCI device so PCI configuration registers may be accessed after \r |
| f926e538 |
44 | SetVirtualAddressMap().\r |
| 45 | \r |
| d11195a3 |
46 | Registers the PCI device specified by Address so all the PCI configuration registers \r |
| 47 | associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r |
| 48 | \r |
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49 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 50 | \r |
| 51 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 52 | Register.\r |
| 53 | \r |
| 54 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
| 55 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r |
| 56 | after ExitBootServices().\r |
| 57 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r |
| 58 | at runtime could not be mapped.\r |
| 59 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r |
| 60 | complete the registration.\r |
| 61 | \r |
| 62 | **/\r |
| 63 | RETURN_STATUS\r |
| 64 | EFIAPI\r |
| 65 | PciCf8RegisterForRuntimeAccess (\r |
| 66 | IN UINTN Address\r |
| 67 | );\r |
| 68 | \r |
| fb3df220 |
69 | /**\r |
| 70 | Reads an 8-bit PCI configuration register.\r |
| 71 | \r |
| 72 | Reads and returns the 8-bit PCI configuration register specified by Address.\r |
| 73 | This function must guarantee that all PCI read and write operations are\r |
| 74 | serialized.\r |
| 75 | \r |
| 76 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 77 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 78 | \r |
| 79 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 80 | Register.\r |
| 81 | \r |
| 82 | @return The read value from the PCI configuration register.\r |
| 83 | \r |
| 84 | **/\r |
| 85 | UINT8\r |
| 86 | EFIAPI\r |
| 87 | PciCf8Read8 (\r |
| 88 | IN UINTN Address\r |
| 89 | );\r |
| 90 | \r |
| 91 | /**\r |
| 92 | Writes an 8-bit PCI configuration register.\r |
| 93 | \r |
| 94 | Writes the 8-bit PCI configuration register specified by Address with the\r |
| 95 | value specified by Value. Value is returned. This function must guarantee\r |
| 96 | that all PCI read and write operations are serialized.\r |
| 97 | \r |
| 98 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 99 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 100 | \r |
| 101 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 102 | Register.\r |
| 103 | @param Value The value to write.\r |
| 104 | \r |
| 105 | @return The value written to the PCI configuration register.\r |
| 106 | \r |
| 107 | **/\r |
| 108 | UINT8\r |
| 109 | EFIAPI\r |
| 110 | PciCf8Write8 (\r |
| 111 | IN UINTN Address,\r |
| 94646ec0 |
112 | IN UINT8 Value\r |
| fb3df220 |
113 | );\r |
| 114 | \r |
| 115 | /**\r |
| 62991af2 |
116 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
| fb3df220 |
117 | an 8-bit value.\r |
| 118 | \r |
| 119 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 62991af2 |
120 | bitwise OR between the read result and the value specified by\r |
| fb3df220 |
121 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 122 | specified by Address. The value written to the PCI configuration register is\r |
| 123 | returned. This function must guarantee that all PCI read and write operations\r |
| 124 | are serialized.\r |
| 125 | \r |
| 126 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 127 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 128 | \r |
| 129 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 130 | Register.\r |
| 131 | @param OrData The value to OR with the PCI configuration register.\r |
| 132 | \r |
| 133 | @return The value written back to the PCI configuration register.\r |
| 134 | \r |
| 135 | **/\r |
| 136 | UINT8\r |
| 137 | EFIAPI\r |
| 138 | PciCf8Or8 (\r |
| 139 | IN UINTN Address,\r |
| 140 | IN UINT8 OrData\r |
| 141 | );\r |
| 142 | \r |
| 143 | /**\r |
| 144 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 145 | value.\r |
| 146 | \r |
| 147 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 148 | bitwise AND between the read result and the value specified by AndData, and\r |
| 149 | writes the result to the 8-bit PCI configuration register specified by\r |
| 150 | Address. The value written to the PCI configuration register is returned.\r |
| 151 | This function must guarantee that all PCI read and write operations are\r |
| 152 | serialized.\r |
| 153 | \r |
| 154 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 155 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 156 | \r |
| 157 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 158 | Register.\r |
| 159 | @param AndData The value to AND with the PCI configuration register.\r |
| 160 | \r |
| 161 | @return The value written back to the PCI configuration register.\r |
| 162 | \r |
| 163 | **/\r |
| 164 | UINT8\r |
| 165 | EFIAPI\r |
| 166 | PciCf8And8 (\r |
| 167 | IN UINTN Address,\r |
| 168 | IN UINT8 AndData\r |
| 169 | );\r |
| 170 | \r |
| 171 | /**\r |
| 172 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
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173 | value, followed a bitwise OR with another 8-bit value.\r |
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174 | \r |
| 175 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 176 | bitwise AND between the read result and the value specified by AndData,\r |
| 62991af2 |
177 | performs a bitwise OR between the result of the AND operation and\r |
| fb3df220 |
178 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
| 179 | configuration register specified by Address. The value written to the PCI\r |
| 180 | configuration register is returned. This function must guarantee that all PCI\r |
| 181 | read and write operations are serialized.\r |
| 182 | \r |
| 183 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 184 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 185 | \r |
| 186 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 187 | Register.\r |
| 188 | @param AndData The value to AND with the PCI configuration register.\r |
| 189 | @param OrData The value to OR with the result of the AND operation.\r |
| 190 | \r |
| 191 | @return The value written back to the PCI configuration register.\r |
| 192 | \r |
| 193 | **/\r |
| 194 | UINT8\r |
| 195 | EFIAPI\r |
| 196 | PciCf8AndThenOr8 (\r |
| 197 | IN UINTN Address,\r |
| 198 | IN UINT8 AndData,\r |
| 199 | IN UINT8 OrData\r |
| 200 | );\r |
| 201 | \r |
| 202 | /**\r |
| 203 | Reads a bit field of a PCI configuration register.\r |
| 204 | \r |
| 205 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r |
| 206 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 207 | returned.\r |
| 208 | \r |
| 209 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 210 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 211 | If StartBit is greater than 7, then ASSERT().\r |
| 212 | If EndBit is greater than 7, then ASSERT().\r |
| 213 | If EndBit is less than StartBit, then ASSERT().\r |
| 214 | \r |
| 215 | @param Address PCI configuration register to read.\r |
| 216 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 217 | Range 0..7.\r |
| 218 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 219 | Range 0..7.\r |
| 220 | \r |
| 221 | @return The value of the bit field read from the PCI configuration register.\r |
| 222 | \r |
| 223 | **/\r |
| 224 | UINT8\r |
| 225 | EFIAPI\r |
| 226 | PciCf8BitFieldRead8 (\r |
| 227 | IN UINTN Address,\r |
| 228 | IN UINTN StartBit,\r |
| 229 | IN UINTN EndBit\r |
| 230 | );\r |
| 231 | \r |
| 232 | /**\r |
| 233 | Writes a bit field to a PCI configuration register.\r |
| 234 | \r |
| 235 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 236 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 237 | destination PCI configuration register are preserved. The new value of the\r |
| 238 | 8-bit register is returned.\r |
| 239 | \r |
| 240 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 241 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 242 | If StartBit is greater than 7, then ASSERT().\r |
| 243 | If EndBit is greater than 7, then ASSERT().\r |
| 244 | If EndBit is less than StartBit, then ASSERT().\r |
| 245 | \r |
| 246 | @param Address PCI configuration register to write.\r |
| 247 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 248 | Range 0..7.\r |
| 249 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 250 | Range 0..7.\r |
| 251 | @param Value New value of the bit field.\r |
| 252 | \r |
| 253 | @return The value written back to the PCI configuration register.\r |
| 254 | \r |
| 255 | **/\r |
| 256 | UINT8\r |
| 257 | EFIAPI\r |
| 258 | PciCf8BitFieldWrite8 (\r |
| 259 | IN UINTN Address,\r |
| 260 | IN UINTN StartBit,\r |
| 261 | IN UINTN EndBit,\r |
| 262 | IN UINT8 Value\r |
| 263 | );\r |
| 264 | \r |
| 265 | /**\r |
| 266 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r |
| 267 | writes the result back to the bit field in the 8-bit port.\r |
| 268 | \r |
| 269 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
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270 | bitwise OR between the read result and the value specified by\r |
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271 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 272 | specified by Address. The value written to the PCI configuration register is\r |
| 273 | returned. This function must guarantee that all PCI read and write operations\r |
| 274 | are serialized. Extra left bits in OrData are stripped.\r |
| 275 | \r |
| 276 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 277 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 278 | If StartBit is greater than 7, then ASSERT().\r |
| 279 | If EndBit is greater than 7, then ASSERT().\r |
| 280 | If EndBit is less than StartBit, then ASSERT().\r |
| 281 | \r |
| 282 | @param Address PCI configuration register to write.\r |
| 283 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 284 | Range 0..7.\r |
| 285 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 286 | Range 0..7.\r |
| 287 | @param OrData The value to OR with the PCI configuration register.\r |
| 288 | \r |
| 289 | @return The value written back to the PCI configuration register.\r |
| 290 | \r |
| 291 | **/\r |
| 292 | UINT8\r |
| 293 | EFIAPI\r |
| 294 | PciCf8BitFieldOr8 (\r |
| 295 | IN UINTN Address,\r |
| 296 | IN UINTN StartBit,\r |
| 297 | IN UINTN EndBit,\r |
| 298 | IN UINT8 OrData\r |
| 299 | );\r |
| 300 | \r |
| 301 | /**\r |
| 302 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r |
| 303 | AND, and writes the result back to the bit field in the 8-bit register.\r |
| 304 | \r |
| 305 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 306 | bitwise AND between the read result and the value specified by AndData, and\r |
| 307 | writes the result to the 8-bit PCI configuration register specified by\r |
| 308 | Address. The value written to the PCI configuration register is returned.\r |
| 309 | This function must guarantee that all PCI read and write operations are\r |
| 310 | serialized. Extra left bits in AndData are stripped.\r |
| 311 | \r |
| 312 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 313 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 314 | If StartBit is greater than 7, then ASSERT().\r |
| 315 | If EndBit is greater than 7, then ASSERT().\r |
| 316 | If EndBit is less than StartBit, then ASSERT().\r |
| 317 | \r |
| 318 | @param Address PCI configuration register to write.\r |
| 319 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 320 | Range 0..7.\r |
| 321 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 322 | Range 0..7.\r |
| 323 | @param AndData The value to AND with the PCI configuration register.\r |
| 324 | \r |
| 325 | @return The value written back to the PCI configuration register.\r |
| 326 | \r |
| 327 | **/\r |
| 328 | UINT8\r |
| 329 | EFIAPI\r |
| 330 | PciCf8BitFieldAnd8 (\r |
| 331 | IN UINTN Address,\r |
| 332 | IN UINTN StartBit,\r |
| 333 | IN UINTN EndBit,\r |
| 334 | IN UINT8 AndData\r |
| 335 | );\r |
| 336 | \r |
| 337 | /**\r |
| 338 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r |
| 62991af2 |
339 | bitwise OR, and writes the result back to the bit field in the\r |
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340 | 8-bit port.\r |
| 341 | \r |
| 342 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 62991af2 |
343 | bitwise AND followed by a bitwise OR between the read result and\r |
| fb3df220 |
344 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
| 345 | configuration register specified by Address. The value written to the PCI\r |
| 346 | configuration register is returned. This function must guarantee that all PCI\r |
| 347 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 348 | OrData are stripped.\r |
| 349 | \r |
| 350 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 351 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 352 | If StartBit is greater than 7, then ASSERT().\r |
| 353 | If EndBit is greater than 7, then ASSERT().\r |
| 354 | If EndBit is less than StartBit, then ASSERT().\r |
| 355 | \r |
| 356 | @param Address PCI configuration register to write.\r |
| 357 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 358 | Range 0..7.\r |
| 359 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 360 | Range 0..7.\r |
| 361 | @param AndData The value to AND with the PCI configuration register.\r |
| 362 | @param OrData The value to OR with the result of the AND operation.\r |
| 363 | \r |
| 364 | @return The value written back to the PCI configuration register.\r |
| 365 | \r |
| 366 | **/\r |
| 367 | UINT8\r |
| 368 | EFIAPI\r |
| 369 | PciCf8BitFieldAndThenOr8 (\r |
| 370 | IN UINTN Address,\r |
| 371 | IN UINTN StartBit,\r |
| 372 | IN UINTN EndBit,\r |
| 373 | IN UINT8 AndData,\r |
| 374 | IN UINT8 OrData\r |
| 375 | );\r |
| 376 | \r |
| 377 | /**\r |
| 378 | Reads a 16-bit PCI configuration register.\r |
| 379 | \r |
| 380 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
| 381 | This function must guarantee that all PCI read and write operations are\r |
| 382 | serialized.\r |
| 383 | \r |
| 384 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 385 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 386 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 387 | \r |
| 388 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 389 | Register.\r |
| 390 | \r |
| 391 | @return The read value from the PCI configuration register.\r |
| 392 | \r |
| 393 | **/\r |
| 394 | UINT16\r |
| 395 | EFIAPI\r |
| 396 | PciCf8Read16 (\r |
| 397 | IN UINTN Address\r |
| 398 | );\r |
| 399 | \r |
| 400 | /**\r |
| 401 | Writes a 16-bit PCI configuration register.\r |
| 402 | \r |
| 403 | Writes the 16-bit PCI configuration register specified by Address with the\r |
| 404 | value specified by Value. Value is returned. This function must guarantee\r |
| 405 | that all PCI read and write operations are serialized.\r |
| 406 | \r |
| 407 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 408 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 409 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 410 | \r |
| 411 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 412 | Register.\r |
| 413 | @param Value The value to write.\r |
| 414 | \r |
| 415 | @return The value written to the PCI configuration register.\r |
| 416 | \r |
| 417 | **/\r |
| 418 | UINT16\r |
| 419 | EFIAPI\r |
| 420 | PciCf8Write16 (\r |
| 421 | IN UINTN Address,\r |
| 94646ec0 |
422 | IN UINT16 Value\r |
| fb3df220 |
423 | );\r |
| 424 | \r |
| 425 | /**\r |
| 62991af2 |
426 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
| fb3df220 |
427 | a 16-bit value.\r |
| 428 | \r |
| 429 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 62991af2 |
430 | bitwise OR between the read result and the value specified by\r |
| fb3df220 |
431 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 432 | specified by Address. The value written to the PCI configuration register is\r |
| 433 | returned. This function must guarantee that all PCI read and write operations\r |
| 434 | are serialized.\r |
| 435 | \r |
| 436 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 437 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 438 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 439 | \r |
| 440 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 441 | Register.\r |
| 442 | @param OrData The value to OR with the PCI configuration register.\r |
| 443 | \r |
| 444 | @return The value written back to the PCI configuration register.\r |
| 445 | \r |
| 446 | **/\r |
| 447 | UINT16\r |
| 448 | EFIAPI\r |
| 449 | PciCf8Or16 (\r |
| 450 | IN UINTN Address,\r |
| 451 | IN UINT16 OrData\r |
| 452 | );\r |
| 453 | \r |
| 454 | /**\r |
| 455 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 456 | value.\r |
| 457 | \r |
| 458 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 459 | bitwise AND between the read result and the value specified by AndData, and\r |
| 460 | writes the result to the 16-bit PCI configuration register specified by\r |
| 461 | Address. The value written to the PCI configuration register is returned.\r |
| 462 | This function must guarantee that all PCI read and write operations are\r |
| 463 | serialized.\r |
| 464 | \r |
| 465 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 466 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 467 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 468 | \r |
| 469 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 470 | Register.\r |
| 471 | @param AndData The value to AND with the PCI configuration register.\r |
| 472 | \r |
| 473 | @return The value written back to the PCI configuration register.\r |
| 474 | \r |
| 475 | **/\r |
| 476 | UINT16\r |
| 477 | EFIAPI\r |
| 478 | PciCf8And16 (\r |
| 479 | IN UINTN Address,\r |
| 480 | IN UINT16 AndData\r |
| 481 | );\r |
| 482 | \r |
| 483 | /**\r |
| 484 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 62991af2 |
485 | value, followed a bitwise OR with another 16-bit value.\r |
| fb3df220 |
486 | \r |
| 487 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 488 | bitwise AND between the read result and the value specified by AndData,\r |
| 62991af2 |
489 | performs a bitwise OR between the result of the AND operation and\r |
| fb3df220 |
490 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
| 491 | configuration register specified by Address. The value written to the PCI\r |
| 492 | configuration register is returned. This function must guarantee that all PCI\r |
| 493 | read and write operations are serialized.\r |
| 494 | \r |
| 495 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 496 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 497 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 498 | \r |
| 499 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 500 | Register.\r |
| 501 | @param AndData The value to AND with the PCI configuration register.\r |
| 502 | @param OrData The value to OR with the result of the AND operation.\r |
| 503 | \r |
| 504 | @return The value written back to the PCI configuration register.\r |
| 505 | \r |
| 506 | **/\r |
| 507 | UINT16\r |
| 508 | EFIAPI\r |
| 509 | PciCf8AndThenOr16 (\r |
| 510 | IN UINTN Address,\r |
| 511 | IN UINT16 AndData,\r |
| 512 | IN UINT16 OrData\r |
| 513 | );\r |
| 514 | \r |
| 515 | /**\r |
| 516 | Reads a bit field of a PCI configuration register.\r |
| 517 | \r |
| 518 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r |
| 519 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 520 | returned.\r |
| 521 | \r |
| 522 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 523 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 524 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 525 | If StartBit is greater than 15, then ASSERT().\r |
| 526 | If EndBit is greater than 15, then ASSERT().\r |
| 527 | If EndBit is less than StartBit, then ASSERT().\r |
| 528 | \r |
| 529 | @param Address PCI configuration register to read.\r |
| 530 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 531 | Range 0..15.\r |
| 532 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 533 | Range 0..15.\r |
| 534 | \r |
| 535 | @return The value of the bit field read from the PCI configuration register.\r |
| 536 | \r |
| 537 | **/\r |
| 538 | UINT16\r |
| 539 | EFIAPI\r |
| 540 | PciCf8BitFieldRead16 (\r |
| 541 | IN UINTN Address,\r |
| 542 | IN UINTN StartBit,\r |
| 543 | IN UINTN EndBit\r |
| 544 | );\r |
| 545 | \r |
| 546 | /**\r |
| 547 | Writes a bit field to a PCI configuration register.\r |
| 548 | \r |
| 549 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 550 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 551 | destination PCI configuration register are preserved. The new value of the\r |
| 552 | 16-bit register is returned.\r |
| 553 | \r |
| 554 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 555 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 556 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 557 | If StartBit is greater than 15, then ASSERT().\r |
| 558 | If EndBit is greater than 15, then ASSERT().\r |
| 559 | If EndBit is less than StartBit, then ASSERT().\r |
| 560 | \r |
| 561 | @param Address PCI configuration register to write.\r |
| 562 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 563 | Range 0..15.\r |
| 564 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 565 | Range 0..15.\r |
| 566 | @param Value New value of the bit field.\r |
| 567 | \r |
| 568 | @return The value written back to the PCI configuration register.\r |
| 569 | \r |
| 570 | **/\r |
| 571 | UINT16\r |
| 572 | EFIAPI\r |
| 573 | PciCf8BitFieldWrite16 (\r |
| 574 | IN UINTN Address,\r |
| 575 | IN UINTN StartBit,\r |
| 576 | IN UINTN EndBit,\r |
| 577 | IN UINT16 Value\r |
| 578 | );\r |
| 579 | \r |
| 580 | /**\r |
| 581 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r |
| 582 | writes the result back to the bit field in the 16-bit port.\r |
| 583 | \r |
| 584 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 62991af2 |
585 | bitwise OR between the read result and the value specified by\r |
| fb3df220 |
586 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 587 | specified by Address. The value written to the PCI configuration register is\r |
| 588 | returned. This function must guarantee that all PCI read and write operations\r |
| 589 | are serialized. Extra left bits in OrData are stripped.\r |
| 590 | \r |
| 591 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 592 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 593 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 594 | If StartBit is greater than 15, then ASSERT().\r |
| 595 | If EndBit is greater than 15, then ASSERT().\r |
| 596 | If EndBit is less than StartBit, then ASSERT().\r |
| 597 | \r |
| 598 | @param Address PCI configuration register to write.\r |
| 599 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 600 | Range 0..15.\r |
| 601 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 602 | Range 0..15.\r |
| 603 | @param OrData The value to OR with the PCI configuration register.\r |
| 604 | \r |
| 605 | @return The value written back to the PCI configuration register.\r |
| 606 | \r |
| 607 | **/\r |
| 608 | UINT16\r |
| 609 | EFIAPI\r |
| 610 | PciCf8BitFieldOr16 (\r |
| 611 | IN UINTN Address,\r |
| 612 | IN UINTN StartBit,\r |
| 613 | IN UINTN EndBit,\r |
| 614 | IN UINT16 OrData\r |
| 615 | );\r |
| 616 | \r |
| 617 | /**\r |
| 618 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r |
| 619 | AND, and writes the result back to the bit field in the 16-bit register.\r |
| 620 | \r |
| 621 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 622 | bitwise AND between the read result and the value specified by AndData, and\r |
| 623 | writes the result to the 16-bit PCI configuration register specified by\r |
| 624 | Address. The value written to the PCI configuration register is returned.\r |
| 625 | This function must guarantee that all PCI read and write operations are\r |
| 626 | serialized. Extra left bits in AndData are stripped.\r |
| 627 | \r |
| 628 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 629 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 630 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 631 | If StartBit is greater than 15, then ASSERT().\r |
| 632 | If EndBit is greater than 15, then ASSERT().\r |
| 633 | If EndBit is less than StartBit, then ASSERT().\r |
| 634 | \r |
| 635 | @param Address PCI configuration register to write.\r |
| 636 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 637 | Range 0..15.\r |
| 638 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 639 | Range 0..15.\r |
| 640 | @param AndData The value to AND with the PCI configuration register.\r |
| 641 | \r |
| 642 | @return The value written back to the PCI configuration register.\r |
| 643 | \r |
| 644 | **/\r |
| 645 | UINT16\r |
| 646 | EFIAPI\r |
| 647 | PciCf8BitFieldAnd16 (\r |
| 648 | IN UINTN Address,\r |
| 649 | IN UINTN StartBit,\r |
| 650 | IN UINTN EndBit,\r |
| 651 | IN UINT16 AndData\r |
| 652 | );\r |
| 653 | \r |
| 654 | /**\r |
| 655 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r |
| 62991af2 |
656 | bitwise OR, and writes the result back to the bit field in the\r |
| fb3df220 |
657 | 16-bit port.\r |
| 658 | \r |
| 659 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 62991af2 |
660 | bitwise AND followed by a bitwise OR between the read result and\r |
| fb3df220 |
661 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
| 662 | configuration register specified by Address. The value written to the PCI\r |
| 663 | configuration register is returned. This function must guarantee that all PCI\r |
| 664 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 665 | OrData are stripped.\r |
| 666 | \r |
| 667 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 668 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 669 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 670 | If StartBit is greater than 15, then ASSERT().\r |
| 671 | If EndBit is greater than 15, then ASSERT().\r |
| 672 | If EndBit is less than StartBit, then ASSERT().\r |
| 673 | \r |
| 674 | @param Address PCI configuration register to write.\r |
| 675 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 676 | Range 0..15.\r |
| 677 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 678 | Range 0..15.\r |
| 679 | @param AndData The value to AND with the PCI configuration register.\r |
| 680 | @param OrData The value to OR with the result of the AND operation.\r |
| 681 | \r |
| 682 | @return The value written back to the PCI configuration register.\r |
| 683 | \r |
| 684 | **/\r |
| 685 | UINT16\r |
| 686 | EFIAPI\r |
| 687 | PciCf8BitFieldAndThenOr16 (\r |
| 688 | IN UINTN Address,\r |
| 689 | IN UINTN StartBit,\r |
| 690 | IN UINTN EndBit,\r |
| 691 | IN UINT16 AndData,\r |
| 692 | IN UINT16 OrData\r |
| 693 | );\r |
| 694 | \r |
| 695 | /**\r |
| 696 | Reads a 32-bit PCI configuration register.\r |
| 697 | \r |
| 698 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
| 699 | This function must guarantee that all PCI read and write operations are\r |
| 700 | serialized.\r |
| 701 | \r |
| 702 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 703 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 704 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 705 | \r |
| 706 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 707 | Register.\r |
| 708 | \r |
| 709 | @return The read value from the PCI configuration register.\r |
| 710 | \r |
| 711 | **/\r |
| 712 | UINT32\r |
| 713 | EFIAPI\r |
| 714 | PciCf8Read32 (\r |
| 715 | IN UINTN Address\r |
| 716 | );\r |
| 717 | \r |
| 718 | /**\r |
| 719 | Writes a 32-bit PCI configuration register.\r |
| 720 | \r |
| 721 | Writes the 32-bit PCI configuration register specified by Address with the\r |
| 722 | value specified by Value. Value is returned. This function must guarantee\r |
| 723 | that all PCI read and write operations are serialized.\r |
| 724 | \r |
| 725 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 726 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 727 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 728 | \r |
| 729 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 730 | Register.\r |
| 731 | @param Value The value to write.\r |
| 732 | \r |
| 733 | @return The value written to the PCI configuration register.\r |
| 734 | \r |
| 735 | **/\r |
| 736 | UINT32\r |
| 737 | EFIAPI\r |
| 738 | PciCf8Write32 (\r |
| 739 | IN UINTN Address,\r |
| 94646ec0 |
740 | IN UINT32 Value\r |
| fb3df220 |
741 | );\r |
| 742 | \r |
| 743 | /**\r |
| 62991af2 |
744 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
| fb3df220 |
745 | a 32-bit value.\r |
| 746 | \r |
| 747 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 62991af2 |
748 | bitwise OR between the read result and the value specified by\r |
| fb3df220 |
749 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 750 | specified by Address. The value written to the PCI configuration register is\r |
| 751 | returned. This function must guarantee that all PCI read and write operations\r |
| 752 | are serialized.\r |
| 753 | \r |
| 754 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 755 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 756 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 757 | \r |
| 758 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 759 | Register.\r |
| 760 | @param OrData The value to OR with the PCI configuration register.\r |
| 761 | \r |
| 762 | @return The value written back to the PCI configuration register.\r |
| 763 | \r |
| 764 | **/\r |
| 765 | UINT32\r |
| 766 | EFIAPI\r |
| 767 | PciCf8Or32 (\r |
| 768 | IN UINTN Address,\r |
| 769 | IN UINT32 OrData\r |
| 770 | );\r |
| 771 | \r |
| 772 | /**\r |
| 773 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 774 | value.\r |
| 775 | \r |
| 776 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 777 | bitwise AND between the read result and the value specified by AndData, and\r |
| 778 | writes the result to the 32-bit PCI configuration register specified by\r |
| 779 | Address. The value written to the PCI configuration register is returned.\r |
| 780 | This function must guarantee that all PCI read and write operations are\r |
| 781 | serialized.\r |
| 782 | \r |
| 783 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 784 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 785 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 786 | \r |
| 787 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 788 | Register.\r |
| 789 | @param AndData The value to AND with the PCI configuration register.\r |
| 790 | \r |
| 791 | @return The value written back to the PCI configuration register.\r |
| 792 | \r |
| 793 | **/\r |
| 794 | UINT32\r |
| 795 | EFIAPI\r |
| 796 | PciCf8And32 (\r |
| 797 | IN UINTN Address,\r |
| 798 | IN UINT32 AndData\r |
| 799 | );\r |
| 800 | \r |
| 801 | /**\r |
| 802 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 62991af2 |
803 | value, followed a bitwise OR with another 32-bit value.\r |
| fb3df220 |
804 | \r |
| 805 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 806 | bitwise AND between the read result and the value specified by AndData,\r |
| 62991af2 |
807 | performs a bitwise OR between the result of the AND operation and\r |
| fb3df220 |
808 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
| 809 | configuration register specified by Address. The value written to the PCI\r |
| 810 | configuration register is returned. This function must guarantee that all PCI\r |
| 811 | read and write operations are serialized.\r |
| 812 | \r |
| 813 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 814 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 815 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 816 | \r |
| 817 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 818 | Register.\r |
| 819 | @param AndData The value to AND with the PCI configuration register.\r |
| 820 | @param OrData The value to OR with the result of the AND operation.\r |
| 821 | \r |
| 822 | @return The value written back to the PCI configuration register.\r |
| 823 | \r |
| 824 | **/\r |
| 825 | UINT32\r |
| 826 | EFIAPI\r |
| 827 | PciCf8AndThenOr32 (\r |
| 828 | IN UINTN Address,\r |
| 829 | IN UINT32 AndData,\r |
| 830 | IN UINT32 OrData\r |
| 831 | );\r |
| 832 | \r |
| 833 | /**\r |
| 834 | Reads a bit field of a PCI configuration register.\r |
| 835 | \r |
| 836 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r |
| 837 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 838 | returned.\r |
| 839 | \r |
| 840 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 841 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 842 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 843 | If StartBit is greater than 31, then ASSERT().\r |
| 844 | If EndBit is greater than 31, then ASSERT().\r |
| 845 | If EndBit is less than StartBit, then ASSERT().\r |
| 846 | \r |
| 847 | @param Address PCI configuration register to read.\r |
| 848 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 849 | Range 0..31.\r |
| 850 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 851 | Range 0..31.\r |
| 852 | \r |
| 853 | @return The value of the bit field read from the PCI configuration register.\r |
| 854 | \r |
| 855 | **/\r |
| 856 | UINT32\r |
| 857 | EFIAPI\r |
| 858 | PciCf8BitFieldRead32 (\r |
| 859 | IN UINTN Address,\r |
| 860 | IN UINTN StartBit,\r |
| 861 | IN UINTN EndBit\r |
| 862 | );\r |
| 863 | \r |
| 864 | /**\r |
| 865 | Writes a bit field to a PCI configuration register.\r |
| 866 | \r |
| 867 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 868 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 869 | destination PCI configuration register are preserved. The new value of the\r |
| 870 | 32-bit register is returned.\r |
| 871 | \r |
| 872 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 873 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 874 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 875 | If StartBit is greater than 31, then ASSERT().\r |
| 876 | If EndBit is greater than 31, then ASSERT().\r |
| 877 | If EndBit is less than StartBit, then ASSERT().\r |
| 878 | \r |
| 879 | @param Address PCI configuration register to write.\r |
| 880 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 881 | Range 0..31.\r |
| 882 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 883 | Range 0..31.\r |
| 884 | @param Value New value of the bit field.\r |
| 885 | \r |
| 886 | @return The value written back to the PCI configuration register.\r |
| 887 | \r |
| 888 | **/\r |
| 889 | UINT32\r |
| 890 | EFIAPI\r |
| 891 | PciCf8BitFieldWrite32 (\r |
| 892 | IN UINTN Address,\r |
| 893 | IN UINTN StartBit,\r |
| 894 | IN UINTN EndBit,\r |
| 895 | IN UINT32 Value\r |
| 896 | );\r |
| 897 | \r |
| 898 | /**\r |
| 899 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r |
| 900 | writes the result back to the bit field in the 32-bit port.\r |
| 901 | \r |
| 902 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 62991af2 |
903 | bitwise OR between the read result and the value specified by\r |
| fb3df220 |
904 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 905 | specified by Address. The value written to the PCI configuration register is\r |
| 906 | returned. This function must guarantee that all PCI read and write operations\r |
| 907 | are serialized. Extra left bits in OrData are stripped.\r |
| 908 | \r |
| 909 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 910 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 911 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 912 | If StartBit is greater than 31, then ASSERT().\r |
| 913 | If EndBit is greater than 31, then ASSERT().\r |
| 914 | If EndBit is less than StartBit, then ASSERT().\r |
| 915 | \r |
| 916 | @param Address PCI configuration register to write.\r |
| 917 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 918 | Range 0..31.\r |
| 919 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 920 | Range 0..31.\r |
| 921 | @param OrData The value to OR with the PCI configuration register.\r |
| 922 | \r |
| 923 | @return The value written back to the PCI configuration register.\r |
| 924 | \r |
| 925 | **/\r |
| 926 | UINT32\r |
| 927 | EFIAPI\r |
| 928 | PciCf8BitFieldOr32 (\r |
| 929 | IN UINTN Address,\r |
| 930 | IN UINTN StartBit,\r |
| 931 | IN UINTN EndBit,\r |
| 932 | IN UINT32 OrData\r |
| 933 | );\r |
| 934 | \r |
| 935 | /**\r |
| 936 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r |
| 937 | AND, and writes the result back to the bit field in the 32-bit register.\r |
| 938 | \r |
| 939 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 940 | bitwise AND between the read result and the value specified by AndData, and\r |
| 941 | writes the result to the 32-bit PCI configuration register specified by\r |
| 942 | Address. The value written to the PCI configuration register is returned.\r |
| 943 | This function must guarantee that all PCI read and write operations are\r |
| 944 | serialized. Extra left bits in AndData are stripped.\r |
| 945 | \r |
| 946 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 947 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 948 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 949 | If StartBit is greater than 31, then ASSERT().\r |
| 950 | If EndBit is greater than 31, then ASSERT().\r |
| 951 | If EndBit is less than StartBit, then ASSERT().\r |
| 952 | \r |
| 953 | @param Address PCI configuration register to write.\r |
| 954 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 955 | Range 0..31.\r |
| 956 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 957 | Range 0..31.\r |
| 958 | @param AndData The value to AND with the PCI configuration register.\r |
| 959 | \r |
| 960 | @return The value written back to the PCI configuration register.\r |
| 961 | \r |
| 962 | **/\r |
| 963 | UINT32\r |
| 964 | EFIAPI\r |
| 965 | PciCf8BitFieldAnd32 (\r |
| 966 | IN UINTN Address,\r |
| 967 | IN UINTN StartBit,\r |
| 968 | IN UINTN EndBit,\r |
| 969 | IN UINT32 AndData\r |
| 970 | );\r |
| 971 | \r |
| 972 | /**\r |
| 973 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r |
| 62991af2 |
974 | bitwise OR, and writes the result back to the bit field in the\r |
| fb3df220 |
975 | 32-bit port.\r |
| 976 | \r |
| 977 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 62991af2 |
978 | bitwise AND followed by a bitwise OR between the read result and\r |
| fb3df220 |
979 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
| 980 | configuration register specified by Address. The value written to the PCI\r |
| 981 | configuration register is returned. This function must guarantee that all PCI\r |
| 982 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 983 | OrData are stripped.\r |
| 984 | \r |
| 985 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 986 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 987 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 988 | If StartBit is greater than 31, then ASSERT().\r |
| 989 | If EndBit is greater than 31, then ASSERT().\r |
| 990 | If EndBit is less than StartBit, then ASSERT().\r |
| 991 | \r |
| 992 | @param Address PCI configuration register to write.\r |
| 993 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 994 | Range 0..31.\r |
| 995 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 996 | Range 0..31.\r |
| 997 | @param AndData The value to AND with the PCI configuration register.\r |
| 998 | @param OrData The value to OR with the result of the AND operation.\r |
| 999 | \r |
| 1000 | @return The value written back to the PCI configuration register.\r |
| 1001 | \r |
| 1002 | **/\r |
| 1003 | UINT32\r |
| 1004 | EFIAPI\r |
| 1005 | PciCf8BitFieldAndThenOr32 (\r |
| 1006 | IN UINTN Address,\r |
| 1007 | IN UINTN StartBit,\r |
| 1008 | IN UINTN EndBit,\r |
| 1009 | IN UINT32 AndData,\r |
| 1010 | IN UINT32 OrData\r |
| 1011 | );\r |
| 1012 | \r |
| 1013 | /**\r |
| 1014 | Reads a range of PCI configuration registers into a caller supplied buffer.\r |
| 1015 | \r |
| 1016 | Reads the range of PCI configuration registers specified by StartAddress and\r |
| 1017 | Size into the buffer specified by Buffer. This function only allows the PCI\r |
| 1018 | configuration registers from a single PCI function to be read. Size is\r |
| 1019 | returned. When possible 32-bit PCI configuration read cycles are used to read\r |
| 1020 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
| 1021 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
| 1022 | end of the range.\r |
| 1023 | \r |
| 1024 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1025 | If the register specified by StartAddress >= 0x100, then ASSERT().\r |
| 1026 | If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().\r |
| 1027 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1028 | \r |
| 1029 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1030 | Function and Register.\r |
| 1031 | @param Size Size in bytes of the transfer.\r |
| 1032 | @param Buffer Pointer to a buffer receiving the data read.\r |
| 1033 | \r |
| 9199040c |
1034 | @return Size read from StartAddress.\r |
| fb3df220 |
1035 | \r |
| 1036 | **/\r |
| 1037 | UINTN\r |
| 1038 | EFIAPI\r |
| 1039 | PciCf8ReadBuffer (\r |
| 1040 | IN UINTN StartAddress,\r |
| 1041 | IN UINTN Size,\r |
| 1042 | OUT VOID *Buffer\r |
| 1043 | );\r |
| 1044 | \r |
| 1045 | /**\r |
| 1046 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
| 1047 | configuration space.\r |
| 1048 | \r |
| 1049 | Writes the range of PCI configuration registers specified by StartAddress and\r |
| 1050 | Size from the buffer specified by Buffer. This function only allows the PCI\r |
| 1051 | configuration registers from a single PCI function to be written. Size is\r |
| 1052 | returned. When possible 32-bit PCI configuration write cycles are used to\r |
| 1053 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r |
| 1054 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
| 1055 | and the end of the range.\r |
| 1056 | \r |
| 1057 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1058 | If the register specified by StartAddress >= 0x100, then ASSERT().\r |
| 1059 | If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().\r |
| 1060 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1061 | \r |
| 1062 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1063 | Function and Register.\r |
| 1064 | @param Size Size in bytes of the transfer.\r |
| 1065 | @param Buffer Pointer to a buffer containing the data to write.\r |
| 1066 | \r |
| 9199040c |
1067 | @return Size written to StartAddress.\r |
| fb3df220 |
1068 | \r |
| 1069 | **/\r |
| 1070 | UINTN\r |
| 1071 | EFIAPI\r |
| 1072 | PciCf8WriteBuffer (\r |
| 1073 | IN UINTN StartAddress,\r |
| 1074 | IN UINTN Size,\r |
| 1075 | IN VOID *Buffer\r |
| 1076 | );\r |
| 1077 | \r |
| 1078 | #endif\r |
projects / mirror_edk2.git / blame