| fb3df220 |
1 | /** @file\r |
| 50a64e5b |
2 | Provides services to access PCI Configuration Space on a platform with multiple PCI segments.\r |
| badcbfb2 |
3 | \r |
| 4 | The PCI Segment Library function provide services to read, write, and modify the PCI configuration\r |
| 5 | registers on PCI root bridges on any supported PCI segment. These library services take a single \r |
| 6 | address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register. \r |
| 7 | The layout of this address parameter is as follows:\r |
| 8 | \r |
| 9 | PCI Register: Bits 0..11\r |
| 10 | PCI Function Bits 12..14\r |
| 11 | PCI Device Bits 15..19\r |
| 12 | PCI Bus Bits 20..27\r |
| 13 | Reserved Bits 28..31. Must be 0.\r |
| 14 | PCI Segment Bits 32..47\r |
| 15 | Reserved Bits 48..63. Must be 0.\r |
| 16 | \r |
| 17 | | Reserved (MBZ) | Segment | Reserved (MBZ) | Bus | Device | Function | Register |\r |
| 18 | 63 48 47 32 31 28 27 20 19 15 14 12 11 0\r |
| 19 | \r |
| 20 | These functions perform PCI configuration cycles using the default PCI configuration access \r |
| 21 | method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it \r |
| 22 | may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate \r |
| 23 | access method. Modules will typically use the PCI Segment Library for its PCI configuration \r |
| 24 | accesses when PCI Segments other than Segment #0 must be accessed. \r |
| fb3df220 |
25 | \r |
| 50a64e5b |
26 | Copyright (c) 2006 - 2008, Intel Corporation\r |
| 27 | All rights reserved. This program and the accompanying materials\r |
| 28 | are licensed and made available under the terms and conditions of the BSD License\r |
| 29 | which accompanies this distribution. The full text of the license may be found at\r |
| 30 | http://opensource.org/licenses/bsd-license.php\r |
| fb3df220 |
31 | \r |
| 50a64e5b |
32 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 33 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| fb3df220 |
34 | \r |
| fb3df220 |
35 | **/\r |
| 36 | \r |
| 37 | #ifndef __PCI_SEGMENT_LIB__\r |
| 38 | #define __PCI_SEGMENT_LIB__\r |
| 39 | \r |
| 40 | \r |
| 41 | /**\r |
| 42 | Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,\r |
| 43 | and PCI Register to an address that can be passed to the PCI Segment Library functions.\r |
| 44 | \r |
| 45 | Computes an address that is compatible with the PCI Segment Library functions.\r |
| 46 | The unused upper bits of Segment, Bus, Device, Function,\r |
| 47 | and Register are stripped prior to the generation of the address.\r |
| 48 | \r |
| 49 | @param Segment PCI Segment number. Range 0..65535.\r |
| 50 | @param Bus PCI Bus number. Range 0..255.\r |
| 51 | @param Device PCI Device number. Range 0..31.\r |
| 52 | @param Function PCI Function number. Range 0..7.\r |
| 53 | @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.\r |
| 54 | \r |
| 55 | @return The address that is compatible with the PCI Segment Library functions.\r |
| 56 | \r |
| 57 | **/\r |
| 58 | #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \\r |
| 59 | ( ((Register) & 0xfff) | \\r |
| 60 | (((Function) & 0x07) << 12) | \\r |
| 61 | (((Device) & 0x1f) << 15) | \\r |
| 62 | (((Bus) & 0xff) << 20) | \\r |
| 63 | (LShiftU64((Segment) & 0xffff, 32)) \\r |
| 64 | )\r |
| 65 | \r |
| f926e538 |
66 | /**\r |
| 67 | Register a PCI device so PCI configuration registers may be accessed after \r |
| 68 | SetVirtualAddressMap().\r |
| 69 | \r |
| 70 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 71 | \r |
| 72 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 73 | Register.\r |
| 74 | \r |
| 75 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
| 76 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r |
| 77 | after ExitBootServices().\r |
| 78 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r |
| 79 | at runtime could not be mapped.\r |
| 80 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r |
| 81 | complete the registration.\r |
| 82 | \r |
| 83 | **/\r |
| 84 | RETURN_STATUS\r |
| 85 | EFIAPI\r |
| 86 | PciSegmentRegisterForRuntimeAccess (\r |
| 87 | IN UINTN Address\r |
| 88 | );\r |
| 89 | \r |
| fb3df220 |
90 | /**\r |
| 91 | Reads an 8-bit PCI configuration register.\r |
| 92 | \r |
| 93 | Reads and returns the 8-bit PCI configuration register specified by Address.\r |
| 94 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
95 | \r |
| fb3df220 |
96 | If any reserved bits in Address are set, then ASSERT().\r |
| 97 | \r |
| 98 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 99 | \r |
| 100 | @return The 8-bit PCI configuration register specified by Address.\r |
| 101 | \r |
| 102 | **/\r |
| 103 | UINT8\r |
| 104 | EFIAPI\r |
| 105 | PciSegmentRead8 (\r |
| 106 | IN UINT64 Address\r |
| ed66e1bc |
107 | );\r |
| fb3df220 |
108 | \r |
| 109 | /**\r |
| 110 | Writes an 8-bit PCI configuration register.\r |
| 111 | \r |
| 112 | Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r |
| 113 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
114 | \r |
| fb3df220 |
115 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 116 | \r |
| 117 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 118 | @param Value The value to write.\r |
| 119 | \r |
| 120 | @return The parameter of Value.\r |
| 121 | \r |
| 122 | **/\r |
| 123 | UINT8\r |
| 124 | EFIAPI\r |
| 125 | PciSegmentWrite8 (\r |
| 126 | IN UINT64 Address,\r |
| 127 | IN UINT8 Value\r |
| ed66e1bc |
128 | );\r |
| fb3df220 |
129 | \r |
| 130 | /**\r |
| 131 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with an 8-bit value.\r |
| 132 | \r |
| 133 | Reads the 8-bit PCI configuration register specified by Address,\r |
| 134 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 135 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
| 136 | The value written to the PCI configuration register is returned.\r |
| 137 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
138 | \r |
| fb3df220 |
139 | If any reserved bits in Address are set, then ASSERT().\r |
| 140 | \r |
| 141 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 142 | @param OrData The value to OR with the PCI configuration register.\r |
| 143 | \r |
| 144 | @return The value written to the PCI configuration register.\r |
| 145 | \r |
| 146 | **/\r |
| 147 | UINT8\r |
| 148 | EFIAPI\r |
| 149 | PciSegmentOr8 (\r |
| 150 | IN UINT64 Address,\r |
| 151 | IN UINT8 OrData\r |
| ed66e1bc |
152 | );\r |
| fb3df220 |
153 | \r |
| 154 | /**\r |
| 155 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r |
| 156 | \r |
| 157 | Reads the 8-bit PCI configuration register specified by Address,\r |
| 158 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 159 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
| 160 | The value written to the PCI configuration register is returned.\r |
| 161 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 162 | If any reserved bits in Address are set, then ASSERT().\r |
| 163 | \r |
| 164 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 7d9333a9 |
165 | @param AndData The value to AND with the PCI configuration register.\r |
| fb3df220 |
166 | \r |
| 167 | @return The value written to the PCI configuration register.\r |
| 168 | \r |
| 169 | **/\r |
| 170 | UINT8\r |
| 171 | EFIAPI\r |
| 172 | PciSegmentAnd8 (\r |
| 173 | IN UINT64 Address,\r |
| 174 | IN UINT8 AndData\r |
| ed66e1bc |
175 | );\r |
| fb3df220 |
176 | \r |
| 177 | /**\r |
| 178 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r |
| 179 | followed a bitwise inclusive OR with another 8-bit value.\r |
| 180 | \r |
| 181 | Reads the 8-bit PCI configuration register specified by Address,\r |
| 182 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 183 | performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r |
| 184 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
| 185 | The value written to the PCI configuration register is returned.\r |
| 186 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
187 | \r |
| fb3df220 |
188 | If any reserved bits in Address are set, then ASSERT().\r |
| 189 | \r |
| 190 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 42eedea9 |
191 | @param AndData The value to AND with the PCI configuration register.\r |
| fb3df220 |
192 | @param OrData The value to OR with the PCI configuration register.\r |
| 193 | \r |
| 194 | @return The value written to the PCI configuration register.\r |
| 195 | \r |
| 196 | **/\r |
| 197 | UINT8\r |
| 198 | EFIAPI\r |
| 199 | PciSegmentAndThenOr8 (\r |
| 200 | IN UINT64 Address,\r |
| 201 | IN UINT8 AndData,\r |
| 202 | IN UINT8 OrData\r |
| ed66e1bc |
203 | );\r |
| fb3df220 |
204 | \r |
| 205 | /**\r |
| 206 | Reads a bit field of a PCI configuration register.\r |
| 207 | \r |
| 208 | Reads the bit field in an 8-bit PCI configuration register.\r |
| 209 | The bit field is specified by the StartBit and the EndBit.\r |
| 210 | The value of the bit field is returned.\r |
| badcbfb2 |
211 | \r |
| fb3df220 |
212 | If any reserved bits in Address are set, then ASSERT().\r |
| 213 | If StartBit is greater than 7, then ASSERT().\r |
| 214 | If EndBit is greater than 7, then ASSERT().\r |
| 215 | If EndBit is less than StartBit, then ASSERT().\r |
| 216 | \r |
| 217 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 218 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 219 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 220 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 221 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 222 | \r |
| 223 | @return The value of the bit field.\r |
| 224 | \r |
| 225 | **/\r |
| 226 | UINT8\r |
| 227 | EFIAPI\r |
| 228 | PciSegmentBitFieldRead8 (\r |
| 229 | IN UINT64 Address,\r |
| 230 | IN UINTN StartBit,\r |
| 231 | IN UINTN EndBit\r |
| ed66e1bc |
232 | );\r |
| fb3df220 |
233 | \r |
| 234 | /**\r |
| 235 | Writes a bit field to a PCI configuration register.\r |
| 236 | \r |
| 237 | Writes Value to the bit field of the PCI configuration register.\r |
| 238 | The bit field is specified by the StartBit and the EndBit.\r |
| 239 | All other bits in the destination PCI configuration register are preserved.\r |
| 240 | The new value of the 8-bit register is returned.\r |
| 241 | If any reserved bits in Address are set, then ASSERT().\r |
| 242 | If StartBit is greater than 7, then ASSERT().\r |
| 243 | If EndBit is greater than 7, then ASSERT().\r |
| 244 | If EndBit is less than StartBit, then ASSERT().\r |
| 245 | \r |
| 246 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 247 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 248 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 249 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 250 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 251 | @param Value New value of the bit field.\r |
| 252 | \r |
| 253 | @return The new value of the 8-bit register.\r |
| 254 | \r |
| 255 | **/\r |
| 256 | UINT8\r |
| 257 | EFIAPI\r |
| 258 | PciSegmentBitFieldWrite8 (\r |
| 259 | IN UINT64 Address,\r |
| 260 | IN UINTN StartBit,\r |
| 261 | IN UINTN EndBit,\r |
| 262 | IN UINT8 Value\r |
| ed66e1bc |
263 | );\r |
| fb3df220 |
264 | \r |
| 265 | /**\r |
| 266 | Reads the 8-bit PCI configuration register specified by Address,\r |
| 267 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 268 | and writes the result to the 8-bit PCI configuration register specified by Address. \r |
| badcbfb2 |
269 | \r |
| 270 | If any reserved bits in Address are set, then ASSERT().\r |
| 271 | If StartBit is greater than 7, then ASSERT().\r |
| 272 | If EndBit is greater than 7, then ASSERT().\r |
| 273 | If EndBit is less than StartBit, then ASSERT().\r |
| fb3df220 |
274 | \r |
| 275 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 276 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 277 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 278 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 279 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 280 | @param OrData The value to OR with the read value from the PCI configuration register.\r |
| 281 | \r |
| 282 | @return The value written to the PCI configuration register.\r |
| 283 | \r |
| 284 | **/\r |
| 285 | UINT8\r |
| 286 | EFIAPI\r |
| 287 | PciSegmentBitFieldOr8 (\r |
| 288 | IN UINT64 Address,\r |
| 289 | IN UINTN StartBit,\r |
| 290 | IN UINTN EndBit,\r |
| 291 | IN UINT8 OrData\r |
| ed66e1bc |
292 | );\r |
| fb3df220 |
293 | \r |
| 294 | /**\r |
| 295 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR,\r |
| 296 | and writes the result back to the bit field in the 8-bit port.\r |
| 297 | \r |
| 298 | Reads the 8-bit PCI configuration register specified by Address,\r |
| 299 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 300 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
| 301 | The value written to the PCI configuration register is returned.\r |
| 302 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 303 | Extra left bits in OrData are stripped.\r |
| badcbfb2 |
304 | \r |
| fb3df220 |
305 | If any reserved bits in Address are set, then ASSERT().\r |
| 306 | If StartBit is greater than 7, then ASSERT().\r |
| 307 | If EndBit is greater than 7, then ASSERT().\r |
| 308 | If EndBit is less than StartBit, then ASSERT().\r |
| 309 | \r |
| 310 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 311 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 312 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 313 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 314 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 315 | @param AndData The value to AND with the read value from the PCI configuration register.\r |
| 316 | \r |
| 317 | @return The value written to the PCI configuration register.\r |
| 318 | \r |
| 319 | **/\r |
| 320 | UINT8\r |
| 321 | EFIAPI\r |
| 322 | PciSegmentBitFieldAnd8 (\r |
| 323 | IN UINT64 Address,\r |
| 324 | IN UINTN StartBit,\r |
| 325 | IN UINTN EndBit,\r |
| 326 | IN UINT8 AndData\r |
| ed66e1bc |
327 | );\r |
| fb3df220 |
328 | \r |
| 329 | /**\r |
| 330 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND,\r |
| 331 | and writes the result back to the bit field in the 8-bit register.\r |
| 332 | \r |
| 333 | Reads the 8-bit PCI configuration register specified by Address,\r |
| 334 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 335 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
| 336 | The value written to the PCI configuration register is returned.\r |
| 337 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 338 | Extra left bits in AndData are stripped.\r |
| badcbfb2 |
339 | \r |
| fb3df220 |
340 | If any reserved bits in Address are set, then ASSERT().\r |
| 341 | If StartBit is greater than 7, then ASSERT().\r |
| 342 | If EndBit is greater than 7, then ASSERT().\r |
| 343 | If EndBit is less than StartBit, then ASSERT().\r |
| 344 | \r |
| 345 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 346 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 347 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 348 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 349 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 350 | @param AndData The value to AND with the read value from the PCI configuration register.\r |
| 351 | @param OrData The value to OR with the read value from the PCI configuration register.\r |
| 352 | \r |
| 353 | @return The value written to the PCI configuration register.\r |
| 354 | \r |
| 355 | **/\r |
| 356 | UINT8\r |
| 357 | EFIAPI\r |
| 358 | PciSegmentBitFieldAndThenOr8 (\r |
| 359 | IN UINT64 Address,\r |
| 360 | IN UINTN StartBit,\r |
| 361 | IN UINTN EndBit,\r |
| 362 | IN UINT8 AndData,\r |
| 363 | IN UINT8 OrData\r |
| ed66e1bc |
364 | );\r |
| fb3df220 |
365 | \r |
| 366 | /**\r |
| 367 | Reads a 16-bit PCI configuration register.\r |
| 368 | \r |
| 369 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
| 370 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
371 | \r |
| fb3df220 |
372 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
373 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| fb3df220 |
374 | \r |
| 375 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 376 | \r |
| 377 | @return The 16-bit PCI configuration register specified by Address.\r |
| 378 | \r |
| 379 | **/\r |
| 380 | UINT16\r |
| 381 | EFIAPI\r |
| 382 | PciSegmentRead16 (\r |
| 383 | IN UINT64 Address\r |
| ed66e1bc |
384 | );\r |
| fb3df220 |
385 | \r |
| 386 | /**\r |
| 387 | Writes a 16-bit PCI configuration register.\r |
| 388 | \r |
| 389 | Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r |
| 390 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
391 | \r |
| 392 | If any reserved bits in Address are set, then ASSERT().\r |
| 393 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| fb3df220 |
394 | \r |
| 395 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 396 | @param Value The value to write.\r |
| 397 | \r |
| 398 | @return The parameter of Value.\r |
| 399 | \r |
| 400 | **/\r |
| 401 | UINT16\r |
| 402 | EFIAPI\r |
| 403 | PciSegmentWrite16 (\r |
| 404 | IN UINT64 Address,\r |
| 405 | IN UINT16 Value\r |
| ed66e1bc |
406 | );\r |
| fb3df220 |
407 | \r |
| 408 | /**\r |
| 409 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with a 16-bit value.\r |
| 410 | \r |
| 411 | Reads the 16-bit PCI configuration register specified by Address,\r |
| 412 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 413 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
| 414 | The value written to the PCI configuration register is returned.\r |
| 415 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
416 | \r |
| fb3df220 |
417 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
418 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| fb3df220 |
419 | \r |
| 420 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 421 | @param OrData The value to OR with the PCI configuration register.\r |
| 422 | \r |
| 423 | @return The value written to the PCI configuration register.\r |
| 424 | \r |
| 425 | **/\r |
| 426 | UINT16\r |
| 427 | EFIAPI\r |
| 428 | PciSegmentOr16 (\r |
| 429 | IN UINT64 Address,\r |
| 430 | IN UINT16 OrData\r |
| ed66e1bc |
431 | );\r |
| fb3df220 |
432 | \r |
| 433 | /**\r |
| 434 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r |
| 435 | \r |
| 436 | Reads the 16-bit PCI configuration register specified by Address,\r |
| 437 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 438 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
| 439 | The value written to the PCI configuration register is returned.\r |
| 440 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
441 | \r |
| fb3df220 |
442 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
443 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 444 | \r |
| fb3df220 |
445 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 7d9333a9 |
446 | @param AndData The value to AND with the PCI configuration register.\r |
| fb3df220 |
447 | \r |
| 448 | @return The value written to the PCI configuration register.\r |
| 449 | \r |
| 450 | **/\r |
| 451 | UINT16\r |
| 452 | EFIAPI\r |
| 453 | PciSegmentAnd16 (\r |
| 454 | IN UINT64 Address,\r |
| 455 | IN UINT16 AndData\r |
| ed66e1bc |
456 | );\r |
| fb3df220 |
457 | \r |
| 458 | /**\r |
| 459 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r |
| 460 | followed a bitwise inclusive OR with another 16-bit value.\r |
| 461 | \r |
| 462 | Reads the 16-bit PCI configuration register specified by Address,\r |
| 463 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 464 | performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r |
| 465 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
| 466 | The value written to the PCI configuration register is returned.\r |
| 467 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
468 | \r |
| fb3df220 |
469 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
470 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| fb3df220 |
471 | \r |
| 472 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 42eedea9 |
473 | @param AndData The value to AND with the PCI configuration register.\r |
| fb3df220 |
474 | @param OrData The value to OR with the PCI configuration register.\r |
| 475 | \r |
| 476 | @return The value written to the PCI configuration register.\r |
| 477 | \r |
| 478 | **/\r |
| 479 | UINT16\r |
| 480 | EFIAPI\r |
| 481 | PciSegmentAndThenOr16 (\r |
| 482 | IN UINT64 Address,\r |
| 483 | IN UINT16 AndData,\r |
| 484 | IN UINT16 OrData\r |
| ed66e1bc |
485 | );\r |
| fb3df220 |
486 | \r |
| 487 | /**\r |
| 488 | Reads a bit field of a PCI configuration register.\r |
| 489 | \r |
| 490 | Reads the bit field in a 16-bit PCI configuration register.\r |
| 491 | The bit field is specified by the StartBit and the EndBit.\r |
| 492 | The value of the bit field is returned.\r |
| badcbfb2 |
493 | \r |
| fb3df220 |
494 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
495 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| fb3df220 |
496 | If StartBit is greater than 7, then ASSERT().\r |
| 497 | If EndBit is greater than 7, then ASSERT().\r |
| 498 | If EndBit is less than StartBit, then ASSERT().\r |
| 499 | \r |
| 500 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 501 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 502 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 503 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 504 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 505 | \r |
| 506 | @return The value of the bit field.\r |
| 507 | \r |
| 508 | **/\r |
| 509 | UINT16\r |
| 510 | EFIAPI\r |
| 511 | PciSegmentBitFieldRead16 (\r |
| 512 | IN UINT64 Address,\r |
| 513 | IN UINTN StartBit,\r |
| 514 | IN UINTN EndBit\r |
| ed66e1bc |
515 | );\r |
| fb3df220 |
516 | \r |
| 517 | /**\r |
| 518 | Writes a bit field to a PCI configuration register.\r |
| 519 | \r |
| 520 | Writes Value to the bit field of the PCI configuration register.\r |
| 521 | The bit field is specified by the StartBit and the EndBit.\r |
| 522 | All other bits in the destination PCI configuration register are preserved.\r |
| 523 | The new value of the 16-bit register is returned.\r |
| badcbfb2 |
524 | \r |
| fb3df220 |
525 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
526 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| fb3df220 |
527 | If StartBit is greater than 7, then ASSERT().\r |
| 528 | If EndBit is greater than 7, then ASSERT().\r |
| 529 | If EndBit is less than StartBit, then ASSERT().\r |
| 530 | \r |
| 531 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 532 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 533 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 534 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 535 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 536 | @param Value New value of the bit field.\r |
| 537 | \r |
| 538 | @return The new value of the 16-bit register.\r |
| 539 | \r |
| 540 | **/\r |
| 541 | UINT16\r |
| 542 | EFIAPI\r |
| 543 | PciSegmentBitFieldWrite16 (\r |
| 544 | IN UINT64 Address,\r |
| 545 | IN UINTN StartBit,\r |
| 546 | IN UINTN EndBit,\r |
| 547 | IN UINT16 Value\r |
| ed66e1bc |
548 | );\r |
| fb3df220 |
549 | \r |
| 550 | /**\r |
| 551 | Reads the 16-bit PCI configuration register specified by Address,\r |
| 552 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 553 | and writes the result to the 16-bit PCI configuration register specified by Address. \r |
| 554 | \r |
| badcbfb2 |
555 | If any reserved bits in Address are set, then ASSERT().\r |
| 556 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 557 | If StartBit is greater than 15, then ASSERT().\r |
| 558 | If EndBit is greater than 15, then ASSERT().\r |
| 559 | If EndBit is less than StartBit, then ASSERT().\r |
| 560 | \r |
| fb3df220 |
561 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 562 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 563 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 564 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 565 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 566 | @param OrData The value to OR with the read value from the PCI configuration register.\r |
| 567 | \r |
| 568 | @return The value written to the PCI configuration register.\r |
| 569 | \r |
| 570 | **/\r |
| 571 | UINT16\r |
| 572 | EFIAPI\r |
| 573 | PciSegmentBitFieldOr16 (\r |
| 574 | IN UINT64 Address,\r |
| 575 | IN UINTN StartBit,\r |
| 576 | IN UINTN EndBit,\r |
| 577 | IN UINT16 OrData\r |
| ed66e1bc |
578 | );\r |
| fb3df220 |
579 | \r |
| 580 | /**\r |
| 581 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,\r |
| 582 | and writes the result back to the bit field in the 16-bit port.\r |
| 583 | \r |
| 584 | Reads the 16-bit PCI configuration register specified by Address,\r |
| 585 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 586 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
| 587 | The value written to the PCI configuration register is returned.\r |
| 588 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 589 | Extra left bits in OrData are stripped.\r |
| badcbfb2 |
590 | \r |
| fb3df220 |
591 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
592 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| fb3df220 |
593 | If StartBit is greater than 7, then ASSERT().\r |
| 594 | If EndBit is greater than 7, then ASSERT().\r |
| 595 | If EndBit is less than StartBit, then ASSERT().\r |
| 596 | \r |
| 597 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 598 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 599 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 600 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 601 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 602 | @param AndData The value to AND with the read value from the PCI configuration register.\r |
| 603 | \r |
| 604 | @return The value written to the PCI configuration register.\r |
| 605 | \r |
| 606 | **/\r |
| 607 | UINT16\r |
| 608 | EFIAPI\r |
| 609 | PciSegmentBitFieldAnd16 (\r |
| 610 | IN UINT64 Address,\r |
| 611 | IN UINTN StartBit,\r |
| 612 | IN UINTN EndBit,\r |
| 613 | IN UINT16 AndData\r |
| ed66e1bc |
614 | );\r |
| fb3df220 |
615 | \r |
| 616 | /**\r |
| 617 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND,\r |
| 618 | and writes the result back to the bit field in the 16-bit register.\r |
| 619 | \r |
| 620 | Reads the 16-bit PCI configuration register specified by Address,\r |
| 621 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 622 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
| 623 | The value written to the PCI configuration register is returned.\r |
| 624 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 625 | Extra left bits in AndData are stripped.\r |
| badcbfb2 |
626 | \r |
| fb3df220 |
627 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
628 | If Address is not aligned on a 16-bit boundary, then ASSERT()..\r |
| fb3df220 |
629 | If StartBit is greater than 7, then ASSERT().\r |
| 630 | If EndBit is greater than 7, then ASSERT().\r |
| 631 | If EndBit is less than StartBit, then ASSERT().\r |
| 632 | \r |
| 633 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 634 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 635 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 636 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 637 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 638 | @param AndData The value to AND with the read value from the PCI configuration register.\r |
| 639 | @param OrData The value to OR with the read value from the PCI configuration register.\r |
| 640 | \r |
| 641 | @return The value written to the PCI configuration register.\r |
| 642 | \r |
| 643 | **/\r |
| 644 | UINT16\r |
| 645 | EFIAPI\r |
| 646 | PciSegmentBitFieldAndThenOr16 (\r |
| 647 | IN UINT64 Address,\r |
| 648 | IN UINTN StartBit,\r |
| 649 | IN UINTN EndBit,\r |
| 650 | IN UINT16 AndData,\r |
| 651 | IN UINT16 OrData\r |
| ed66e1bc |
652 | );\r |
| fb3df220 |
653 | \r |
| 654 | /**\r |
| 655 | Reads a 32-bit PCI configuration register.\r |
| 656 | \r |
| 657 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
| 658 | This function must guarantee that all PCI read and write operations are serialized.\r |
| fb3df220 |
659 | \r |
| badcbfb2 |
660 | If any reserved bits in Address are set, then ASSERT().\r |
| 661 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 662 | \r |
| fb3df220 |
663 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 664 | \r |
| 665 | @return The 32-bit PCI configuration register specified by Address.\r |
| 666 | \r |
| 667 | **/\r |
| 668 | UINT32\r |
| 669 | EFIAPI\r |
| 670 | PciSegmentRead32 (\r |
| 671 | IN UINT64 Address\r |
| ed66e1bc |
672 | );\r |
| fb3df220 |
673 | \r |
| 674 | /**\r |
| 675 | Writes a 32-bit PCI configuration register.\r |
| 676 | \r |
| 677 | Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r |
| 678 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
679 | \r |
| 680 | If any reserved bits in Address are set, then ASSERT().\r |
| 681 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| fb3df220 |
682 | \r |
| 683 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 684 | @param Value The value to write.\r |
| 685 | \r |
| 686 | @return The parameter of Value.\r |
| 687 | \r |
| 688 | **/\r |
| 689 | UINT32\r |
| 690 | EFIAPI\r |
| 691 | PciSegmentWrite32 (\r |
| 692 | IN UINT64 Address,\r |
| 693 | IN UINT32 Value\r |
| ed66e1bc |
694 | );\r |
| fb3df220 |
695 | \r |
| 696 | /**\r |
| 697 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with a 32-bit value.\r |
| 698 | \r |
| 699 | Reads the 32-bit PCI configuration register specified by Address,\r |
| 700 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 701 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
| 702 | The value written to the PCI configuration register is returned.\r |
| 703 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
704 | \r |
| fb3df220 |
705 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
706 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| fb3df220 |
707 | \r |
| 708 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 709 | @param OrData The value to OR with the PCI configuration register.\r |
| 710 | \r |
| 711 | @return The value written to the PCI configuration register.\r |
| 712 | \r |
| 713 | **/\r |
| 714 | UINT32\r |
| 715 | EFIAPI\r |
| 716 | PciSegmentOr32 (\r |
| 717 | IN UINT64 Address,\r |
| 718 | IN UINT32 OrData\r |
| ed66e1bc |
719 | );\r |
| fb3df220 |
720 | \r |
| 721 | /**\r |
| 722 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r |
| 723 | \r |
| 724 | Reads the 32-bit PCI configuration register specified by Address,\r |
| 725 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 726 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
| 727 | The value written to the PCI configuration register is returned.\r |
| 728 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
729 | \r |
| fb3df220 |
730 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
731 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| fb3df220 |
732 | \r |
| 733 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 7d9333a9 |
734 | @param AndData The value to AND with the PCI configuration register.\r |
| fb3df220 |
735 | \r |
| 736 | @return The value written to the PCI configuration register.\r |
| 737 | \r |
| 738 | **/\r |
| 739 | UINT32\r |
| 740 | EFIAPI\r |
| 741 | PciSegmentAnd32 (\r |
| 742 | IN UINT64 Address,\r |
| 743 | IN UINT32 AndData\r |
| ed66e1bc |
744 | );\r |
| fb3df220 |
745 | \r |
| 746 | /**\r |
| 747 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r |
| 748 | followed a bitwise inclusive OR with another 32-bit value.\r |
| 749 | \r |
| 750 | Reads the 32-bit PCI configuration register specified by Address,\r |
| 751 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 752 | performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r |
| 753 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
| 754 | The value written to the PCI configuration register is returned.\r |
| 755 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
756 | \r |
| fb3df220 |
757 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
758 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| fb3df220 |
759 | \r |
| 760 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 7d9333a9 |
761 | @param AndData The value to AND with the PCI configuration register.\r |
| fb3df220 |
762 | @param OrData The value to OR with the PCI configuration register.\r |
| 763 | \r |
| 764 | @return The value written to the PCI configuration register.\r |
| 765 | \r |
| 766 | **/\r |
| 767 | UINT32\r |
| 768 | EFIAPI\r |
| 769 | PciSegmentAndThenOr32 (\r |
| 770 | IN UINT64 Address,\r |
| 771 | IN UINT32 AndData,\r |
| 772 | IN UINT32 OrData\r |
| ed66e1bc |
773 | );\r |
| fb3df220 |
774 | \r |
| 775 | /**\r |
| 776 | Reads a bit field of a PCI configuration register.\r |
| 777 | \r |
| 778 | Reads the bit field in a 32-bit PCI configuration register.\r |
| 779 | The bit field is specified by the StartBit and the EndBit.\r |
| 780 | The value of the bit field is returned.\r |
| badcbfb2 |
781 | \r |
| fb3df220 |
782 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
783 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| fb3df220 |
784 | If StartBit is greater than 7, then ASSERT().\r |
| 785 | If EndBit is greater than 7, then ASSERT().\r |
| 786 | If EndBit is less than StartBit, then ASSERT().\r |
| 787 | \r |
| 788 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 789 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 790 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 791 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 792 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 793 | \r |
| 794 | @return The value of the bit field.\r |
| 795 | \r |
| 796 | **/\r |
| 797 | UINT32\r |
| 798 | EFIAPI\r |
| 799 | PciSegmentBitFieldRead32 (\r |
| 800 | IN UINT64 Address,\r |
| 801 | IN UINTN StartBit,\r |
| 802 | IN UINTN EndBit\r |
| ed66e1bc |
803 | );\r |
| fb3df220 |
804 | \r |
| 805 | /**\r |
| 806 | Writes a bit field to a PCI configuration register.\r |
| 807 | \r |
| 808 | Writes Value to the bit field of the PCI configuration register.\r |
| 809 | The bit field is specified by the StartBit and the EndBit.\r |
| 810 | All other bits in the destination PCI configuration register are preserved.\r |
| 811 | The new value of the 32-bit register is returned.\r |
| badcbfb2 |
812 | \r |
| fb3df220 |
813 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
814 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| fb3df220 |
815 | If StartBit is greater than 7, then ASSERT().\r |
| 816 | If EndBit is greater than 7, then ASSERT().\r |
| 817 | If EndBit is less than StartBit, then ASSERT().\r |
| 818 | \r |
| 819 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 820 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 821 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 822 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 823 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 824 | @param Value New value of the bit field.\r |
| 825 | \r |
| 826 | @return The new value of the 32-bit register.\r |
| 827 | \r |
| 828 | **/\r |
| 829 | UINT32\r |
| 830 | EFIAPI\r |
| 831 | PciSegmentBitFieldWrite32 (\r |
| 832 | IN UINT64 Address,\r |
| 833 | IN UINTN StartBit,\r |
| 834 | IN UINTN EndBit,\r |
| 835 | IN UINT32 Value\r |
| ed66e1bc |
836 | );\r |
| fb3df220 |
837 | \r |
| 838 | /**\r |
| 839 | Reads the 32-bit PCI configuration register specified by Address,\r |
| 840 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 841 | and writes the result to the 32-bit PCI configuration register specified by Address. \r |
| badcbfb2 |
842 | \r |
| 843 | If any reserved bits in Address are set, then ASSERT().\r |
| 844 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 845 | If StartBit is greater than 7, then ASSERT().\r |
| 846 | If EndBit is greater than 7, then ASSERT().\r |
| 847 | If EndBit is less than StartBit, then ASSERT().\r |
| 848 | \r |
| fb3df220 |
849 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 850 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 851 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 852 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 853 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 854 | @param OrData The value to OR with the read value from the PCI configuration register.\r |
| 855 | \r |
| 856 | @return The value written to the PCI configuration register.\r |
| 857 | \r |
| 858 | **/\r |
| 859 | UINT32\r |
| 860 | EFIAPI\r |
| 861 | PciSegmentBitFieldOr32 (\r |
| 862 | IN UINT64 Address,\r |
| 863 | IN UINTN StartBit,\r |
| 864 | IN UINTN EndBit,\r |
| 865 | IN UINT32 OrData\r |
| ed66e1bc |
866 | );\r |
| fb3df220 |
867 | \r |
| 868 | /**\r |
| 869 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR,\r |
| 870 | and writes the result back to the bit field in the 32-bit port.\r |
| 871 | \r |
| 872 | Reads the 32-bit PCI configuration register specified by Address,\r |
| 873 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 874 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
| 875 | The value written to the PCI configuration register is returned.\r |
| 876 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 877 | Extra left bits in OrData are stripped.\r |
| badcbfb2 |
878 | \r |
| fb3df220 |
879 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
880 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| fb3df220 |
881 | If StartBit is greater than 7, then ASSERT().\r |
| 882 | If EndBit is greater than 7, then ASSERT().\r |
| 883 | If EndBit is less than StartBit, then ASSERT().\r |
| 884 | \r |
| 885 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 886 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 887 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 888 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 889 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 890 | @param AndData The value to AND with the read value from the PCI configuration register.\r |
| 891 | \r |
| 892 | @return The value written to the PCI configuration register.\r |
| 893 | \r |
| 894 | **/\r |
| 895 | UINT32\r |
| 896 | EFIAPI\r |
| 897 | PciSegmentBitFieldAnd32 (\r |
| 898 | IN UINT64 Address,\r |
| 899 | IN UINTN StartBit,\r |
| 900 | IN UINTN EndBit,\r |
| 901 | IN UINT32 AndData\r |
| ed66e1bc |
902 | );\r |
| fb3df220 |
903 | \r |
| 904 | /**\r |
| 905 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND,\r |
| 906 | and writes the result back to the bit field in the 32-bit register.\r |
| 907 | \r |
| 908 | Reads the 32-bit PCI configuration register specified by Address,\r |
| 909 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 910 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
| 911 | The value written to the PCI configuration register is returned.\r |
| 912 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 913 | Extra left bits in AndData are stripped.\r |
| badcbfb2 |
914 | \r |
| fb3df220 |
915 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
916 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| fb3df220 |
917 | If StartBit is greater than 7, then ASSERT().\r |
| 918 | If EndBit is greater than 7, then ASSERT().\r |
| 919 | If EndBit is less than StartBit, then ASSERT().\r |
| 920 | \r |
| 921 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 922 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 923 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 924 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 925 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 926 | @param AndData The value to AND with the read value from the PCI configuration register.\r |
| 927 | @param OrData The value to OR with the read value from the PCI configuration register.\r |
| 928 | \r |
| 929 | @return The value written to the PCI configuration register.\r |
| 930 | \r |
| 931 | **/\r |
| 932 | UINT32\r |
| 933 | EFIAPI\r |
| 934 | PciSegmentBitFieldAndThenOr32 (\r |
| 935 | IN UINT64 Address,\r |
| 936 | IN UINTN StartBit,\r |
| 937 | IN UINTN EndBit,\r |
| 938 | IN UINT32 AndData,\r |
| 939 | IN UINT32 OrData\r |
| ed66e1bc |
940 | );\r |
| fb3df220 |
941 | \r |
| 942 | /**\r |
| 943 | Reads a range of PCI configuration registers into a caller supplied buffer.\r |
| 944 | \r |
| 945 | Reads the range of PCI configuration registers specified by StartAddress\r |
| 946 | and Size into the buffer specified by Buffer.\r |
| 947 | This function only allows the PCI configuration registers from a single PCI function to be read.\r |
| 948 | Size is returned.\r |
| badcbfb2 |
949 | \r |
| fb3df220 |
950 | If any reserved bits in StartAddress are set, then ASSERT().\r |
| 951 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 952 | If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().\r |
| badcbfb2 |
953 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| fb3df220 |
954 | \r |
| 955 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 956 | @param Size Size in bytes of the transfer.\r |
| 957 | @param Buffer Pointer to a buffer receiving the data read.\r |
| 958 | \r |
| badcbfb2 |
959 | @return The parameter of Size.\r |
| fb3df220 |
960 | \r |
| 961 | **/\r |
| 962 | UINTN\r |
| 963 | EFIAPI\r |
| 964 | PciSegmentReadBuffer (\r |
| 965 | IN UINT64 StartAddress,\r |
| 966 | IN UINTN Size,\r |
| 967 | OUT VOID *Buffer\r |
| ed66e1bc |
968 | );\r |
| fb3df220 |
969 | \r |
| 970 | /**\r |
| 971 | Copies the data in a caller supplied buffer to a specified range of PCI configuration space.\r |
| 972 | \r |
| 973 | Writes the range of PCI configuration registers specified by StartAddress\r |
| 974 | and Size from the buffer specified by Buffer.\r |
| 975 | This function only allows the PCI configuration registers from a single PCI function to be written.\r |
| 976 | Size is returned.\r |
| badcbfb2 |
977 | \r |
| fb3df220 |
978 | If any reserved bits in StartAddress are set, then ASSERT().\r |
| 979 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 980 | If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().\r |
| 981 | If Buffer is NULL, then ASSERT().\r |
| 982 | \r |
| 983 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 984 | @param Size Size in bytes of the transfer.\r |
| 985 | @param Buffer Pointer to a buffer containing the data to write.\r |
| 986 | \r |
| badcbfb2 |
987 | @return The parameter of Size.\r |
| fb3df220 |
988 | \r |
| 989 | **/\r |
| 990 | UINTN\r |
| 991 | EFIAPI\r |
| 992 | PciSegmentWriteBuffer (\r |
| 993 | IN UINT64 StartAddress,\r |
| 994 | IN UINTN Size,\r |
| 995 | IN VOID *Buffer\r |
| ed66e1bc |
996 | );\r |
| fb3df220 |
997 | \r |
| 998 | #endif\r |
projects / mirror_edk2.git / blame