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4006b0b5 EL |
1 | /** @file\r |
2 | Include file matches things in PI.\r | |
3 | \r | |
9095d37b | 4 | Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
4006b0b5 EL |
6 | \r |
7 | @par Revision Reference:\r | |
8 | PI Version 1.3\r | |
9 | \r | |
10 | **/\r | |
11 | \r | |
12 | #ifndef __PI_I2C_H__\r | |
13 | #define __PI_I2C_H__\r | |
14 | \r | |
15 | ///\r | |
16 | /// A 10-bit slave address is or'ed with the following value enabling the\r | |
17 | /// I2C protocol stack to address the duplicated address space between 0\r | |
18 | // and 127 in 10-bit mode.\r | |
19 | ///\r | |
2f88bd3a | 20 | #define I2C_ADDRESSING_10_BIT 0x80000000\r |
4006b0b5 EL |
21 | \r |
22 | ///\r | |
23 | /// I2C controller capabilities\r | |
24 | ///\r | |
25 | /// The EFI_I2C_CONTROLLER_CAPABILITIES specifies the capabilities of the\r | |
26 | /// I2C host controller. The StructureSizeInBytes enables variations of\r | |
27 | /// this structure to be identified if there is need to extend this\r | |
28 | /// structure in the future.\r | |
29 | ///\r | |
30 | typedef struct {\r | |
31 | ///\r | |
32 | /// Length of this data structure in bytes\r | |
33 | ///\r | |
2f88bd3a | 34 | UINT32 StructureSizeInBytes;\r |
4006b0b5 EL |
35 | \r |
36 | ///\r | |
37 | /// The maximum number of bytes the I2C host controller is able to\r | |
38 | /// receive from the I2C bus.\r | |
39 | ///\r | |
2f88bd3a | 40 | UINT32 MaximumReceiveBytes;\r |
4006b0b5 EL |
41 | \r |
42 | ///\r | |
43 | /// The maximum number of bytes the I2C host controller is able to send\r | |
44 | /// on the I2C bus.\r | |
45 | ///\r | |
2f88bd3a | 46 | UINT32 MaximumTransmitBytes;\r |
4006b0b5 EL |
47 | \r |
48 | ///\r | |
49 | /// The maximum number of bytes in the I2C bus transaction.\r | |
50 | ///\r | |
2f88bd3a | 51 | UINT32 MaximumTotalBytes;\r |
4006b0b5 EL |
52 | } EFI_I2C_CONTROLLER_CAPABILITIES;\r |
53 | \r | |
54 | ///\r | |
55 | /// I2C device description\r | |
56 | ///\r | |
57 | /// The EFI_I2C_ENUMERATE_PROTOCOL uses the EFI_I2C_DEVICE to describe\r | |
58 | /// the platform specific details associated with an I2C device. This\r | |
59 | /// description is passed to the I2C bus driver during enumeration where\r | |
60 | /// it is made available to the third party I2C device driver via the\r | |
61 | /// EFI_I2C_IO_PROTOCOL.\r | |
62 | ///\r | |
63 | typedef struct {\r | |
64 | ///\r | |
65 | /// Unique value assigned by the silicon manufacture or the third\r | |
66 | /// party I2C driver writer for the I2C part. This value logically\r | |
67 | /// combines both the manufacture name and the I2C part number into\r | |
68 | /// a single value specified as a GUID.\r | |
69 | ///\r | |
2f88bd3a | 70 | CONST EFI_GUID *DeviceGuid;\r |
4006b0b5 EL |
71 | \r |
72 | ///\r | |
73 | /// Unique ID of the I2C part within the system\r | |
74 | ///\r | |
2f88bd3a | 75 | UINT32 DeviceIndex;\r |
4006b0b5 EL |
76 | \r |
77 | ///\r | |
78 | /// Hardware revision - ACPI _HRV value. See the Advanced\r | |
79 | /// Configuration and Power Interface Specification, Revision 5.0\r | |
80 | /// for the field format and the Plug and play support for I2C\r | |
81 | /// web-page for restriction on values.\r | |
82 | ///\r | |
83 | /// http://www.acpi.info/spec.htm\r | |
84 | /// http://msdn.microsoft.com/en-us/library/windows/hardware/jj131711(v=vs.85).aspx\r | |
85 | ///\r | |
2f88bd3a | 86 | UINT32 HardwareRevision;\r |
4006b0b5 EL |
87 | \r |
88 | ///\r | |
89 | /// I2C bus configuration for the I2C device\r | |
90 | ///\r | |
2f88bd3a | 91 | UINT32 I2cBusConfiguration;\r |
4006b0b5 EL |
92 | \r |
93 | ///\r | |
94 | /// Number of slave addresses for the I2C device.\r | |
95 | ///\r | |
2f88bd3a | 96 | UINT32 SlaveAddressCount;\r |
4006b0b5 EL |
97 | \r |
98 | ///\r | |
99 | /// Pointer to the array of slave addresses for the I2C device.\r | |
100 | ///\r | |
2f88bd3a | 101 | CONST UINT32 *SlaveAddressArray;\r |
4006b0b5 EL |
102 | } EFI_I2C_DEVICE;\r |
103 | \r | |
104 | ///\r | |
105 | /// Define the I2C flags\r | |
106 | ///\r | |
107 | /// I2C read operation when set\r | |
2f88bd3a | 108 | #define I2C_FLAG_READ 0x00000001\r |
4006b0b5 EL |
109 | \r |
110 | ///\r | |
111 | /// Define the flags for SMBus operation\r | |
112 | ///\r | |
113 | /// The following flags are also present in only the first I2C operation\r | |
114 | /// and are ignored when present in other operations. These flags\r | |
115 | /// describe a particular SMB transaction as shown in the following table.\r | |
116 | ///\r | |
117 | \r | |
118 | /// SMBus operation\r | |
2f88bd3a | 119 | #define I2C_FLAG_SMBUS_OPERATION 0x00010000\r |
4006b0b5 EL |
120 | \r |
121 | /// SMBus block operation\r | |
122 | /// The flag I2C_FLAG_SMBUS_BLOCK causes the I2C master protocol to update\r | |
123 | /// the LengthInBytes field of the operation in the request packet with\r | |
124 | /// the actual number of bytes read or written. These values are only\r | |
125 | /// valid when the entire I2C transaction is successful.\r | |
126 | /// This flag also changes the LengthInBytes meaning to be: A maximum\r | |
127 | /// of LengthInBytes is to be read from the device. The first byte\r | |
128 | /// read contains the number of bytes remaining to be read, plus an\r | |
129 | /// optional PEC value.\r | |
2f88bd3a | 130 | #define I2C_FLAG_SMBUS_BLOCK 0x00020000\r |
4006b0b5 EL |
131 | \r |
132 | /// SMBus process call operation\r | |
2f88bd3a | 133 | #define I2C_FLAG_SMBUS_PROCESS_CALL 0x00040000\r |
4006b0b5 EL |
134 | \r |
135 | /// SMBus use packet error code (PEC)\r | |
136 | /// Note that the I2C master protocol may clear the I2C_FLAG_SMBUS_PEC bit\r | |
137 | /// to indicate that the PEC value was checked by the hardware and is\r | |
138 | /// not appended to the returned read data.\r | |
139 | ///\r | |
2f88bd3a | 140 | #define I2C_FLAG_SMBUS_PEC 0x00080000\r |
4006b0b5 | 141 | \r |
2f88bd3a | 142 | // ----------------------------------------------------------------------\r |
4006b0b5 EL |
143 | ///\r |
144 | /// QuickRead: OperationCount=1,\r | |
145 | /// LengthInBytes=0, Flags=I2C_FLAG_READ\r | |
146 | /// QuickWrite: OperationCount=1,\r | |
147 | /// LengthInBytes=0, Flags=0\r | |
148 | ///\r | |
149 | ///\r | |
150 | /// ReceiveByte: OperationCount=1,\r | |
151 | /// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
152 | /// | I2C_FLAG_READ\r | |
153 | /// ReceiveByte+PEC: OperationCount=1,\r | |
154 | /// LengthInBytes=2, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
155 | /// | I2C_FLAG_READ\r | |
156 | /// | I2C_FLAG_SMBUS_PEC\r | |
157 | ///\r | |
158 | ///\r | |
159 | /// SendByte: OperationCount=1,\r | |
160 | /// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
161 | /// SendByte+PEC: OperationCount=1,\r | |
162 | /// LengthInBytes=2, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
163 | /// | I2C_FLAG_SMBUS_PEC\r | |
164 | ///\r | |
165 | ///\r | |
166 | /// ReadDataByte: OperationCount=2,\r | |
167 | /// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
168 | /// LengthInBytes=1, Flags=I2C_FLAG_READ\r | |
169 | /// ReadDataByte+PEC: OperationCount=2,\r | |
170 | /// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
171 | /// | I2C_FLAG_SMBUS_PEC\r | |
172 | /// LengthInBytes=2, Flags=I2C_FLAG_READ\r | |
173 | ///\r | |
174 | ///\r | |
175 | /// WriteDataByte: OperationCount=1,\r | |
176 | /// LengthInBytes=2, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
177 | /// WriteDataByte+PEC: OperationCount=1,\r | |
178 | /// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
179 | /// | I2C_FLAG_SMBUS_PEC\r | |
180 | ///\r | |
181 | ///\r | |
182 | /// ReadDataWord: OperationCount=2,\r | |
183 | /// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
184 | /// LengthInBytes=2, Flags=I2C_FLAG_READ\r | |
185 | /// ReadDataWord+PEC: OperationCount=2,\r | |
186 | /// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
187 | /// | I2C_FLAG_SMBUS_PEC\r | |
188 | /// LengthInBytes=3, Flags=I2C_FLAG_READ\r | |
189 | ///\r | |
190 | ///\r | |
191 | /// WriteDataWord: OperationCount=1,\r | |
192 | /// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
193 | /// WriteDataWord+PEC: OperationCount=1,\r | |
194 | /// LengthInBytes=4, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
195 | /// | I2C_FLAG_SMBUS_PEC\r | |
196 | ///\r | |
197 | ///\r | |
198 | /// ReadBlock: OperationCount=2,\r | |
199 | /// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
200 | /// | I2C_FLAG_SMBUS_BLOCK\r | |
201 | /// LengthInBytes=33, Flags=I2C_FLAG_READ\r | |
202 | /// ReadBlock+PEC: OperationCount=2,\r | |
203 | /// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
204 | /// | I2C_FLAG_SMBUS_BLOCK\r | |
205 | /// | I2C_FLAG_SMBUS_PEC\r | |
206 | /// LengthInBytes=34, Flags=I2C_FLAG_READ\r | |
207 | ///\r | |
208 | ///\r | |
209 | /// WriteBlock: OperationCount=1,\r | |
210 | /// LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
211 | /// | I2C_FLAG_SMBUS_BLOCK\r | |
212 | /// WriteBlock+PEC: OperationCount=1,\r | |
213 | /// LengthInBytes=N+3, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
214 | /// | I2C_FLAG_SMBUS_BLOCK\r | |
215 | /// | I2C_FLAG_SMBUS_PEC\r | |
216 | ///\r | |
217 | ///\r | |
218 | /// ProcessCall: OperationCount=2,\r | |
219 | /// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
220 | /// | I2C_FLAG_SMBUS_PROCESS_CALL\r | |
221 | /// LengthInBytes=2, Flags=I2C_FLAG_READ\r | |
222 | /// ProcessCall+PEC: OperationCount=2,\r | |
223 | /// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
224 | /// | I2C_FLAG_SMBUS_PROCESS_CALL\r | |
225 | /// | I2C_FLAG_SMBUS_PEC\r | |
226 | /// LengthInBytes=3, Flags=I2C_FLAG_READ\r | |
227 | ///\r | |
228 | ///\r | |
229 | /// BlkProcessCall: OperationCount=2,\r | |
230 | /// LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
231 | /// | I2C_FLAG_SMBUS_PROCESS_CALL\r | |
232 | /// | I2C_FLAG_SMBUS_BLOCK\r | |
233 | /// LengthInBytes=33, Flags=I2C_FLAG_READ\r | |
234 | /// BlkProcessCall+PEC: OperationCount=2,\r | |
235 | /// LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION\r | |
236 | /// | I2C_FLAG_SMBUS_PROCESS_CALL\r | |
237 | /// | I2C_FLAG_SMBUS_BLOCK\r | |
238 | /// | I2C_FLAG_SMBUS_PEC\r | |
239 | /// LengthInBytes=34, Flags=I2C_FLAG_READ\r | |
240 | ///\r | |
2f88bd3a | 241 | // ----------------------------------------------------------------------\r |
4006b0b5 EL |
242 | \r |
243 | ///\r | |
244 | /// I2C device operation\r | |
245 | ///\r | |
246 | /// The EFI_I2C_OPERATION describes a subset of an I2C transaction in which\r | |
247 | /// the I2C controller is either sending or receiving bytes from the bus.\r | |
248 | /// Some transactions will consist of a single operation while others will\r | |
249 | /// be two or more.\r | |
250 | ///\r | |
251 | /// Note: Some I2C controllers do not support read or write ping (address\r | |
252 | /// only) operation and will return EFI_UNSUPPORTED status when these\r | |
253 | /// operations are requested.\r | |
254 | ///\r | |
255 | /// Note: I2C controllers which do not support complex transactions requiring\r | |
256 | /// multiple repeated start bits return EFI_UNSUPPORTED without processing\r | |
257 | /// any of the transaction.\r | |
258 | ///\r | |
259 | typedef struct {\r | |
260 | ///\r | |
261 | /// Flags to qualify the I2C operation.\r | |
262 | ///\r | |
2f88bd3a | 263 | UINT32 Flags;\r |
4006b0b5 EL |
264 | \r |
265 | ///\r | |
266 | /// Number of bytes to send to or receive from the I2C device. A ping\r | |
267 | /// (address only byte/bytes) is indicated by setting the LengthInBytes\r | |
268 | /// to zero.\r | |
269 | ///\r | |
2f88bd3a | 270 | UINT32 LengthInBytes;\r |
4006b0b5 EL |
271 | \r |
272 | ///\r | |
273 | /// Pointer to a buffer containing the data to send or to receive from\r | |
274 | /// the I2C device. The Buffer must be at least LengthInBytes in size.\r | |
275 | ///\r | |
2f88bd3a | 276 | UINT8 *Buffer;\r |
4006b0b5 EL |
277 | } EFI_I2C_OPERATION;\r |
278 | \r | |
279 | ///\r | |
280 | /// I2C device request\r | |
281 | ///\r | |
282 | /// The EFI_I2C_REQUEST_PACKET describes a single I2C transaction. The\r | |
283 | /// transaction starts with a start bit followed by the first operation\r | |
284 | /// in the operation array. Subsequent operations are separated with\r | |
285 | /// repeated start bits and the last operation is followed by a stop bit\r | |
286 | /// which concludes the transaction. Each operation is described by one\r | |
287 | /// of the elements in the Operation array.\r | |
288 | ///\r | |
289 | typedef struct {\r | |
290 | ///\r | |
291 | /// Number of elements in the operation array\r | |
292 | ///\r | |
2f88bd3a | 293 | UINTN OperationCount;\r |
4006b0b5 EL |
294 | \r |
295 | ///\r | |
296 | /// Description of the I2C operation\r | |
297 | ///\r | |
2f88bd3a | 298 | EFI_I2C_OPERATION Operation[1];\r |
4006b0b5 EL |
299 | } EFI_I2C_REQUEST_PACKET;\r |
300 | \r | |
2f88bd3a | 301 | #endif // __PI_I2C_H__\r |