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1 | /** @file\r |
2 | EFI MM Access PPI definition.\r | |
3 | \r | |
4 | This PPI is used to control the visibility of the MMRAM on the platform.\r | |
5 | The EFI_PEI_MM_ACCESS_PPI abstracts the location and characteristics of MMRAM. The\r | |
6 | principal functionality found in the memory controller includes the following:\r | |
7 | - Exposing the MMRAM to all non-MM agents, or the "open" state\r | |
8 | - Shrouding the MMRAM to all but the MM agents, or the "closed" state\r | |
9 | - Preserving the system integrity, or "locking" the MMRAM, such that the settings cannot be\r | |
10 | perturbed by either boot service or runtime agents\r | |
11 | \r | |
12 | Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>\r | |
13 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
14 | \r | |
15 | @par Revision Reference:\r | |
16 | This PPI is introduced in PI Version 1.5.\r | |
17 | \r | |
18 | **/\r | |
19 | \r | |
20 | #ifndef _MM_ACCESS_PPI_H_\r | |
21 | #define _MM_ACCESS_PPI_H_\r | |
22 | \r | |
23 | #define EFI_PEI_MM_ACCESS_PPI_GUID \\r | |
24 | { 0x268f33a9, 0xcccd, 0x48be, { 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 }}\r | |
25 | \r | |
26 | typedef struct _EFI_PEI_MM_ACCESS_PPI EFI_PEI_MM_ACCESS_PPI;\r | |
27 | \r | |
28 | /**\r | |
29 | Opens the MMRAM area to be accessible by a PEIM.\r | |
30 | \r | |
31 | This function "opens" MMRAM so that it is visible while not inside of MM. The function should\r | |
32 | return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM. The function\r | |
33 | should return EFI_DEVICE_ERROR if the MMRAM configuration is locked.\r | |
34 | \r | |
35 | @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.\r | |
36 | @param This The EFI_PEI_MM_ACCESS_PPI instance.\r | |
37 | @param DescriptorIndex The region of MMRAM to Open.\r | |
38 | \r | |
39 | @retval EFI_SUCCESS The operation was successful.\r | |
40 | @retval EFI_UNSUPPORTED The system does not support opening and closing of MMRAM.\r | |
41 | @retval EFI_DEVICE_ERROR MMRAM cannot be opened, perhaps because it is locked.\r | |
42 | \r | |
43 | **/\r | |
44 | typedef\r | |
45 | EFI_STATUS\r | |
46 | (EFIAPI *EFI_PEI_MM_OPEN)(\r | |
47 | IN EFI_PEI_SERVICES **PeiServices,\r | |
48 | IN EFI_PEI_MM_ACCESS_PPI *This,\r | |
49 | IN UINTN DescriptorIndex\r | |
50 | );\r | |
51 | \r | |
52 | /**\r | |
53 | Inhibits access to the MMRAM.\r | |
54 | \r | |
55 | This function "closes" MMRAM so that it is not visible while outside of MM. The function should\r | |
56 | return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM.\r | |
57 | \r | |
58 | @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.\r | |
59 | @param This The EFI_PEI_MM_ACCESS_PPI instance.\r | |
60 | @param DescriptorIndex The region of MMRAM to Close.\r | |
61 | \r | |
62 | @retval EFI_SUCCESS The operation was successful.\r | |
63 | @retval EFI_UNSUPPORTED The system does not support opening and closing of MMRAM.\r | |
64 | @retval EFI_DEVICE_ERROR MMRAM cannot be closed.\r | |
65 | \r | |
66 | **/\r | |
67 | typedef\r | |
68 | EFI_STATUS\r | |
69 | (EFIAPI *EFI_PEI_MM_CLOSE)(\r | |
70 | IN EFI_PEI_SERVICES **PeiServices,\r | |
71 | IN EFI_PEI_MM_ACCESS_PPI *This,\r | |
72 | IN UINTN DescriptorIndex\r | |
73 | );\r | |
74 | \r | |
75 | /**\r | |
76 | This function prohibits access to the MMRAM region. This function is usually implemented such\r | |
77 | that it is a write-once operation.\r | |
78 | \r | |
79 | @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.\r | |
80 | @param This The EFI_PEI_MM_ACCESS_PPI instance.\r | |
81 | @param DescriptorIndex The region of MMRAM to Lock.\r | |
82 | \r | |
83 | @retval EFI_SUCCESS The operation was successful.\r | |
84 | @retval EFI_UNSUPPORTED The system does not support opening and closing of MMRAM.\r | |
85 | \r | |
86 | **/\r | |
87 | typedef\r | |
88 | EFI_STATUS\r | |
89 | (EFIAPI *EFI_PEI_MM_LOCK)(\r | |
90 | IN EFI_PEI_SERVICES **PeiServices,\r | |
91 | IN EFI_PEI_MM_ACCESS_PPI *This,\r | |
92 | IN UINTN DescriptorIndex\r | |
93 | );\r | |
94 | \r | |
95 | /**\r | |
96 | Queries the memory controller for the possible regions that will support MMRAM.\r | |
97 | \r | |
98 | This function describes the MMRAM regions.\r | |
99 | This data structure forms the contract between the MM_ACCESS and MM_IPL drivers. There is an\r | |
100 | ambiguity when any MMRAM region is remapped. For example, on some chipsets, some MMRAM\r | |
101 | regions can be initialized at one physical address but is later accessed at another processor address.\r | |
102 | There is currently no way for the MM IPL driver to know that it must use two different addresses\r | |
103 | depending on what it is trying to do. As a result, initial configuration and loading can use the\r | |
104 | physical address PhysicalStart while MMRAM is open. However, once the region has been\r | |
105 | closed and needs to be accessed by agents in MM, the CpuStart address must be used.\r | |
106 | This PPI publishes the available memory that the chipset can shroud for the use of installing code.\r | |
107 | These regions serve the dual purpose of describing which regions have been open, closed, or locked.\r | |
108 | In addition, these regions may include overlapping memory ranges, depending on the chipset\r | |
109 | implementation. The latter might include a chipset that supports T-SEG, where memory near the top\r | |
110 | of the physical DRAM can be allocated for MMRAM too.\r | |
111 | The key thing to note is that the regions that are described by the PPI are a subset of the capabilities\r | |
112 | of the hardware.\r | |
113 | \r | |
114 | @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.\r | |
115 | @param This The EFI_PEI_MM_ACCESS_PPI instance.\r | |
116 | @param MmramMapSize A pointer to the size, in bytes, of the MmramMemoryMap buffer. On input, this value is\r | |
117 | the size of the buffer that is allocated by the caller. On output, it is the size of the\r | |
118 | buffer that was returned by the firmware if the buffer was large enough, or, if the\r | |
119 | buffer was too small, the size of the buffer that is needed to contain the map.\r | |
120 | @param MmramMap A pointer to the buffer in which firmware places the current memory map. The map is\r | |
121 | an array of EFI_MMRAM_DESCRIPTORs\r | |
122 | \r | |
123 | @retval EFI_SUCCESS The chipset supported the given resource.\r | |
124 | @retval EFI_BUFFER_TOO_SMALL The MmramMap parameter was too small. The current\r | |
125 | buffer size needed to hold the memory map is returned in\r | |
126 | MmramMapSize.\r | |
127 | \r | |
128 | **/\r | |
129 | typedef\r | |
130 | EFI_STATUS\r | |
131 | (EFIAPI *EFI_PEI_MM_CAPABILITIES)(\r | |
132 | IN EFI_PEI_SERVICES **PeiServices,\r | |
133 | IN EFI_PEI_MM_ACCESS_PPI *This,\r | |
134 | IN OUT UINTN *MmramMapSize,\r | |
135 | IN OUT EFI_MMRAM_DESCRIPTOR *MmramMap\r | |
136 | );\r | |
137 | \r | |
138 | ///\r | |
139 | /// EFI MM Access PPI is used to control the visibility of the MMRAM on the platform.\r | |
140 | /// It abstracts the location and characteristics of MMRAM. The platform should report\r | |
141 | /// all MMRAM via EFI_PEI_MM_ACCESS_PPI. The expectation is that the north bridge or\r | |
142 | /// memory controller would publish this PPI.\r | |
143 | ///\r | |
144 | struct _EFI_PEI_MM_ACCESS_PPI {\r | |
145 | EFI_PEI_MM_OPEN Open;\r | |
146 | EFI_PEI_MM_CLOSE Close;\r | |
147 | EFI_PEI_MM_LOCK Lock;\r | |
148 | EFI_PEI_MM_CAPABILITIES GetCapabilities;\r | |
149 | BOOLEAN LockState;\r | |
150 | BOOLEAN OpenState;\r | |
151 | };\r | |
152 | \r | |
153 | extern EFI_GUID gEfiPeiMmAccessPpiGuid;\r | |
154 | \r | |
155 | #endif\r |