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5879b875 | 1 | /** @file\r |
d7132512 | 2 | This file declares PciCfg2 PPI.\r |
5879b875 | 3 | \r |
d7132512 LG |
4 | This ppi Provides platform or chipset-specific access to \r |
5 | the PCI configuration space for a specific PCI segment.\r | |
6 | \r | |
7 | Copyright (c) 2006 - 2008, Intel Corporation\r | |
845effb3 | 8 | All rights reserved. This program and the accompanying materials\r |
9 | are licensed and made available under the terms and conditions of the BSD License\r | |
10 | which accompanies this distribution. The full text of the license may be found at\r | |
11 | http://opensource.org/licenses/bsd-license.php\r | |
5879b875 | 12 | \r |
845effb3 | 13 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
14 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
5879b875 | 15 | \r |
5879b875 | 16 | @par Revision Reference:\r |
17 | This PPI is defined in PI\r | |
18 | Version 1.00.\r | |
19 | \r | |
20 | **/\r | |
21 | \r | |
22 | #ifndef __PEI_PCI_CFG2_H__\r | |
23 | #define __PEI_PCI_CFG2_H__\r | |
24 | \r | |
0c7f62f8 | 25 | #include <ProcessorBind.h>\r |
26 | #include <Pi/PiPeiCis.h>\r | |
5879b875 | 27 | \r |
28 | #define EFI_PEI_PCI_CFG2_PPI_GUID \\r | |
29 | { 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } }\r | |
30 | \r | |
31 | \r | |
32 | typedef struct _EFI_PEI_PCI_CFG2_PPI EFI_PEI_PCI_CFG2_PPI;\r | |
33 | \r | |
34 | #define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \\r | |
35 | (((bus) << 24) | \\r | |
36 | ((dev) << 16) | \\r | |
37 | ((func) << 8) | \\r | |
8b13229b | 38 | ((reg) < 256 ? (reg) : ((UINT64)(reg) << 32)));\r |
5879b875 | 39 | \r |
06889842 | 40 | ///\r |
41 | /// EFI_PEI_PCI_CFG_PPI_WIDTH\r | |
42 | ///\r | |
5879b875 | 43 | typedef enum {\r |
44 | EfiPeiPciCfgWidthUint8 = 0,\r | |
45 | EfiPeiPciCfgWidthUint16 = 1,\r | |
46 | EfiPeiPciCfgWidthUint32 = 2,\r | |
47 | EfiPeiPciCfgWidthUint64 = 3,\r | |
48 | EfiPeiPciCfgWidthMaximum\r | |
49 | } EFI_PEI_PCI_CFG_PPI_WIDTH;\r | |
50 | \r | |
06889842 | 51 | ///\r |
52 | /// EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS\r | |
53 | ///\r | |
5879b875 | 54 | typedef struct {\r |
55 | UINT8 Register;\r | |
56 | UINT8 Function;\r | |
57 | UINT8 Device;\r | |
58 | UINT8 Bus;\r | |
59 | UINT32 ExtendedRegister;\r | |
60 | } EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS;\r | |
61 | \r | |
62 | /**\r | |
63 | Reads from or write to a given location in the PCI configuration space.\r | |
64 | \r | |
65 | @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.\r | |
66 | \r | |
67 | @param This Pointer to local data for the interface.\r | |
68 | \r | |
845effb3 | 69 | @param Width The width of the access. Enumerated in bytes.\r |
5879b875 | 70 | See EFI_PEI_PCI_CFG_PPI_WIDTH above.\r |
71 | \r | |
845effb3 | 72 | @param Address The physical address of the access. The format of\r |
5879b875 | 73 | the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.\r |
74 | \r | |
75 | @param Buffer A pointer to the buffer of data..\r | |
76 | \r | |
77 | \r | |
78 | @retval EFI_SUCCESS The function completed successfully.\r | |
79 | \r | |
80 | @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r | |
81 | \r | |
82 | @retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this\r | |
83 | time.\r | |
84 | \r | |
85 | **/\r | |
86 | typedef\r | |
87 | EFI_STATUS\r | |
8b13229b | 88 | (EFIAPI *EFI_PEI_PCI_CFG2_PPI_IO)(\r |
00edb218 A |
89 | IN CONST EFI_PEI_SERVICES **PeiServices,\r |
90 | IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r | |
ef4fa1a4 | 91 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r |
92 | IN UINT64 Address,\r | |
5879b875 | 93 | IN OUT VOID *Buffer\r |
94 | );\r | |
95 | \r | |
96 | \r | |
97 | /**\r | |
d7132512 LG |
98 | Performs a read-modify-write operation on the contents \r |
99 | from a given location in the PCI configuration space.\r | |
5879b875 | 100 | \r |
845effb3 | 101 | @param PeiServices An indirect pointer to the PEI Services Table\r |
5879b875 | 102 | published by the PEI Foundation.\r |
103 | \r | |
104 | @param This Pointer to local data for the interface.\r | |
105 | \r | |
106 | @param Width The width of the access. Enumerated in bytes. Type\r | |
107 | EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().\r | |
108 | \r | |
109 | @param Address The physical address of the access.\r | |
110 | \r | |
845effb3 | 111 | @param SetBits Points to value to bitwise-OR with the read configuration value.\r |
5879b875 | 112 | \r |
113 | The size of the value is determined by Width.\r | |
114 | \r | |
845effb3 | 115 | @param ClearBits Points to the value to negate and bitwise-AND with the read configuration value.\r |
5879b875 | 116 | The size of the value is determined by Width.\r |
117 | \r | |
118 | \r | |
119 | @retval EFI_SUCCESS The function completed successfully.\r | |
120 | \r | |
121 | @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r | |
122 | \r | |
845effb3 | 123 | @retval EFI_DEVICE_NOT_READY The device is not capable of supporting\r |
5879b875 | 124 | the operation at this time.\r |
125 | \r | |
126 | **/\r | |
127 | typedef\r | |
128 | EFI_STATUS\r | |
8b13229b | 129 | (EFIAPI *EFI_PEI_PCI_CFG2_PPI_RW)(\r |
5879b875 | 130 | IN CONST EFI_PEI_SERVICES **PeiServices,\r |
131 | IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r | |
ef4fa1a4 | 132 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r |
133 | IN UINT64 Address,\r | |
5879b875 | 134 | IN CONST VOID *SetBits,\r |
135 | IN CONST VOID *ClearBits\r | |
136 | );\r | |
137 | \r | |
138 | /**\r | |
139 | @par Ppi Description:\r | |
845effb3 | 140 | The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI\r |
5879b875 | 141 | controllers behind a PCI root bridge controller.\r |
142 | \r | |
143 | @param Read PCI read services. See the Read() function description.\r | |
144 | \r | |
145 | @param Write PCI write services. See the Write() function description.\r | |
146 | \r | |
147 | @param Modify PCI read-modify-write services. See the Modify() function description.\r | |
148 | \r | |
149 | @param Segment The PCI bus segment which the specified functions will access.\r | |
150 | \r | |
151 | **/\r | |
152 | struct _EFI_PEI_PCI_CFG2_PPI {\r | |
845effb3 | 153 | EFI_PEI_PCI_CFG2_PPI_IO Read;\r |
154 | EFI_PEI_PCI_CFG2_PPI_IO Write;\r | |
155 | EFI_PEI_PCI_CFG2_PPI_RW Modify;\r | |
5879b875 | 156 | UINT16 Segment;\r |
157 | };\r | |
158 | \r | |
159 | \r | |
160 | extern EFI_GUID gEfiPciCfg2PpiGuid;\r | |
161 | \r | |
162 | #endif\r |