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d1f95000 1/** @file\r
2 DebugSupport protocol and supporting definitions as defined in the UEFI2.0\r
3 specification.\r
4\r
5 The DebugSupport protocol is used by source level debuggers to abstract the\r
6 processor and handle context save and restore operations.\r
7\r
8 Copyright (c) 2006, Intel Corporation \r
9 All rights reserved. This program and the accompanying materials \r
10 are licensed and made available under the terms and conditions of the BSD License \r
11 which accompanies this distribution. The full text of the license may be found at \r
12 http://opensource.org/licenses/bsd-license.php \r
13\r
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
16\r
d1f95000 17**/\r
18\r
19#ifndef __DEBUG_SUPPORT_H__\r
20#define __DEBUG_SUPPORT_H__\r
21\r
3f748e52 22#include <ProcessorBind.h>\r
d1f95000 23#include <IndustryStandard/PeImage.h>\r
24\r
25typedef struct _EFI_DEBUG_SUPPORT_PROTOCOL EFI_DEBUG_SUPPORT_PROTOCOL;\r
26\r
27//\r
28// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}\r
29//\r
30#define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \\r
31 { \\r
32 0x2755590C, 0x6F3C, 0x42FA, {0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25 } \\r
33 }\r
34\r
35//\r
36// Debug Support definitions\r
37//\r
38typedef INTN EFI_EXCEPTION_TYPE;\r
39\r
40//\r
41// IA-32 processor exception types\r
42//\r
43#define EXCEPT_IA32_DIVIDE_ERROR 0\r
44#define EXCEPT_IA32_DEBUG 1\r
45#define EXCEPT_IA32_NMI 2\r
46#define EXCEPT_IA32_BREAKPOINT 3\r
47#define EXCEPT_IA32_OVERFLOW 4\r
48#define EXCEPT_IA32_BOUND 5\r
49#define EXCEPT_IA32_INVALID_OPCODE 6\r
50#define EXCEPT_IA32_DOUBLE_FAULT 8\r
51#define EXCEPT_IA32_INVALID_TSS 10\r
52#define EXCEPT_IA32_SEG_NOT_PRESENT 11\r
53#define EXCEPT_IA32_STACK_FAULT 12\r
54#define EXCEPT_IA32_GP_FAULT 13\r
55#define EXCEPT_IA32_PAGE_FAULT 14\r
56#define EXCEPT_IA32_FP_ERROR 16\r
57#define EXCEPT_IA32_ALIGNMENT_CHECK 17\r
58#define EXCEPT_IA32_MACHINE_CHECK 18\r
59#define EXCEPT_IA32_SIMD 19\r
60\r
61//\r
62// IA-32 processor context definition\r
63//\r
64//\r
65// FXSAVE_STATE\r
66// FP / MMX / XMM registers (see fxrstor instruction definition)\r
67//\r
68typedef struct {\r
69 UINT16 Fcw;\r
70 UINT16 Fsw;\r
71 UINT16 Ftw;\r
72 UINT16 Opcode;\r
73 UINT32 Eip;\r
74 UINT16 Cs;\r
75 UINT16 Reserved1;\r
76 UINT32 DataOffset;\r
77 UINT16 Ds;\r
78 UINT8 Reserved2[10];\r
79#if (EFI_SPECIFICATION_VERSION >= 0x00020000)\r
80 UINT8 St0Mm0[10], Reserved3[6];\r
81 UINT8 St1Mm1[10], Reserved4[6];\r
82 UINT8 St2Mm2[10], Reserved5[6];\r
83 UINT8 St3Mm3[10], Reserved6[6];\r
84 UINT8 St4Mm4[10], Reserved7[6];\r
85 UINT8 St5Mm5[10], Reserved8[6];\r
86 UINT8 St6Mm6[10], Reserved9[6];\r
87 UINT8 St7Mm7[10], Reserved10[6];\r
88 UINT8 Xmm0[16];\r
89 UINT8 Xmm1[16];\r
90 UINT8 Xmm2[16];\r
91 UINT8 Xmm3[16];\r
92 UINT8 Xmm4[16];\r
93 UINT8 Xmm5[16];\r
94 UINT8 Xmm6[16];\r
95 UINT8 Xmm7[16];\r
96 UINT8 Reserved11[14 * 16];\r
97} EFI_FX_SAVE_STATE_IA32;\r
98#else\r
99 UINT8 St0Mm0[10], Reserved3[6];\r
100 UINT8 St0Mm1[10], Reserved4[6];\r
101 UINT8 St0Mm2[10], Reserved5[6];\r
102 UINT8 St0Mm3[10], Reserved6[6];\r
103 UINT8 St0Mm4[10], Reserved7[6];\r
104 UINT8 St0Mm5[10], Reserved8[6];\r
105 UINT8 St0Mm6[10], Reserved9[6];\r
106 UINT8 St0Mm7[10], Reserved10[6];\r
107 UINT8 Reserved11[22 * 16];\r
108} EFI_FX_SAVE_STATE;\r
109#endif\r
110\r
111typedef struct {\r
112 UINT32 ExceptionData;\r
113#if (EFI_SPECIFICATION_VERSION >= 0x00020000)\r
114 EFI_FX_SAVE_STATE_IA32 FxSaveState;\r
115#else\r
116 EFI_FX_SAVE_STATE FxSaveState;\r
117#endif\r
118 UINT32 Dr0;\r
119 UINT32 Dr1;\r
120 UINT32 Dr2;\r
121 UINT32 Dr3;\r
122 UINT32 Dr6;\r
123 UINT32 Dr7;\r
124 UINT32 Cr0;\r
125 UINT32 Cr1; /* Reserved */\r
126 UINT32 Cr2;\r
127 UINT32 Cr3;\r
128 UINT32 Cr4;\r
129 UINT32 Eflags;\r
130 UINT32 Ldtr;\r
131 UINT32 Tr;\r
132 UINT32 Gdtr[2];\r
133 UINT32 Idtr[2];\r
134 UINT32 Eip;\r
135 UINT32 Gs;\r
136 UINT32 Fs;\r
137 UINT32 Es;\r
138 UINT32 Ds;\r
139 UINT32 Cs;\r
140 UINT32 Ss;\r
141 UINT32 Edi;\r
142 UINT32 Esi;\r
143 UINT32 Ebp;\r
144 UINT32 Esp;\r
145 UINT32 Ebx;\r
146 UINT32 Edx;\r
147 UINT32 Ecx;\r
148 UINT32 Eax;\r
149} EFI_SYSTEM_CONTEXT_IA32;\r
150\r
151//\r
152// X64 processor exception types\r
153//\r
154#define EXCEPT_X64_DIVIDE_ERROR 0\r
155#define EXCEPT_X64_DEBUG 1\r
156#define EXCEPT_X64_NMI 2\r
157#define EXCEPT_X64_BREAKPOINT 3\r
158#define EXCEPT_X64_OVERFLOW 4\r
159#define EXCEPT_X64_BOUND 5\r
160#define EXCEPT_X64_INVALID_OPCODE 6\r
161#define EXCEPT_X64_DOUBLE_FAULT 8\r
162#define EXCEPT_X64_INVALID_TSS 10\r
163#define EXCEPT_X64_SEG_NOT_PRESENT 11\r
164#define EXCEPT_X64_STACK_FAULT 12\r
165#define EXCEPT_X64_GP_FAULT 13\r
166#define EXCEPT_X64_PAGE_FAULT 14\r
167#define EXCEPT_X64_FP_ERROR 16\r
168#define EXCEPT_X64_ALIGNMENT_CHECK 17\r
169#define EXCEPT_X64_MACHINE_CHECK 18\r
170#define EXCEPT_X64_SIMD 19\r
171\r
172//\r
173// X64 processor context definition\r
174//\r
175// FXSAVE_STATE\r
176// FP / MMX / XMM registers (see fxrstor instruction definition)\r
177//\r
178typedef struct {\r
179 UINT16 Fcw;\r
180 UINT16 Fsw;\r
181 UINT16 Ftw;\r
182 UINT16 Opcode;\r
183 UINT64 Rip;\r
184 UINT64 DataOffset;\r
185 UINT8 Reserved1[8];\r
186 UINT8 St0Mm0[10], Reserved2[6];\r
187 UINT8 St1Mm1[10], Reserved3[6];\r
188 UINT8 St2Mm2[10], Reserved4[6];\r
189 UINT8 St3Mm3[10], Reserved5[6];\r
190 UINT8 St4Mm4[10], Reserved6[6];\r
191 UINT8 St5Mm5[10], Reserved7[6];\r
192 UINT8 St6Mm6[10], Reserved8[6];\r
193 UINT8 St7Mm7[10], Reserved9[6];\r
194 UINT8 Xmm0[16];\r
195 UINT8 Xmm1[16];\r
196 UINT8 Xmm2[16];\r
197 UINT8 Xmm3[16];\r
198 UINT8 Xmm4[16];\r
199 UINT8 Xmm5[16];\r
200 UINT8 Xmm6[16];\r
201 UINT8 Xmm7[16];\r
202#if (EFI_SPECIFICATION_VERSION >= 0x00020000)\r
203 //\r
204 // NOTE: UEFI 2.0 spec definition as follows. It should be updated \r
205 // after spec update.\r
206 //\r
207 UINT8 Reserved11[14 * 16];\r
208#else\r
209 UINT8 Xmm8[16];\r
210 UINT8 Xmm9[16];\r
211 UINT8 Xmm10[16];\r
212 UINT8 Xmm11[16];\r
213 UINT8 Xmm12[16];\r
214 UINT8 Xmm13[16];\r
215 UINT8 Xmm14[16];\r
216 UINT8 Xmm15[16];\r
217 UINT8 Reserved10[6 * 16];\r
218#endif\r
219} EFI_FX_SAVE_STATE_X64;\r
220\r
221typedef struct {\r
222 UINT64 ExceptionData;\r
223 EFI_FX_SAVE_STATE_X64 FxSaveState;\r
224 UINT64 Dr0;\r
225 UINT64 Dr1;\r
226 UINT64 Dr2;\r
227 UINT64 Dr3;\r
228 UINT64 Dr6;\r
229 UINT64 Dr7;\r
230 UINT64 Cr0;\r
231 UINT64 Cr1; /* Reserved */\r
232 UINT64 Cr2;\r
233 UINT64 Cr3;\r
234 UINT64 Cr4;\r
235 UINT64 Cr8;\r
236 UINT64 Rflags;\r
237 UINT64 Ldtr;\r
238 UINT64 Tr;\r
239 UINT64 Gdtr[2];\r
240 UINT64 Idtr[2];\r
241 UINT64 Rip;\r
242 UINT64 Gs;\r
243 UINT64 Fs;\r
244 UINT64 Es;\r
245 UINT64 Ds;\r
246 UINT64 Cs;\r
247 UINT64 Ss;\r
248 UINT64 Rdi;\r
249 UINT64 Rsi;\r
250 UINT64 Rbp;\r
251 UINT64 Rsp;\r
252 UINT64 Rbx;\r
253 UINT64 Rdx;\r
254 UINT64 Rcx;\r
255 UINT64 Rax;\r
256 UINT64 R8;\r
257 UINT64 R9;\r
258 UINT64 R10;\r
259 UINT64 R11;\r
260 UINT64 R12;\r
261 UINT64 R13;\r
262 UINT64 R14;\r
263 UINT64 R15;\r
264} EFI_SYSTEM_CONTEXT_X64;\r
265\r
266//\r
267// IPF processor exception types\r
268//\r
269#define EXCEPT_IPF_VHTP_TRANSLATION 0\r
270#define EXCEPT_IPF_INSTRUCTION_TLB 1\r
271#define EXCEPT_IPF_DATA_TLB 2\r
272#define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3\r
273#define EXCEPT_IPF_ALT_DATA_TLB 4\r
274#define EXCEPT_IPF_DATA_NESTED_TLB 5\r
275#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6\r
276#define EXCEPT_IPF_DATA_KEY_MISSED 7\r
277#define EXCEPT_IPF_DIRTY_BIT 8\r
278#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9\r
279#define EXCEPT_IPF_DATA_ACCESS_BIT 10\r
280#define EXCEPT_IPF_BREAKPOINT 11\r
281#define EXCEPT_IPF_EXTERNAL_INTERRUPT 12\r
282//\r
283// 13 - 19 reserved\r
284//\r
285#define EXCEPT_IPF_PAGE_NOT_PRESENT 20\r
286#define EXCEPT_IPF_KEY_PERMISSION 21\r
287#define EXCEPT_IPF_INSTRUCTION_ACCESS_RIGHTS 22\r
288#define EXCEPT_IPF_DATA_ACCESS_RIGHTS 23\r
289#define EXCEPT_IPF_GENERAL_EXCEPTION 24\r
290#define EXCEPT_IPF_DISABLED_FP_REGISTER 25\r
291#define EXCEPT_IPF_NAT_CONSUMPTION 26\r
292#define EXCEPT_IPF_SPECULATION 27\r
293//\r
294// 28 reserved\r
295//\r
296#define EXCEPT_IPF_DEBUG 29\r
297#define EXCEPT_IPF_UNALIGNED_REFERENCE 30\r
298#define EXCEPT_IPF_UNSUPPORTED_DATA_REFERENCE 31\r
299#define EXCEPT_IPF_FP_FAULT 32\r
300#define EXCEPT_IPF_FP_TRAP 33\r
301#define EXCEPT_IPF_LOWER_PRIVILEGE_TRANSFER_TRAP 34\r
302#define EXCEPT_IPF_TAKEN_BRANCH 35\r
303#define EXCEPT_IPF_SINGLE_STEP 36\r
304//\r
305// 37 - 44 reserved\r
306//\r
307#define EXCEPT_IPF_IA32_EXCEPTION 45\r
308#define EXCEPT_IPF_IA32_INTERCEPT 46\r
309#define EXCEPT_IPF_IA32_INTERRUPT 47\r
310\r
311//\r
312// IPF processor context definition\r
313//\r
314typedef struct {\r
315 //\r
316 // The first reserved field is necessary to preserve alignment for the correct\r
317 // bits in UNAT and to insure F2 is 16 byte aligned..\r
318 //\r
319 UINT64 Reserved;\r
320 UINT64 R1;\r
321 UINT64 R2;\r
322 UINT64 R3;\r
323 UINT64 R4;\r
324 UINT64 R5;\r
325 UINT64 R6;\r
326 UINT64 R7;\r
327 UINT64 R8;\r
328 UINT64 R9;\r
329 UINT64 R10;\r
330 UINT64 R11;\r
331 UINT64 R12;\r
332 UINT64 R13;\r
333 UINT64 R14;\r
334 UINT64 R15;\r
335 UINT64 R16;\r
336 UINT64 R17;\r
337 UINT64 R18;\r
338 UINT64 R19;\r
339 UINT64 R20;\r
340 UINT64 R21;\r
341 UINT64 R22;\r
342 UINT64 R23;\r
343 UINT64 R24;\r
344 UINT64 R25;\r
345 UINT64 R26;\r
346 UINT64 R27;\r
347 UINT64 R28;\r
348 UINT64 R29;\r
349 UINT64 R30;\r
350 UINT64 R31;\r
351\r
352 UINT64 F2[2];\r
353 UINT64 F3[2];\r
354 UINT64 F4[2];\r
355 UINT64 F5[2];\r
356 UINT64 F6[2];\r
357 UINT64 F7[2];\r
358 UINT64 F8[2];\r
359 UINT64 F9[2];\r
360 UINT64 F10[2];\r
361 UINT64 F11[2];\r
362 UINT64 F12[2];\r
363 UINT64 F13[2];\r
364 UINT64 F14[2];\r
365 UINT64 F15[2];\r
366 UINT64 F16[2];\r
367 UINT64 F17[2];\r
368 UINT64 F18[2];\r
369 UINT64 F19[2];\r
370 UINT64 F20[2];\r
371 UINT64 F21[2];\r
372 UINT64 F22[2];\r
373 UINT64 F23[2];\r
374 UINT64 F24[2];\r
375 UINT64 F25[2];\r
376 UINT64 F26[2];\r
377 UINT64 F27[2];\r
378 UINT64 F28[2];\r
379 UINT64 F29[2];\r
380 UINT64 F30[2];\r
381 UINT64 F31[2];\r
382\r
383 UINT64 Pr;\r
384\r
385 UINT64 B0;\r
386 UINT64 B1;\r
387 UINT64 B2;\r
388 UINT64 B3;\r
389 UINT64 B4;\r
390 UINT64 B5;\r
391 UINT64 B6;\r
392 UINT64 B7;\r
393\r
394 //\r
395 // application registers\r
396 //\r
397 UINT64 ArRsc;\r
398 UINT64 ArBsp;\r
399 UINT64 ArBspstore;\r
400 UINT64 ArRnat;\r
401\r
402 UINT64 ArFcr;\r
403\r
404 UINT64 ArEflag;\r
405 UINT64 ArCsd;\r
406 UINT64 ArSsd;\r
407 UINT64 ArCflg;\r
408 UINT64 ArFsr;\r
409 UINT64 ArFir;\r
410 UINT64 ArFdr;\r
411\r
412 UINT64 ArCcv;\r
413\r
414 UINT64 ArUnat;\r
415\r
416 UINT64 ArFpsr;\r
417\r
418 UINT64 ArPfs;\r
419 UINT64 ArLc;\r
420 UINT64 ArEc;\r
421\r
422 //\r
423 // control registers\r
424 //\r
425 UINT64 CrDcr;\r
426 UINT64 CrItm;\r
427 UINT64 CrIva;\r
428 UINT64 CrPta;\r
429 UINT64 CrIpsr;\r
430 UINT64 CrIsr;\r
431 UINT64 CrIip;\r
432 UINT64 CrIfa;\r
433 UINT64 CrItir;\r
434 UINT64 CrIipa;\r
435 UINT64 CrIfs;\r
436 UINT64 CrIim;\r
437 UINT64 CrIha;\r
438\r
439 //\r
440 // debug registers\r
441 //\r
442 UINT64 Dbr0;\r
443 UINT64 Dbr1;\r
444 UINT64 Dbr2;\r
445 UINT64 Dbr3;\r
446 UINT64 Dbr4;\r
447 UINT64 Dbr5;\r
448 UINT64 Dbr6;\r
449 UINT64 Dbr7;\r
450\r
451 UINT64 Ibr0;\r
452 UINT64 Ibr1;\r
453 UINT64 Ibr2;\r
454 UINT64 Ibr3;\r
455 UINT64 Ibr4;\r
456 UINT64 Ibr5;\r
457 UINT64 Ibr6;\r
458 UINT64 Ibr7;\r
459\r
460 //\r
461 // virtual registers - nat bits for R1-R31\r
462 //\r
463 UINT64 IntNat;\r
464\r
465} EFI_SYSTEM_CONTEXT_IPF;\r
466\r
467//\r
468// EBC processor exception types\r
469//\r
470#define EXCEPT_EBC_UNDEFINED 0\r
471#define EXCEPT_EBC_DIVIDE_ERROR 1\r
472#define EXCEPT_EBC_DEBUG 2\r
473#define EXCEPT_EBC_BREAKPOINT 3\r
474#define EXCEPT_EBC_OVERFLOW 4\r
475#define EXCEPT_EBC_INVALID_OPCODE 5 // opcode out of range\r
476#define EXCEPT_EBC_STACK_FAULT 6\r
477#define EXCEPT_EBC_ALIGNMENT_CHECK 7\r
478#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 // malformed instruction\r
479#define EXCEPT_EBC_BAD_BREAK 9 // BREAK 0 or undefined BREAK\r
480#define EXCEPT_EBC_STEP 10 // to support debug stepping\r
481//\r
482// For coding convenience, define the maximum valid EBC exception.\r
483//\r
484#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP\r
485\r
486//\r
487// EBC processor context definition\r
488//\r
489typedef struct {\r
490 UINT64 R0;\r
491 UINT64 R1;\r
492 UINT64 R2;\r
493 UINT64 R3;\r
494 UINT64 R4;\r
495 UINT64 R5;\r
496 UINT64 R6;\r
497 UINT64 R7;\r
498 UINT64 Flags;\r
499 UINT64 ControlFlags;\r
500 UINT64 Ip;\r
501} EFI_SYSTEM_CONTEXT_EBC;\r
502\r
503//\r
504// Universal EFI_SYSTEM_CONTEXT definition\r
505//\r
506typedef union {\r
507 EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;\r
508 EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;\r
509 EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;\r
510 EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;\r
511} EFI_SYSTEM_CONTEXT;\r
512\r
513//\r
514// DebugSupport callback function prototypes\r
515//\r
516\r
517/** \r
518 Registers and enables an exception callback function for the specified exception.\r
519 \r
520 @param ExceptionType Exception types in EBC, IA-32, X64, or IPF\r
521 @param SystemContext Exception content.\r
522 \r
523**/\r
524typedef\r
525VOID\r
526(*EFI_EXCEPTION_CALLBACK) (\r
527 IN EFI_EXCEPTION_TYPE ExceptionType,\r
528 IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
529 );\r
530\r
531/** \r
532 Registers and enables the on-target debug agent's periodic entry point.\r
533 \r
534 @param SystemContext Exception content.\r
535 \r
536**/\r
537typedef\r
538VOID\r
539(*EFI_PERIODIC_CALLBACK) (\r
540 IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
541 );\r
542\r
543//\r
544// Machine type definition\r
545//\r
546typedef enum {\r
547 IsaIa32 = IMAGE_FILE_MACHINE_I386, // 0x014C\r
548 IsaX64 = IMAGE_FILE_MACHINE_X64, // 0x8664\r
549 IsaIpf = IMAGE_FILE_MACHINE_IA64, // 0x0200\r
550 IsaEbc = IMAGE_FILE_MACHINE_EBC // 0x0EBC\r
551} EFI_INSTRUCTION_SET_ARCHITECTURE;\r
552\r
553\r
554//\r
555// DebugSupport member function definitions\r
556//\r
557\r
558/** \r
559 Returns the maximum value that may be used for the ProcessorIndex parameter in\r
560 RegisterPeriodicCallback() and RegisterExceptionCallback(). \r
561 \r
562 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
563 @param MaxProcessorIndex Pointer to a caller-allocated UINTN in which the maximum supported\r
564 processor index is returned. \r
565 \r
566 @retval EFI_SUCCESS The function completed successfully. \r
567 \r
568**/\r
569typedef\r
570EFI_STATUS\r
571(EFIAPI *EFI_GET_MAXIMUM_PROCESSOR_INDEX) (\r
572 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
573 OUT UINTN *MaxProcessorIndex\r
574 );\r
575\r
576/** \r
577 Registers a function to be called back periodically in interrupt context.\r
578 \r
579 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
580 @param ProcessorIndex Specifies which processor the callback function applies to.\r
581 @param PeriodicCallback A pointer to a function of type PERIODIC_CALLBACK that is the main\r
582 periodic entry point of the debug agent.\r
583 \r
584 @retval EFI_SUCCESS The function completed successfully. \r
585 @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback\r
586 function was previously registered. \r
587 @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback \r
588 function. \r
589 \r
590**/\r
591typedef\r
592EFI_STATUS\r
593(EFIAPI *EFI_REGISTER_PERIODIC_CALLBACK) (\r
594 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
595 IN UINTN ProcessorIndex,\r
596 IN EFI_PERIODIC_CALLBACK PeriodicCallback\r
597 );\r
598\r
599/** \r
600 Registers a function to be called when a given processor exception occurs.\r
601 \r
602 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
603 @param ProcessorIndex Specifies which processor the callback function applies to.\r
604 @param PeriodicCallback A pointer to a function of type EXCEPTION_CALLBACK that is called\r
605 when the processor exception specified by ExceptionType occurs. \r
606 @param ExceptionType Specifies which processor exception to hook. \r
607 \r
608 @retval EFI_SUCCESS The function completed successfully. \r
609 @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback\r
610 function was previously registered. \r
611 @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback \r
612 function. \r
613 \r
614**/\r
615typedef\r
616EFI_STATUS\r
617(EFIAPI *EFI_REGISTER_EXCEPTION_CALLBACK) (\r
618 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
619 IN UINTN ProcessorIndex,\r
620 IN EFI_EXCEPTION_CALLBACK ExceptionCallback,\r
621 IN EFI_EXCEPTION_TYPE ExceptionType\r
622 );\r
623\r
624/** \r
625 Invalidates processor instruction cache for a memory range. Subsequent execution in this range\r
626 causes a fresh memory fetch to retrieve code to be executed. \r
627 \r
628 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
629 @param ProcessorIndex Specifies which processor's instruction cache is to be invalidated.\r
630 @param Start Specifies the physical base of the memory range to be invalidated. \r
631 @param Length Specifies the minimum number of bytes in the processor's instruction\r
632 cache to invalidate. \r
633 \r
634 @retval EFI_SUCCESS The function completed successfully. \r
635 \r
636**/\r
637typedef\r
638EFI_STATUS\r
639(EFIAPI *EFI_INVALIDATE_INSTRUCTION_CACHE) (\r
640 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
641 IN UINTN ProcessorIndex,\r
642 IN VOID *Start,\r
643 IN UINT64 Length\r
644 );\r
645\r
646//\r
647// DebugSupport protocol definition\r
648//\r
649struct _EFI_DEBUG_SUPPORT_PROTOCOL {\r
650 EFI_INSTRUCTION_SET_ARCHITECTURE Isa;\r
651 EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;\r
652 EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;\r
653 EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback;\r
654 EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache;\r
655};\r
656\r
657extern EFI_GUID gEfiDebugSupportProtocolGuid;\r
658\r
659#endif \r
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