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1 | /** @file\r |
2 | I2C Master Protocol as defined in the PI 1.3 specification.\r | |
3 | \r | |
9095d37b | 4 | This protocol manipulates the I2C host controller to perform transactions as a master\r |
4006b0b5 EL |
5 | on the I2C bus using the current state of any switches or multiplexers in the I2C bus.\r |
6 | \r | |
9095d37b | 7 | Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 8 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
4006b0b5 EL |
9 | \r |
10 | @par Revision Reference:\r | |
11 | This protocol is from PI Version 1.3.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef __I2C_MASTER_H__\r | |
16 | #define __I2C_MASTER_H__\r | |
17 | \r | |
18 | #include <Pi/PiI2c.h>\r | |
19 | \r | |
2f88bd3a | 20 | #define EFI_I2C_MASTER_PROTOCOL_GUID { 0xcd72881f, 0x45b5, 0x4feb, { 0x98, 0xc8, 0x31, 0x3d, 0xa8, 0x11, 0x74, 0x62 }}\r |
4006b0b5 EL |
21 | \r |
22 | typedef struct _EFI_I2C_MASTER_PROTOCOL EFI_I2C_MASTER_PROTOCOL;\r | |
23 | \r | |
24 | /**\r | |
25 | Set the frequency for the I2C clock line.\r | |
26 | \r | |
27 | This routine must be called at or below TPL_NOTIFY.\r | |
28 | \r | |
29 | The software and controller do a best case effort of using the specified\r | |
30 | frequency for the I2C bus. If the frequency does not match exactly then\r | |
31 | the I2C master protocol selects the next lower frequency to avoid\r | |
32 | exceeding the operating conditions for any of the I2C devices on the bus.\r | |
33 | For example if 400 KHz was specified and the controller's divide network\r | |
34 | only supports 402 KHz or 398 KHz then the I2C master protocol selects 398\r | |
35 | KHz. If there are not lower frequencies available, then return\r | |
36 | EFI_UNSUPPORTED.\r | |
37 | \r | |
38 | @param[in] This Pointer to an EFI_I2C_MASTER_PROTOCOL structure\r | |
39 | @param[in] BusClockHertz Pointer to the requested I2C bus clock frequency\r | |
40 | in Hertz. Upon return this value contains the\r | |
41 | actual frequency in use by the I2C controller.\r | |
42 | \r | |
43 | @retval EFI_SUCCESS The bus frequency was set successfully.\r | |
44 | @retval EFI_ALREADY_STARTED The controller is busy with another transaction.\r | |
45 | @retval EFI_INVALID_PARAMETER BusClockHertz is NULL\r | |
46 | @retval EFI_UNSUPPORTED The controller does not support this frequency.\r | |
47 | \r | |
48 | **/\r | |
49 | typedef\r | |
50 | EFI_STATUS\r | |
2f88bd3a | 51 | (EFIAPI *EFI_I2C_MASTER_PROTOCOL_SET_BUS_FREQUENCY)(\r |
4006b0b5 EL |
52 | IN CONST EFI_I2C_MASTER_PROTOCOL *This,\r |
53 | IN OUT UINTN *BusClockHertz\r | |
54 | );\r | |
55 | \r | |
56 | /**\r | |
57 | Reset the I2C controller and configure it for use\r | |
58 | \r | |
59 | This routine must be called at or below TPL_NOTIFY.\r | |
60 | \r | |
61 | The I2C controller is reset. The caller must call SetBusFrequench() after\r | |
62 | calling Reset().\r | |
63 | \r | |
64 | @param[in] This Pointer to an EFI_I2C_MASTER_PROTOCOL structure.\r | |
65 | \r | |
66 | @retval EFI_SUCCESS The reset completed successfully.\r | |
67 | @retval EFI_ALREADY_STARTED The controller is busy with another transaction.\r | |
68 | @retval EFI_DEVICE_ERROR The reset operation failed.\r | |
9095d37b | 69 | \r |
4006b0b5 EL |
70 | **/\r |
71 | typedef\r | |
72 | EFI_STATUS\r | |
2f88bd3a | 73 | (EFIAPI *EFI_I2C_MASTER_PROTOCOL_RESET)(\r |
4006b0b5 EL |
74 | IN CONST EFI_I2C_MASTER_PROTOCOL *This\r |
75 | );\r | |
76 | \r | |
77 | /**\r | |
78 | Start an I2C transaction on the host controller.\r | |
79 | \r | |
80 | This routine must be called at or below TPL_NOTIFY. For synchronous\r | |
81 | requests this routine must be called at or below TPL_CALLBACK.\r | |
82 | \r | |
83 | This function initiates an I2C transaction on the controller. To\r | |
84 | enable proper error handling by the I2C protocol stack, the I2C\r | |
85 | master protocol does not support queuing but instead only manages\r | |
86 | one I2C transaction at a time. This API requires that the I2C bus\r | |
87 | is in the correct configuration for the I2C transaction.\r | |
88 | \r | |
89 | The transaction is performed by sending a start-bit and selecting the\r | |
90 | I2C device with the specified I2C slave address and then performing\r | |
91 | the specified I2C operations. When multiple operations are requested\r | |
92 | they are separated with a repeated start bit and the slave address.\r | |
93 | The transaction is terminated with a stop bit.\r | |
94 | \r | |
95 | When Event is NULL, StartRequest operates synchronously and returns\r | |
96 | the I2C completion status as its return value.\r | |
97 | \r | |
98 | When Event is not NULL, StartRequest synchronously returns EFI_SUCCESS\r | |
99 | indicating that the I2C transaction was started asynchronously. The\r | |
100 | transaction status value is returned in the buffer pointed to by\r | |
101 | I2cStatus upon the completion of the I2C transaction when I2cStatus\r | |
102 | is not NULL. After the transaction status is returned the Event is\r | |
103 | signaled.\r | |
104 | \r | |
105 | Note: The typical consumer of this API is the I2C host protocol.\r | |
106 | Extreme care must be taken by other consumers of this API to prevent\r | |
107 | confusing the third party I2C drivers due to a state change at the\r | |
108 | I2C device which the third party I2C drivers did not initiate. I2C\r | |
109 | platform specific code may use this API within these guidelines.\r | |
110 | \r | |
111 | @param[in] This Pointer to an EFI_I2C_MASTER_PROTOCOL structure.\r | |
112 | @param[in] SlaveAddress Address of the device on the I2C bus. Set the\r | |
113 | I2C_ADDRESSING_10_BIT when using 10-bit addresses,\r | |
114 | clear this bit for 7-bit addressing. Bits 0-6\r | |
115 | are used for 7-bit I2C slave addresses and bits\r | |
116 | 0-9 are used for 10-bit I2C slave addresses.\r | |
117 | @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET\r | |
118 | structure describing the I2C transaction.\r | |
119 | @param[in] Event Event to signal for asynchronous transactions,\r | |
120 | NULL for asynchronous transactions\r | |
121 | @param[out] I2cStatus Optional buffer to receive the I2C transaction\r | |
122 | completion status\r | |
123 | \r | |
124 | @retval EFI_SUCCESS The asynchronous transaction was successfully\r | |
125 | started when Event is not NULL.\r | |
126 | @retval EFI_SUCCESS The transaction completed successfully when\r | |
127 | Event is NULL.\r | |
128 | @retval EFI_ALREADY_STARTED The controller is busy with another transaction.\r | |
129 | @retval EFI_BAD_BUFFER_SIZE The RequestPacket->LengthInBytes value is too\r | |
130 | large.\r | |
131 | @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the\r | |
132 | transaction.\r | |
133 | @retval EFI_INVALID_PARAMETER RequestPacket is NULL\r | |
134 | @retval EFI_NOT_FOUND Reserved bit set in the SlaveAddress parameter\r | |
135 | @retval EFI_NO_RESPONSE The I2C device is not responding to the slave\r | |
136 | address. EFI_DEVICE_ERROR will be returned if\r | |
137 | the controller cannot distinguish when the NACK\r | |
138 | occurred.\r | |
139 | @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C transaction\r | |
140 | @retval EFI_UNSUPPORTED The controller does not support the requested\r | |
141 | transaction.\r | |
142 | \r | |
143 | **/\r | |
144 | typedef\r | |
145 | EFI_STATUS\r | |
2f88bd3a | 146 | (EFIAPI *EFI_I2C_MASTER_PROTOCOL_START_REQUEST)(\r |
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147 | IN CONST EFI_I2C_MASTER_PROTOCOL *This,\r |
148 | IN UINTN SlaveAddress,\r | |
149 | IN EFI_I2C_REQUEST_PACKET *RequestPacket,\r | |
150 | IN EFI_EVENT Event OPTIONAL,\r | |
151 | OUT EFI_STATUS *I2cStatus OPTIONAL\r | |
152 | );\r | |
153 | \r | |
154 | ///\r | |
155 | /// I2C master mode protocol\r | |
156 | ///\r | |
157 | /// This protocol manipulates the I2C host controller to perform transactions as a\r | |
158 | /// master on the I2C bus using the current state of any switches or multiplexers\r | |
159 | /// in the I2C bus.\r | |
160 | ///\r | |
161 | struct _EFI_I2C_MASTER_PROTOCOL {\r | |
162 | ///\r | |
163 | /// Set the clock frequency for the I2C bus.\r | |
164 | ///\r | |
2f88bd3a | 165 | EFI_I2C_MASTER_PROTOCOL_SET_BUS_FREQUENCY SetBusFrequency;\r |
4006b0b5 EL |
166 | \r |
167 | ///\r | |
168 | /// Reset the I2C host controller.\r | |
169 | ///\r | |
2f88bd3a | 170 | EFI_I2C_MASTER_PROTOCOL_RESET Reset;\r |
4006b0b5 EL |
171 | \r |
172 | ///\r | |
173 | /// Start an I2C transaction in master mode on the host controller.\r | |
174 | ///\r | |
2f88bd3a | 175 | EFI_I2C_MASTER_PROTOCOL_START_REQUEST StartRequest;\r |
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176 | \r |
177 | ///\r | |
178 | /// Pointer to an EFI_I2C_CONTROLLER_CAPABILITIES data structure containing\r | |
179 | /// the capabilities of the I2C host controller.\r | |
180 | ///\r | |
2f88bd3a | 181 | CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;\r |
4006b0b5 EL |
182 | };\r |
183 | \r | |
2f88bd3a | 184 | extern EFI_GUID gEfiI2cMasterProtocolGuid;\r |
4006b0b5 | 185 | \r |
2f88bd3a | 186 | #endif // __I2C_MASTER_H__\r |