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73c31a3d 1/** @file\r
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2 This file declares PCI Host Bridge Resource Allocation Protocol which\r
3 provides the basic interfaces to abstract a PCI host bridge resource allocation.\r
73c31a3d 4 This protocol is mandatory if the system includes PCI devices.\r
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5\r
6Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
9344f092 7SPDX-License-Identifier: BSD-2-Clause-Patent\r
73c31a3d 8\r
9 @par Revision Reference:\r
9095d37b 10 This Protocol is defined in UEFI Platform Initialization Specification 1.2\r
af2dc6a7 11 Volume 5: Standards.\r
9095d37b 12\r
73c31a3d 13**/\r
14\r
15#ifndef _PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_H_\r
16#define _PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_H_\r
17\r
18//\r
19// This file must be included because EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
20// uses EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS\r
21//\r
22#include <Protocol/PciRootBridgeIo.h>\r
23\r
24///\r
af2dc6a7 25/// Global ID for the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
73c31a3d 26///\r
27#define EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GUID \\r
28 { \\r
29 0xCF8034BE, 0x6768, 0x4d8b, {0xB7,0x39,0x7C,0xCE,0x68,0x3A,0x9F,0xBE } \\r
30 }\r
31\r
32///\r
af2dc6a7 33/// Forward declaration for EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
73c31a3d 34///\r
35typedef struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL;\r
36\r
37/// If this bit is set, then the PCI Root Bridge does not\r
38/// support separate windows for Non-prefetchable and Prefetchable\r
39/// memory. A PCI bus driver needs to include requests for Prefetchable\r
40/// memory in the Non-prefetchable memory pool.\r
41///\r
42#define EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM 1\r
43\r
44///\r
45/// If this bit is set, then the PCI Root Bridge supports\r
46/// 64 bit memory windows. If this bit is not set,\r
47/// the PCI bus driver needs to include requests for 64 bit\r
48/// memory address in the corresponding 32 bit memory pool.\r
49///\r
50#define EFI_PCI_HOST_BRIDGE_MEM64_DECODE 2\r
51\r
52///\r
9095d37b 53/// A UINT64 value that contains the status of a PCI resource requested\r
73c31a3d 54/// in the Configuration parameter returned by GetProposedResources()\r
55/// The legal values are EFI_RESOURCE_SATISFIED and EFI_RESOURCE_NOT_SATISFIED\r
56///\r
57typedef UINT64 EFI_RESOURCE_ALLOCATION_STATUS;\r
58\r
59///\r
9095d37b 60/// The request of this resource type could be fulfilled. Used in the\r
73c31a3d 61/// Configuration parameter returned by GetProposedResources() to identify\r
62/// a PCI resources request that can be satisfied.\r
63///\r
64#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL\r
65\r
66///\r
67/// The request of this resource type could not be fulfilled for its\r
9095d37b 68/// absence in the host bridge resource pool. Used in the Configuration parameter\r
73c31a3d 69/// returned by GetProposedResources() to identify a PCI resources request that\r
70/// can not be satisfied.\r
71///\r
72#define EFI_RESOURCE_NOT_SATISFIED 0xFFFFFFFFFFFFFFFFULL\r
73\r
74///\r
af2dc6a7 75/// This enum is used to specify the phase of the PCI enumaeration process.\r
73c31a3d 76///\r
77typedef enum {\r
78 ///\r
79 /// Reset the host bridge PCI apertures and internal data structures.\r
80 /// PCI enumerator should issue this notification before starting fresh\r
81 /// enumeration process. Enumeration cannot be restarted after sending\r
82 /// any other notification such as EfiPciHostBridgeBeginBusAllocation.\r
83 ///\r
84 EfiPciHostBridgeBeginEnumeration,\r
85\r
86 ///\r
87 /// The bus allocation phase is about to begin. No specific action\r
88 /// is required here. This notification can be used to perform any\r
9095d37b 89 /// chipset specific programming.\r
73c31a3d 90 ///\r
91 EfiPciHostBridgeBeginBusAllocation,\r
92\r
93 ///\r
94 /// The bus allocation and bus programming phase is complete. No specific\r
95 /// action is required here. This notification can be used to perform any\r
9095d37b 96 /// chipset specific programming.\r
73c31a3d 97 ///\r
98 EfiPciHostBridgeEndBusAllocation,\r
9095d37b 99\r
73c31a3d 100 ///\r
101 /// The resource allocation phase is about to begin.No specific action is\r
9095d37b 102 /// required here. This notification can be used to perform any chipset specific programming.\r
73c31a3d 103 ///\r
104 EfiPciHostBridgeBeginResourceAllocation,\r
9095d37b 105\r
73c31a3d 106 ///\r
107 /// Allocate resources per previously submitted requests for all the PCI Root\r
108 /// Bridges. These resource settings are returned on the next call to\r
9095d37b 109 /// GetProposedResources().\r
73c31a3d 110 ///\r
111 EfiPciHostBridgeAllocateResources,\r
9095d37b 112\r
73c31a3d 113 ///\r
114 /// Program the Host Bridge hardware to decode previously allocated resources\r
115 /// (proposed resources) for all the PCI Root Bridges.\r
116 ///\r
117 EfiPciHostBridgeSetResources,\r
9095d37b 118\r
73c31a3d 119 ///\r
120 /// De-allocate previously allocated resources previously for all the PCI\r
9095d37b 121 /// Root Bridges and reset the I/O and memory apertures to initial state.\r
73c31a3d 122 ///\r
123 EfiPciHostBridgeFreeResources,\r
9095d37b 124\r
73c31a3d 125 ///\r
126 /// The resource allocation phase is completed. No specific action is required\r
9095d37b 127 /// here. This notification can be used to perform any chipset specific programming.\r
73c31a3d 128 ///\r
1f7ff5ab 129 EfiPciHostBridgeEndResourceAllocation,\r
130\r
131 ///\r
132 /// The Host Bridge Enumeration is completed. No specific action is required here.\r
133 /// This notification can be used to perform any chipset specific programming.\r
134 ///\r
135 EfiPciHostBridgeEndEnumeration,\r
136 EfiMaxPciHostBridgeEnumerationPhase\r
73c31a3d 137} EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE;\r
138\r
139///\r
140/// Definitions of 2 notification points.\r
141///\r
142typedef enum {\r
143 ///\r
144 /// This notification is only applicable to PCI-PCI bridges and\r
145 /// indicates that the PCI enumerator is about to begin enumerating\r
146 /// the bus behind the PCI-PCI Bridge. This notification is sent after\r
147 /// the primary bus number, the secondary bus number and the subordinate\r
148 /// bus number registers in the PCI-PCI Bridge are programmed to valid\r
149 /// (not necessary final) values\r
150 ///\r
151 EfiPciBeforeChildBusEnumeration,\r
152\r
153 ///\r
154 /// This notification is sent before the PCI enumerator probes BAR registers\r
9095d37b 155 /// for every valid PCI function.\r
73c31a3d 156 ///\r
157 EfiPciBeforeResourceCollection\r
158} EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE;\r
159\r
160/**\r
9095d37b 161 These are the notifications from the PCI bus driver that it is about to enter a certain phase of the PCI\r
73c31a3d 162 enumeration process.\r
163\r
9095d37b 164 @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
73c31a3d 165 instance.\r
af2dc6a7 166 @param[in] Phase The phase during enumeration.\r
73c31a3d 167\r
168 @retval EFI_SUCCESS The notification was accepted without any errors.\r
169 @retval EFI_INVALID_PARAMETER The Phase is invalid.\r
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170 @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error\r
171 is valid for a Phase of EfiPciHostBridgeAllocateResources if\r
172 SubmitResources() has not been called for one or more\r
73c31a3d 173 PCI root bridges before this call.\r
9095d37b 174 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid for\r
73c31a3d 175 a Phase of EfiPciHostBridgeSetResources.\r
9095d37b 176 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
73c31a3d 177 This error is valid for a Phase of EfiPciHostBridgeAllocateResources\r
9095d37b 178 if the previously submitted resource requests cannot be fulfilled or were only\r
73c31a3d 179 partially fulfilled\r
180\r
181**/\r
182typedef\r
183EFI_STATUS\r
184(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_NOTIFY_PHASE)(\r
185 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
186 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
187 );\r
188\r
189/**\r
190 Returns the device handle of the next PCI root bridge that is associated with this host bridge.\r
191\r
9095d37b 192 @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
73c31a3d 193 instance.\r
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194 @param[in,out] RootBridgeHandle Returns the device handle of the next PCI root bridge. On input, it holds the\r
195 RootBridgeHandle that was returned by the most recent call to\r
196 GetNextRootBridge(). If RootBridgeHandle is NULL on input, the handle\r
73c31a3d 197 for the first PCI root bridge is returned.\r
198\r
199 @retval EFI_SUCCESS The requested attribute information was returned.\r
9095d37b 200 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was returned\r
73c31a3d 201 on a previous call to GetNextRootBridge().\r
202 @retval EFI_NOT_FOUND There are no more PCI root bridge device handles.\r
203\r
204**/\r
205typedef\r
206EFI_STATUS\r
207(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_NEXT_ROOT_BRIDGE)(\r
208 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
209 IN OUT EFI_HANDLE *RootBridgeHandle\r
210 );\r
211\r
212/**\r
213 Returns the allocation attributes of a PCI root bridge.\r
214\r
9095d37b 215 @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
73c31a3d 216 instance.\r
217 @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested.\r
218 @param[out] Attribute The pointer to attributes of the PCI root bridge.\r
219\r
220 @retval EFI_SUCCESS The requested attribute information was returned.\r
221 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
222 @retval EFI_INVALID_PARAMETER Attributes is NULL.\r
223\r
224**/\r
225typedef\r
226EFI_STATUS\r
227(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_ATTRIBUTES)(\r
228 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
229 IN EFI_HANDLE RootBridgeHandle,\r
230 OUT UINT64 *Attributes\r
231 );\r
232\r
233/**\r
234 Sets up the specified PCI root bridge for the bus enumeration process.\r
235\r
9095d37b 236 @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
73c31a3d 237 instance.\r
238 @param[in] RootBridgeHandle The PCI root bridge to be set up.\r
af2dc6a7 239 @param[out] Configuration The pointer to the pointer to the PCI bus resource descriptor.\r
73c31a3d 240\r
9095d37b 241 @retval EFI_SUCCESS The PCI root bridge was set up and the bus range was returned in\r
73c31a3d 242 Configuration.\r
243 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
244 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
245 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
246\r
247**/\r
248typedef\r
249EFI_STATUS\r
250(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_START_BUS_ENUMERATION)(\r
251 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
252 IN EFI_HANDLE RootBridgeHandle,\r
253 OUT VOID **Configuration\r
254 );\r
255\r
256/**\r
257 Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.\r
258\r
af2dc6a7 259 @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
9095d37b 260 instance.\r
73c31a3d 261 @param[in] RootBridgeHandle The PCI root bridge whose bus range is to be programmed.\r
af2dc6a7 262 @param[in] Configuration The pointer to the PCI bus resource descriptor.\r
73c31a3d 263\r
264 @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.\r
265 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
266 @retval EFI_INVALID_PARAMETER Configuration is NULL\r
9095d37b 267 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI (2.0 & 3.0)\r
73c31a3d 268 resource descriptor.\r
269 @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource\r
270 descriptor.\r
9095d37b 271 @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI (2.0 & 3.0) resource\r
73c31a3d 272 descriptors other than bus descriptors.\r
9095d37b 273 @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource\r
73c31a3d 274 descriptors.\r
275 @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.\r
276 @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.\r
277 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
278\r
279**/\r
280typedef\r
281EFI_STATUS\r
282(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SET_BUS_NUMBERS)(\r
283 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
284 IN EFI_HANDLE RootBridgeHandle,\r
285 IN VOID *Configuration\r
286 );\r
287\r
288/**\r
289 Submits the I/O and memory resource requirements for the specified PCI root bridge.\r
290\r
9095d37b 291 @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
73c31a3d 292 instance.\r
9095d37b 293 @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being\r
73c31a3d 294 submitted.\r
295 @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.\r
296\r
9095d37b 297 @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were\r
73c31a3d 298 accepted.\r
299 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
300 @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
9095d37b 301 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI (2.0 & 3.0)\r
73c31a3d 302 resource descriptor.\r
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303 @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource\r
304 types that are not supported by this PCI root bridge. This error will\r
305 happen if the caller did not combine resources according to\r
73c31a3d 306 Attributes that were returned by GetAllocAttributes().\r
307 @retval EFI_INVALID_PARAMETER "Address Range Maximum" is invalid.\r
308 @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.\r
309 @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.\r
9095d37b 310\r
73c31a3d 311**/\r
312typedef\r
313EFI_STATUS\r
314(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SUBMIT_RESOURCES)(\r
315 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
316 IN EFI_HANDLE RootBridgeHandle,\r
317 IN VOID *Configuration\r
318 );\r
319\r
320/**\r
321 Returns the proposed resource settings for the specified PCI root bridge.\r
322\r
9095d37b 323 @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
73c31a3d 324 instance.\r
325 @param[in] RootBridgeHandle The PCI root bridge handle.\r
326 @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.\r
327\r
328 @retval EFI_SUCCESS The requested parameters were returned.\r
329 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
330 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
331 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
332\r
333**/\r
334typedef\r
335EFI_STATUS\r
336(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_PROPOSED_RESOURCES)(\r
337 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
338 IN EFI_HANDLE RootBridgeHandle,\r
339 OUT VOID **Configuration\r
340 );\r
341\r
342/**\r
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343 Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
344 stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
73c31a3d 345 PCI controllers before enumeration.\r
346\r
af2dc6a7 347 @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
73c31a3d 348 @param[in] RootBridgeHandle The associated PCI root bridge handle.\r
349 @param[in] PciAddress The address of the PCI device on the PCI bus.\r
350 @param[in] Phase The phase of the PCI device enumeration.\r
351\r
352 @retval EFI_SUCCESS The requested parameters were returned.\r
353 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
9095d37b 354 @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r
73c31a3d 355 EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
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356 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator\r
357 should not enumerate this device, including its child devices if it is\r
73c31a3d 358 a PCI-to-PCI bridge.\r
359\r
360**/\r
361typedef\r
362EFI_STATUS\r
363(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_PREPROCESS_CONTROLLER)(\r
364 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
365 IN EFI_HANDLE RootBridgeHandle,\r
366 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
367 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
368 );\r
369\r
370///\r
371/// Provides the basic interfaces to abstract a PCI host bridge resource allocation.\r
372///\r
373struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL {\r
374 ///\r
375 /// The notification from the PCI bus enumerator that it is about to enter\r
376 /// a certain phase during the enumeration process.\r
377 ///\r
378 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_NOTIFY_PHASE NotifyPhase;\r
9095d37b 379\r
73c31a3d 380 ///\r
381 /// Retrieves the device handle for the next PCI root bridge that is produced by the\r
9095d37b 382 /// host bridge to which this instance of the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is attached.\r
73c31a3d 383 ///\r
384 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_NEXT_ROOT_BRIDGE GetNextRootBridge;\r
9095d37b 385\r
73c31a3d 386 ///\r
387 /// Retrieves the allocation-related attributes of a PCI root bridge.\r
388 ///\r
389 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_ATTRIBUTES GetAllocAttributes;\r
9095d37b 390\r
73c31a3d 391 ///\r
392 /// Sets up a PCI root bridge for bus enumeration.\r
393 ///\r
394 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_START_BUS_ENUMERATION StartBusEnumeration;\r
9095d37b 395\r
73c31a3d 396 ///\r
397 /// Sets up the PCI root bridge so that it decodes a specific range of bus numbers.\r
398 ///\r
399 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SET_BUS_NUMBERS SetBusNumbers;\r
9095d37b 400\r
73c31a3d 401 ///\r
402 /// Submits the resource requirements for the specified PCI root bridge.\r
403 ///\r
404 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SUBMIT_RESOURCES SubmitResources;\r
9095d37b 405\r
73c31a3d 406 ///\r
407 /// Returns the proposed resource assignment for the specified PCI root bridges.\r
408 ///\r
409 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_PROPOSED_RESOURCES GetProposedResources;\r
9095d37b 410\r
73c31a3d 411 ///\r
412 /// Provides hooks from the PCI bus driver to every PCI controller\r
413 /// (device/function) at various stages of the PCI enumeration process that\r
414 /// allow the host bridge driver to preinitialize individual PCI controllers\r
9095d37b 415 /// before enumeration.\r
73c31a3d 416 ///\r
417 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_PREPROCESS_CONTROLLER PreprocessController;\r
418};\r
419\r
420extern EFI_GUID gEfiPciHostBridgeResourceAllocationProtocolGuid;\r
421\r
422#endif\r