projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| b15cbd9c BS |
1 | /** @file\r |
| 2 | MSR Definitions.\r | |
| 3 | \r | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
| 7 | provided for that MSR.\r | |
| 8 | \r | |
| 9 | Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>\r | |
| 0acd8697 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| b15cbd9c BS |
11 | \r |
| 12 | @par Specification Reference:\r | |
| 788421d5 | 13 | AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34\r |
| b15cbd9c BS |
14 | \r |
| 15 | **/\r | |
| 16 | \r | |
| 8cf19dc7 DB |
17 | #ifndef __FAM17_MSR_H__\r |
| 18 | #define __FAM17_MSR_H__\r | |
| b15cbd9c | 19 | \r |
| a80e8878 TL |
20 | /**\r |
| 21 | Secure Encrypted Virtualization - Encrypted State (SEV-ES) GHCB register\r | |
| 22 | \r | |
| 23 | **/\r | |
| 24 | #define MSR_SEV_ES_GHCB 0xc0010130\r | |
| 25 | \r | |
| 26 | /**\r | |
| 27 | MSR information returned for #MSR_SEV_ES_GHCB\r | |
| 28 | **/\r | |
| 29 | typedef union {\r | |
| 30 | struct {\r | |
| 31 | UINT32 Function:12;\r | |
| 32 | UINT32 Reserved1:20;\r | |
| 33 | UINT32 Reserved2:32;\r | |
| 34 | } GhcbInfo;\r | |
| 35 | \r | |
| 36 | struct {\r | |
| 37 | UINT8 Reserved[3];\r | |
| 38 | UINT8 SevEncryptionBitPos;\r | |
| 39 | UINT16 SevEsProtocolMin;\r | |
| 40 | UINT16 SevEsProtocolMax;\r | |
| 41 | } GhcbProtocol;\r | |
| 42 | \r | |
| 43 | struct {\r | |
| 44 | UINT32 Function:12;\r | |
| 45 | UINT32 ReasonCodeSet:4;\r | |
| 46 | UINT32 ReasonCode:8;\r | |
| 47 | UINT32 Reserved1:8;\r | |
| 48 | UINT32 Reserved2:32;\r | |
| 49 | } GhcbTerminate;\r | |
| 50 | \r | |
| 51 | VOID *Ghcb;\r | |
| 52 | \r | |
| 53 | UINT64 GhcbPhysicalAddress;\r | |
| 54 | } MSR_SEV_ES_GHCB_REGISTER;\r | |
| 55 | \r | |
| 56 | #define GHCB_INFO_SEV_INFO 1\r | |
| 57 | #define GHCB_INFO_SEV_INFO_GET 2\r | |
| 58 | #define GHCB_INFO_CPUID_REQUEST 4\r | |
| 59 | #define GHCB_INFO_CPUID_RESPONSE 5\r | |
| 60 | #define GHCB_INFO_TERMINATE_REQUEST 256\r | |
| 61 | \r | |
| 62 | #define GHCB_TERMINATE_GHCB 0\r | |
| 63 | #define GHCB_TERMINATE_GHCB_GENERAL 0\r | |
| 64 | #define GHCB_TERMINATE_GHCB_PROTOCOL 1\r | |
| 65 | \r | |
| b15cbd9c BS |
66 | /**\r |
| 67 | Secure Encrypted Virtualization (SEV) status register\r | |
| 68 | \r | |
| 69 | **/\r | |
| 70 | #define MSR_SEV_STATUS 0xc0010131\r | |
| 71 | \r | |
| 72 | /**\r | |
| 73 | MSR information returned for #MSR_SEV_STATUS\r | |
| 74 | **/\r | |
| 75 | typedef union {\r | |
| 76 | ///\r | |
| 77 | /// Individual bit fields\r | |
| 78 | ///\r | |
| 79 | struct {\r | |
| 80 | ///\r | |
| 81 | /// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled\r | |
| 82 | ///\r | |
| 83 | UINT32 SevBit:1;\r | |
| 84 | \r | |
| 85 | ///\r | |
| 86 | /// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled\r | |
| 87 | ///\r | |
| 88 | UINT32 SevEsBit:1;\r | |
| 89 | \r | |
| 0095070e BS |
90 | ///\r |
| 91 | /// [Bit 2] Secure Nested Paging (SevSnp) is enabled\r | |
| 92 | ///\r | |
| 93 | UINT32 SevSnpBit:1;\r | |
| 94 | \r | |
| 95 | UINT32 Reserved2:29;\r | |
| b15cbd9c BS |
96 | } Bits;\r |
| 97 | ///\r | |
| 98 | /// All bit fields as a 32-bit value\r | |
| 99 | ///\r | |
| 100 | UINT32 Uint32;\r | |
| 101 | ///\r | |
| 102 | /// All bit fields as a 64-bit value\r | |
| 103 | ///\r | |
| 104 | UINT64 Uint64;\r | |
| 105 | } MSR_SEV_STATUS_REGISTER;\r | |
| 106 | \r | |
| 107 | #endif\r |