MdePkg/Register/Amd: expand the SEV MSR to include the SNP definition

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Define the SEV-SNP MSR bits.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Message-Id: <20210519181949.6574-2-brijesh.singh@amd.com>

diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h b/MdePkg/Include/Register/Amd/Fam17Msr.h
index e4db09c5184c32d1f633749b32abff3493cbd0a8..716d52fd508d8c4df4e69490d2c200ded6c2a3f3 100644 (file)
--- a/MdePkg/Include/Register/Amd/Fam17Msr.h
+++ b/MdePkg/Include/Register/Amd/Fam17Msr.h
@@ -87,7 +87,12 @@ typedef union {
     ///\r
     UINT32  SevEsBit:1;\r
 \r
-    UINT32  Reserved:30;\r
+    ///\r
+    /// [Bit 2] Secure Nested Paging (SevSnp) is enabled\r
+    ///\r
+    UINT32  SevSnpBit:1;\r
+\r
+    UINT32  Reserved2:29;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r