[mirror_edk2.git] / MdePkg / Include / Register / Intel / Msr / BroadwellMsr.h

/** @file\r
  MSR Definitions for Intel processors based on the Broadwell microarchitecture.\r
\r
  Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
  are provided for MSRs that contain one or more bit fields.  If the MSR value\r
  returned is a single 32-bit or 64-bit value, then a data structure is not\r
  provided for that MSR.\r
\r
  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
  @par Specification Reference:\r
  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
  May 2018, Volume 4: Model-Specific-Registers (MSR)\r
\r
**/\r
\r
#ifndef __BROADWELL_MSR_H__\r
#define __BROADWELL_MSR_H__\r
\r
#include <Register/Intel/ArchitecturalMsr.h>\r
\r
/**\r
  Is Intel processors based on the Broadwell microarchitecture?\r
\r
  @param   DisplayFamily  Display Family ID\r
  @param   DisplayModel   Display Model ID\r
\r
  @retval  TRUE   Yes, it is.\r
  @retval  FALSE  No, it isn't.\r
**/\r
#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \\r
  (DisplayFamily == 0x06 && \\r
   (                        \\r
    DisplayModel == 0x3D || \\r
    DisplayModel == 0x47 || \\r
    DisplayModel == 0x4F || \\r
    DisplayModel == 0x56    \\r
    )                       \\r
   )\r
\r
/**\r
  Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control\r
  Facilities.".\r
\r
  @param  ECX  MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);\r
  AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r
  @endcode\r
  @note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
**/\r
#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS  0x0000038E\r
\r
/**\r
  MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Ovf_PMC0.\r
    ///\r
    UINT32    Ovf_PMC0       : 1;\r
    ///\r
    /// [Bit 1] Ovf_PMC1.\r
    ///\r
    UINT32    Ovf_PMC1       : 1;\r
    ///\r
    /// [Bit 2] Ovf_PMC2.\r
    ///\r
    UINT32    Ovf_PMC2       : 1;\r
    ///\r
    /// [Bit 3] Ovf_PMC3.\r
    ///\r
    UINT32    Ovf_PMC3       : 1;\r
    UINT32    Reserved1      : 28;\r
    ///\r
    /// [Bit 32] Ovf_FixedCtr0.\r
    ///\r
    UINT32    Ovf_FixedCtr0  : 1;\r
    ///\r
    /// [Bit 33] Ovf_FixedCtr1.\r
    ///\r
    UINT32    Ovf_FixedCtr1  : 1;\r
    ///\r
    /// [Bit 34] Ovf_FixedCtr2.\r
    ///\r
    UINT32    Ovf_FixedCtr2  : 1;\r
    UINT32    Reserved2      : 20;\r
    ///\r
    /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical\r
    /// Addresses (ToPA).".\r
    ///\r
    UINT32    Trace_ToPA_PMI : 1;\r
    UINT32    Reserved3      : 5;\r
    ///\r
    /// [Bit 61] Ovf_Uncore.\r
    ///\r
    UINT32    Ovf_Uncore     : 1;\r
    ///\r
    /// [Bit 62] Ovf_BufDSSAVE.\r
    ///\r
    UINT32    OvfBuf         : 1;\r
    ///\r
    /// [Bit 63] CondChgd.\r
    ///\r
    UINT32    CondChgd       : 1;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
\r
/**\r
  Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
  specific C-state code names, unrelated to MWAIT extension C-state parameters\r
  or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
\r
  @param  ECX  MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);\r
  AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
  @endcode\r
  @note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL  0x000000E2\r
\r
/**\r
  MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r
    /// processor-specific C-state code name (consuming the least power) for\r
    /// the package. The default is set as factory-configured package C-state\r
    /// limit. The following C-state code name encodings are supported: 0000b:\r
    /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6\r
    /// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.\r
    ///\r
    UINT32    Limit              : 4;\r
    UINT32    Reserved1          : 6;\r
    ///\r
    /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
    ///\r
    UINT32    IO_MWAIT           : 1;\r
    UINT32    Reserved2          : 4;\r
    ///\r
    /// [Bit 15] CFG Lock (R/WO).\r
    ///\r
    UINT32    CFGLock            : 1;\r
    UINT32    Reserved3          : 9;\r
    ///\r
    /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
    ///\r
    UINT32    C3AutoDemotion     : 1;\r
    ///\r
    /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
    ///\r
    UINT32    C1AutoDemotion     : 1;\r
    ///\r
    /// [Bit 27] Enable C3 Undemotion (R/W).\r
    ///\r
    UINT32    C3Undemotion       : 1;\r
    ///\r
    /// [Bit 28] Enable C1 Undemotion (R/W).\r
    ///\r
    UINT32    C1Undemotion       : 1;\r
    ///\r
    /// [Bit 29] Enable Package C-State Auto-demotion (R/W).\r
    ///\r
    UINT32    CStateAutoDemotion : 1;\r
    ///\r
    /// [Bit 30] Enable Package C-State Undemotion (R/W).\r
    ///\r
    UINT32    CStateUndemotion   : 1;\r
    UINT32    Reserved4          : 1;\r
    UINT32    Reserved5          : 32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
/**\r
  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
  RW if MSR_PLATFORM_INFO.[28] = 1.\r
\r
  @param  ECX  MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);\r
  @endcode\r
  @note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
#define MSR_BROADWELL_TURBO_RATIO_LIMIT  0x000001AD\r
\r
/**\r
  MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
    /// limit of 1 core active.\r
    ///\r
    UINT32    Maximum1C : 8;\r
    ///\r
    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
    /// limit of 2 core active.\r
    ///\r
    UINT32    Maximum2C : 8;\r
    ///\r
    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
    /// limit of 3 core active.\r
    ///\r
    UINT32    Maximum3C : 8;\r
    ///\r
    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
    /// limit of 4 core active.\r
    ///\r
    UINT32    Maximum4C : 8;\r
    ///\r
    /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
    /// limit of 5core active.\r
    ///\r
    UINT32    Maximum5C : 8;\r
    ///\r
    /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
    /// limit of 6core active.\r
    ///\r
    UINT32    Maximum6C : 8;\r
    UINT32    Reserved  : 16;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;\r
\r
/**\r
  Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
  fields represent the widest possible range of uncore frequencies. Writing to\r
  these fields allows software to control the minimum and the maximum\r
  frequency that hardware will select.\r
\r
  @param  ECX  MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT);\r
  AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
  @endcode\r
**/\r
#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT  0x00000620\r
\r
/**\r
  MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
    /// LLC/Ring.\r
    ///\r
    UINT32    MAX_RATIO : 7;\r
    UINT32    Reserved2 : 1;\r
    ///\r
    /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
    /// possible ratio of the LLC/Ring.\r
    ///\r
    UINT32    MIN_RATIO : 7;\r
    UINT32    Reserved3 : 17;\r
    UINT32    Reserved4 : 32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
\r
/**\r
  Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL\r
  Domains.".\r
\r
  @param  ECX  MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);\r
  @endcode\r
  @note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
#define MSR_BROADWELL_PP0_ENERGY_STATUS  0x00000639\r
\r
#endif\r
Commit	Line	Data
d57201c0 MK	1	/** @file\r
	2	MSR Definitions for Intel processors based on the Broadwell microarchitecture.\r
	3	\r
	4	Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
	5	are provided for MSRs that contain one or more bit fields. If the MSR value\r
	6	returned is a single 32-bit or 64-bit value, then a data structure is not\r
	7	provided for that MSR.\r
	8	\r
e057908f	9	Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
0acd8697	10	SPDX-License-Identifier: BSD-2-Clause-Patent\r
d57201c0 MK	11	\r
d57201c0 MK	12	@par Specification Reference:\r
ba1a2d11 ED	13	Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
ba1a2d11 ED	14	May 2018, Volume 4: Model-Specific-Registers (MSR)\r
d57201c0 MK	15	\r
	16	**/\r
	17	\r
	18	#ifndef __BROADWELL_MSR_H__\r
	19	#define __BROADWELL_MSR_H__\r
	20	\r
e057908f	21	#include <Register/Intel/ArchitecturalMsr.h>\r
d57201c0	22	\r
f4c982bf JF	23	/**\r
	24	Is Intel processors based on the Broadwell microarchitecture?\r
	25	\r
	26	@param DisplayFamily Display Family ID\r
	27	@param DisplayModel Display Model ID\r
	28	\r
	29	@retval TRUE Yes, it is.\r
	30	@retval FALSE No, it isn't.\r
	31	**/\r
	32	#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \\r
	33	(DisplayFamily == 0x06 && \\r
	34	( \\r
	35	DisplayModel == 0x3D \|\| \\r
	36	DisplayModel == 0x47 \|\| \\r
	37	DisplayModel == 0x4F \|\| \\r
	38	DisplayModel == 0x56 \\r
	39	) \\r
	40	)\r
	41	\r
d57201c0	42	/**\r
ba1a2d11	43	Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control\r
d57201c0 MK	44	Facilities.".\r
d57201c0 MK	45	\r
0f16be6d	46	@param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
d57201c0	47	@param EAX Lower 32-bits of MSR value.\r
0f16be6d	48	Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
d57201c0	49	@param EDX Upper 32-bits of MSR value.\r
0f16be6d	50	Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
d57201c0 MK	51	\r
	52	<b>Example usage</b>\r
	53	@code\r
0f16be6d	54	MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r
d57201c0	55	\r
0f16be6d HW	56	Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);\r
0f16be6d HW	57	AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r
d57201c0	58	@endcode\r
0f16be6d	59	@note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
d57201c0	60	**/\r
2f88bd3a	61	#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
d57201c0 MK	62	\r
d57201c0 MK	63	/**\r
0f16be6d	64	MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS\r
d57201c0 MK	65	**/\r
	66	typedef union {\r
	67	///\r
	68	/// Individual bit fields\r
	69	///\r
	70	struct {\r
	71	///\r
	72	/// [Bit 0] Ovf_PMC0.\r
	73	///\r
2f88bd3a	74	UINT32 Ovf_PMC0 : 1;\r
d57201c0 MK	75	///\r
	76	/// [Bit 1] Ovf_PMC1.\r
	77	///\r
2f88bd3a	78	UINT32 Ovf_PMC1 : 1;\r
d57201c0 MK	79	///\r
	80	/// [Bit 2] Ovf_PMC2.\r
	81	///\r
2f88bd3a	82	UINT32 Ovf_PMC2 : 1;\r
d57201c0 MK	83	///\r
	84	/// [Bit 3] Ovf_PMC3.\r
	85	///\r
2f88bd3a MK	86	UINT32 Ovf_PMC3 : 1;\r
2f88bd3a MK	87	UINT32 Reserved1 : 28;\r
d57201c0 MK	88	///\r
	89	/// [Bit 32] Ovf_FixedCtr0.\r
	90	///\r
2f88bd3a	91	UINT32 Ovf_FixedCtr0 : 1;\r
d57201c0 MK	92	///\r
	93	/// [Bit 33] Ovf_FixedCtr1.\r
	94	///\r
2f88bd3a	95	UINT32 Ovf_FixedCtr1 : 1;\r
d57201c0 MK	96	///\r
	97	/// [Bit 34] Ovf_FixedCtr2.\r
	98	///\r
2f88bd3a MK	99	UINT32 Ovf_FixedCtr2 : 1;\r
2f88bd3a MK	100	UINT32 Reserved2 : 20;\r
d57201c0	101	///\r
0f16be6d	102	/// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical\r
d57201c0 MK	103	/// Addresses (ToPA).".\r
d57201c0 MK	104	///\r
2f88bd3a MK	105	UINT32 Trace_ToPA_PMI : 1;\r
2f88bd3a MK	106	UINT32 Reserved3 : 5;\r
d57201c0 MK	107	///\r
	108	/// [Bit 61] Ovf_Uncore.\r
	109	///\r
2f88bd3a	110	UINT32 Ovf_Uncore : 1;\r
d57201c0 MK	111	///\r
	112	/// [Bit 62] Ovf_BufDSSAVE.\r
	113	///\r
2f88bd3a	114	UINT32 OvfBuf : 1;\r
d57201c0 MK	115	///\r
	116	/// [Bit 63] CondChgd.\r
	117	///\r
2f88bd3a	118	UINT32 CondChgd : 1;\r
d57201c0 MK	119	} Bits;\r
	120	///\r
	121	/// All bit fields as a 64-bit value\r
	122	///\r
2f88bd3a	123	UINT64 Uint64;\r
0f16be6d	124	} MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
d57201c0	125	\r
d57201c0 MK	126	/**\r
	127	Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
	128	specific C-state code names, unrelated to MWAIT extension C-state parameters\r
	129	or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
	130	\r
	131	@param ECX MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
	132	@param EAX Lower 32-bits of MSR value.\r
	133	Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
	134	@param EDX Upper 32-bits of MSR value.\r
	135	Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
	136	\r
	137	<b>Example usage</b>\r
	138	@code\r
	139	MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
	140	\r
	141	Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);\r
	142	AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
	143	@endcode\r
a6b7bc3c	144	@note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
d57201c0	145	**/\r
2f88bd3a	146	#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r
d57201c0 MK	147	\r
	148	/**\r
	149	MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL\r
	150	**/\r
	151	typedef union {\r
	152	///\r
	153	/// Individual bit fields\r
	154	///\r
	155	struct {\r
	156	///\r
	157	/// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r
	158	/// processor-specific C-state code name (consuming the least power) for\r
	159	/// the package. The default is set as factory-configured package C-state\r
	160	/// limit. The following C-state code name encodings are supported: 0000b:\r
	161	/// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6\r
	162	/// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.\r
	163	///\r
2f88bd3a MK	164	UINT32 Limit : 4;\r
2f88bd3a MK	165	UINT32 Reserved1 : 6;\r
d57201c0 MK	166	///\r
	167	/// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
	168	///\r
2f88bd3a MK	169	UINT32 IO_MWAIT : 1;\r
2f88bd3a MK	170	UINT32 Reserved2 : 4;\r
d57201c0 MK	171	///\r
	172	/// [Bit 15] CFG Lock (R/WO).\r
	173	///\r
2f88bd3a MK	174	UINT32 CFGLock : 1;\r
2f88bd3a MK	175	UINT32 Reserved3 : 9;\r
d57201c0 MK	176	///\r
	177	/// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
	178	///\r
2f88bd3a	179	UINT32 C3AutoDemotion : 1;\r
d57201c0 MK	180	///\r
	181	/// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
	182	///\r
2f88bd3a	183	UINT32 C1AutoDemotion : 1;\r
d57201c0 MK	184	///\r
	185	/// [Bit 27] Enable C3 Undemotion (R/W).\r
	186	///\r
2f88bd3a	187	UINT32 C3Undemotion : 1;\r
d57201c0 MK	188	///\r
	189	/// [Bit 28] Enable C1 Undemotion (R/W).\r
	190	///\r
2f88bd3a	191	UINT32 C1Undemotion : 1;\r
d57201c0 MK	192	///\r
	193	/// [Bit 29] Enable Package C-State Auto-demotion (R/W).\r
	194	///\r
2f88bd3a	195	UINT32 CStateAutoDemotion : 1;\r
d57201c0 MK	196	///\r
	197	/// [Bit 30] Enable Package C-State Undemotion (R/W).\r
	198	///\r
2f88bd3a MK	199	UINT32 CStateUndemotion : 1;\r
	200	UINT32 Reserved4 : 1;\r
	201	UINT32 Reserved5 : 32;\r
d57201c0 MK	202	} Bits;\r
	203	///\r
	204	/// All bit fields as a 32-bit value\r
	205	///\r
2f88bd3a	206	UINT32 Uint32;\r
d57201c0 MK	207	///\r
	208	/// All bit fields as a 64-bit value\r
	209	///\r
2f88bd3a	210	UINT64 Uint64;\r
d57201c0 MK	211	} MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;\r
d57201c0 MK	212	\r
d57201c0 MK	213	/**\r
	214	Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
	215	RW if MSR_PLATFORM_INFO.[28] = 1.\r
	216	\r
	217	@param ECX MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)\r
	218	@param EAX Lower 32-bits of MSR value.\r
	219	Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r
	220	@param EDX Upper 32-bits of MSR value.\r
	221	Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r
	222	\r
	223	<b>Example usage</b>\r
	224	@code\r
	225	MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER Msr;\r
	226	\r
	227	Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);\r
	228	@endcode\r
a6b7bc3c	229	@note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
d57201c0	230	**/\r
2f88bd3a	231	#define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD\r
d57201c0 MK	232	\r
	233	/**\r
	234	MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT\r
	235	**/\r
	236	typedef union {\r
	237	///\r
	238	/// Individual bit fields\r
	239	///\r
	240	struct {\r
	241	///\r
	242	/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
	243	/// limit of 1 core active.\r
	244	///\r
2f88bd3a	245	UINT32 Maximum1C : 8;\r
d57201c0 MK	246	///\r
	247	/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
	248	/// limit of 2 core active.\r
	249	///\r
2f88bd3a	250	UINT32 Maximum2C : 8;\r
d57201c0 MK	251	///\r
	252	/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
	253	/// limit of 3 core active.\r
	254	///\r
2f88bd3a	255	UINT32 Maximum3C : 8;\r
d57201c0 MK	256	///\r
	257	/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
	258	/// limit of 4 core active.\r
	259	///\r
2f88bd3a	260	UINT32 Maximum4C : 8;\r
d57201c0 MK	261	///\r
	262	/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
	263	/// limit of 5core active.\r
	264	///\r
2f88bd3a	265	UINT32 Maximum5C : 8;\r
d57201c0 MK	266	///\r
	267	/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
	268	/// limit of 6core active.\r
	269	///\r
2f88bd3a MK	270	UINT32 Maximum6C : 8;\r
2f88bd3a MK	271	UINT32 Reserved : 16;\r
d57201c0 MK	272	} Bits;\r
	273	///\r
	274	/// All bit fields as a 64-bit value\r
	275	///\r
2f88bd3a	276	UINT64 Uint64;\r
d57201c0 MK	277	} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;\r
d57201c0 MK	278	\r
c4b07363 ED	279	/**\r
	280	Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
	281	fields represent the widest possible range of uncore frequencies. Writing to\r
	282	these fields allows software to control the minimum and the maximum\r
	283	frequency that hardware will select.\r
	284	\r
	285	@param ECX MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
	286	@param EAX Lower 32-bits of MSR value.\r
	287	Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
	288	@param EDX Upper 32-bits of MSR value.\r
	289	Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
	290	\r
	291	<b>Example usage</b>\r
	292	@code\r
	293	MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
	294	\r
	295	Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT);\r
	296	AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
	297	@endcode\r
	298	**/\r
2f88bd3a	299	#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT 0x00000620\r
c4b07363 ED	300	\r
	301	/**\r
	302	MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT\r
	303	**/\r
	304	typedef union {\r
	305	///\r
	306	/// Individual bit fields\r
	307	///\r
	308	struct {\r
	309	///\r
	310	/// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
	311	/// LLC/Ring.\r
	312	///\r
2f88bd3a MK	313	UINT32 MAX_RATIO : 7;\r
2f88bd3a MK	314	UINT32 Reserved2 : 1;\r
c4b07363 ED	315	///\r
	316	/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
	317	/// possible ratio of the LLC/Ring.\r
	318	///\r
2f88bd3a MK	319	UINT32 MIN_RATIO : 7;\r
	320	UINT32 Reserved3 : 17;\r
	321	UINT32 Reserved4 : 32;\r
c4b07363 ED	322	} Bits;\r
	323	///\r
	324	/// All bit fields as a 32-bit value\r
	325	///\r
2f88bd3a	326	UINT32 Uint32;\r
c4b07363 ED	327	///\r
	328	/// All bit fields as a 64-bit value\r
	329	///\r
2f88bd3a	330	UINT64 Uint64;\r
c4b07363 ED	331	} MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
c4b07363 ED	332	\r
0f16be6d HW	333	/**\r
	334	Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
	335	Domains.".\r
	336	\r
	337	@param ECX MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)\r
	338	@param EAX Lower 32-bits of MSR value.\r
	339	@param EDX Upper 32-bits of MSR value.\r
	340	\r
	341	<b>Example usage</b>\r
	342	@code\r
	343	UINT64 Msr;\r
	344	\r
	345	Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);\r
	346	@endcode\r
	347	@note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
	348	**/\r
2f88bd3a	349	#define MSR_BROADWELL_PP0_ENERGY_STATUS 0x00000639\r
0f16be6d	350	\r
d57201c0	351	#endif\r