projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| c67b579c MK |
1 | /** @file\r |
| 2 | MSR Definitions for Intel processors based on the Haswell-E microarchitecture.\r | |
| 3 | \r | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
| 7 | provided for that MSR.\r | |
| 8 | \r | |
| e057908f | 9 | Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r |
| 0acd8697 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| c67b579c MK |
11 | \r |
| 12 | @par Specification Reference:\r | |
| ba1a2d11 ED |
13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r |
| 14 | May 2018, Volume 4: Model-Specific-Registers (MSR)\r | |
| c67b579c MK |
15 | \r |
| 16 | **/\r | |
| 17 | \r | |
| 18 | #ifndef __HASWELL_E_MSR_H__\r | |
| 19 | #define __HASWELL_E_MSR_H__\r | |
| 20 | \r | |
| e057908f | 21 | #include <Register/Intel/ArchitecturalMsr.h>\r |
| c67b579c | 22 | \r |
| f4c982bf JF |
23 | /**\r |
| 24 | Is Intel processors based on the Haswell-E microarchitecture?\r | |
| 25 | \r | |
| 26 | @param DisplayFamily Display Family ID\r | |
| 27 | @param DisplayModel Display Model ID\r | |
| 28 | \r | |
| 29 | @retval TRUE Yes, it is.\r | |
| 30 | @retval FALSE No, it isn't.\r | |
| 31 | **/\r | |
| 32 | #define IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
| 33 | (DisplayFamily == 0x06 && \\r | |
| 34 | ( \\r | |
| 35 | DisplayModel == 0x3F \\r | |
| 36 | ) \\r | |
| 37 | )\r | |
| 38 | \r | |
| 0f16be6d HW |
39 | /**\r |
| 40 | Package. Configured State of Enabled Processor Core Count and Logical\r | |
| 41 | Processor Count (RO) - After a Power-On RESET, enumerates factory\r | |
| 42 | configuration of the number of processor cores and logical processors in the\r | |
| 43 | physical package. - Following the sequence of (i) BIOS modified a\r | |
| 44 | Configuration Mask which selects a subset of processor cores to be active\r | |
| 45 | post RESET and (ii) a RESET event after the modification, enumerates the\r | |
| 46 | current configuration of enabled processor core count and logical processor\r | |
| 47 | count in the physical package.\r | |
| 48 | \r | |
| 49 | @param ECX MSR_HASWELL_E_CORE_THREAD_COUNT (0x00000035)\r | |
| 50 | @param EAX Lower 32-bits of MSR value.\r | |
| 51 | Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.\r | |
| 52 | @param EDX Upper 32-bits of MSR value.\r | |
| 53 | Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.\r | |
| 54 | \r | |
| 55 | <b>Example usage</b>\r | |
| 56 | @code\r | |
| 57 | MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER Msr;\r | |
| 58 | \r | |
| 59 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_THREAD_COUNT);\r | |
| 60 | @endcode\r | |
| 61 | @note MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM.\r | |
| 62 | **/\r | |
| 2f88bd3a | 63 | #define MSR_HASWELL_E_CORE_THREAD_COUNT 0x00000035\r |
| 0f16be6d HW |
64 | \r |
| 65 | /**\r | |
| 66 | MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT\r | |
| 67 | **/\r | |
| 68 | typedef union {\r | |
| 69 | ///\r | |
| 70 | /// Individual bit fields\r | |
| 71 | ///\r | |
| 72 | struct {\r | |
| 73 | ///\r | |
| 74 | /// [Bits 15:0] Core_COUNT (RO) The number of processor cores that are\r | |
| 75 | /// currently enabled (by either factory configuration or BIOS\r | |
| 76 | /// configuration) in the physical package.\r | |
| 77 | ///\r | |
| 2f88bd3a | 78 | UINT32 Core_Count : 16;\r |
| 0f16be6d HW |
79 | ///\r |
| 80 | /// [Bits 31:16] THREAD_COUNT (RO) The number of logical processors that\r | |
| 81 | /// are currently enabled (by either factory configuration or BIOS\r | |
| 82 | /// configuration) in the physical package.\r | |
| 83 | ///\r | |
| 2f88bd3a MK |
84 | UINT32 Thread_Count : 16;\r |
| 85 | UINT32 Reserved : 32;\r | |
| 0f16be6d HW |
86 | } Bits;\r |
| 87 | ///\r | |
| 88 | /// All bit fields as a 32-bit value\r | |
| 89 | ///\r | |
| 2f88bd3a | 90 | UINT32 Uint32;\r |
| 0f16be6d HW |
91 | ///\r |
| 92 | /// All bit fields as a 64-bit value\r | |
| 93 | ///\r | |
| 2f88bd3a | 94 | UINT64 Uint64;\r |
| 0f16be6d HW |
95 | } MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER;\r |
| 96 | \r | |
| 0f16be6d HW |
97 | /**\r |
| 98 | Thread. A Hardware Assigned ID for the Logical Processor (RO).\r | |
| 99 | \r | |
| 100 | @param ECX MSR_HASWELL_E_THREAD_ID_INFO (0x00000053)\r | |
| 101 | @param EAX Lower 32-bits of MSR value.\r | |
| 102 | Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.\r | |
| 103 | @param EDX Upper 32-bits of MSR value.\r | |
| 104 | Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.\r | |
| 105 | \r | |
| 106 | <b>Example usage</b>\r | |
| 107 | @code\r | |
| 108 | MSR_HASWELL_E_THREAD_ID_INFO_REGISTER Msr;\r | |
| 109 | \r | |
| 110 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_THREAD_ID_INFO);\r | |
| 111 | @endcode\r | |
| 112 | @note MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM.\r | |
| 113 | **/\r | |
| 2f88bd3a | 114 | #define MSR_HASWELL_E_THREAD_ID_INFO 0x00000053\r |
| 0f16be6d HW |
115 | \r |
| 116 | /**\r | |
| 117 | MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO\r | |
| 118 | **/\r | |
| 119 | typedef union {\r | |
| 120 | ///\r | |
| 121 | /// Individual bit fields\r | |
| 122 | ///\r | |
| 123 | struct {\r | |
| 124 | ///\r | |
| 125 | /// [Bits 7:0] Logical_Processor_ID (RO) An implementation-specific\r | |
| 126 | /// numerical. value physically assigned to each logical processor. This\r | |
| 127 | /// ID is not related to Initial APIC ID or x2APIC ID, it is unique within\r | |
| 128 | /// a physical package.\r | |
| 129 | ///\r | |
| 2f88bd3a MK |
130 | UINT32 Logical_Processor_ID : 8;\r |
| 131 | UINT32 Reserved1 : 24;\r | |
| 132 | UINT32 Reserved2 : 32;\r | |
| 0f16be6d HW |
133 | } Bits;\r |
| 134 | ///\r | |
| 135 | /// All bit fields as a 32-bit value\r | |
| 136 | ///\r | |
| 2f88bd3a | 137 | UINT32 Uint32;\r |
| 0f16be6d HW |
138 | ///\r |
| 139 | /// All bit fields as a 64-bit value\r | |
| 140 | ///\r | |
| 2f88bd3a | 141 | UINT64 Uint64;\r |
| 0f16be6d HW |
142 | } MSR_HASWELL_E_THREAD_ID_INFO_REGISTER;\r |
| 143 | \r | |
| c67b579c MK |
144 | /**\r |
| 145 | Core. C-State Configuration Control (R/W) Note: C-state values are processor\r | |
| 146 | specific C-state code names, unrelated to MWAIT extension C-state parameters\r | |
| 147 | or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r | |
| 148 | \r | |
| 149 | @param ECX MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL (0x000000E2)\r | |
| 150 | @param EAX Lower 32-bits of MSR value.\r | |
| 151 | Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 152 | @param EDX Upper 32-bits of MSR value.\r | |
| 153 | Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 154 | \r | |
| 155 | <b>Example usage</b>\r | |
| 156 | @code\r | |
| 157 | MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r | |
| 158 | \r | |
| 159 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL);\r | |
| 160 | AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r | |
| 161 | @endcode\r | |
| a73ab083 | 162 | @note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r |
| c67b579c | 163 | **/\r |
| 2f88bd3a | 164 | #define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2\r |
| c67b579c MK |
165 | \r |
| 166 | /**\r | |
| 167 | MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL\r | |
| 168 | **/\r | |
| 169 | typedef union {\r | |
| 170 | ///\r | |
| 171 | /// Individual bit fields\r | |
| 172 | ///\r | |
| 173 | struct {\r | |
| 174 | ///\r | |
| 175 | /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r | |
| 176 | /// processor-specific C-state code name (consuming the least power) for\r | |
| 177 | /// the package. The default is set as factory-configured package C-state\r | |
| 178 | /// limit. The following C-state code name encodings are supported: 000b:\r | |
| 179 | /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)\r | |
| 180 | /// 011b: C6 (retention) 111b: No Package C state limits. All C states\r | |
| 181 | /// supported by the processor are available.\r | |
| 182 | ///\r | |
| 2f88bd3a MK |
183 | UINT32 Limit : 3;\r |
| 184 | UINT32 Reserved1 : 7;\r | |
| c67b579c MK |
185 | ///\r |
| 186 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r | |
| 187 | ///\r | |
| 2f88bd3a MK |
188 | UINT32 IO_MWAIT : 1;\r |
| 189 | UINT32 Reserved2 : 4;\r | |
| c67b579c MK |
190 | ///\r |
| 191 | /// [Bit 15] CFG Lock (R/WO).\r | |
| 192 | ///\r | |
| 2f88bd3a MK |
193 | UINT32 CFGLock : 1;\r |
| 194 | UINT32 Reserved3 : 9;\r | |
| c67b579c MK |
195 | ///\r |
| 196 | /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r | |
| 197 | ///\r | |
| 2f88bd3a | 198 | UINT32 C3AutoDemotion : 1;\r |
| c67b579c MK |
199 | ///\r |
| 200 | /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r | |
| 201 | ///\r | |
| 2f88bd3a | 202 | UINT32 C1AutoDemotion : 1;\r |
| c67b579c MK |
203 | ///\r |
| 204 | /// [Bit 27] Enable C3 Undemotion (R/W).\r | |
| 205 | ///\r | |
| 2f88bd3a | 206 | UINT32 C3Undemotion : 1;\r |
| c67b579c MK |
207 | ///\r |
| 208 | /// [Bit 28] Enable C1 Undemotion (R/W).\r | |
| 209 | ///\r | |
| 2f88bd3a | 210 | UINT32 C1Undemotion : 1;\r |
| c67b579c MK |
211 | ///\r |
| 212 | /// [Bit 29] Package C State Demotion Enable (R/W).\r | |
| 213 | ///\r | |
| 2f88bd3a | 214 | UINT32 CStateDemotion : 1;\r |
| c67b579c MK |
215 | ///\r |
| 216 | /// [Bit 30] Package C State UnDemotion Enable (R/W).\r | |
| 217 | ///\r | |
| 2f88bd3a MK |
218 | UINT32 CStateUndemotion : 1;\r |
| 219 | UINT32 Reserved4 : 1;\r | |
| 220 | UINT32 Reserved5 : 32;\r | |
| c67b579c MK |
221 | } Bits;\r |
| 222 | ///\r | |
| 223 | /// All bit fields as a 32-bit value\r | |
| 224 | ///\r | |
| 2f88bd3a | 225 | UINT32 Uint32;\r |
| c67b579c MK |
226 | ///\r |
| 227 | /// All bit fields as a 64-bit value\r | |
| 228 | ///\r | |
| 2f88bd3a | 229 | UINT64 Uint64;\r |
| c67b579c MK |
230 | } MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER;\r |
| 231 | \r | |
| c67b579c MK |
232 | /**\r |
| 233 | Thread. Global Machine Check Capability (R/O).\r | |
| 234 | \r | |
| 235 | @param ECX MSR_HASWELL_E_IA32_MCG_CAP (0x00000179)\r | |
| 236 | @param EAX Lower 32-bits of MSR value.\r | |
| 237 | Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.\r | |
| 238 | @param EDX Upper 32-bits of MSR value.\r | |
| 239 | Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.\r | |
| 240 | \r | |
| 241 | <b>Example usage</b>\r | |
| 242 | @code\r | |
| 243 | MSR_HASWELL_E_IA32_MCG_CAP_REGISTER Msr;\r | |
| 244 | \r | |
| 245 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP);\r | |
| 246 | @endcode\r | |
| a73ab083 | 247 | @note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r |
| c67b579c | 248 | **/\r |
| 2f88bd3a | 249 | #define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179\r |
| c67b579c MK |
250 | \r |
| 251 | /**\r | |
| 252 | MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP\r | |
| 253 | **/\r | |
| 254 | typedef union {\r | |
| 255 | ///\r | |
| 256 | /// Individual bit fields\r | |
| 257 | ///\r | |
| 258 | struct {\r | |
| 259 | ///\r | |
| 260 | /// [Bits 7:0] Count.\r | |
| 261 | ///\r | |
| 2f88bd3a | 262 | UINT32 Count : 8;\r |
| c67b579c MK |
263 | ///\r |
| 264 | /// [Bit 8] MCG_CTL_P.\r | |
| 265 | ///\r | |
| 2f88bd3a | 266 | UINT32 MCG_CTL_P : 1;\r |
| c67b579c MK |
267 | ///\r |
| 268 | /// [Bit 9] MCG_EXT_P.\r | |
| 269 | ///\r | |
| 2f88bd3a | 270 | UINT32 MCG_EXT_P : 1;\r |
| c67b579c MK |
271 | ///\r |
| 272 | /// [Bit 10] MCP_CMCI_P.\r | |
| 273 | ///\r | |
| 2f88bd3a | 274 | UINT32 MCP_CMCI_P : 1;\r |
| c67b579c MK |
275 | ///\r |
| 276 | /// [Bit 11] MCG_TES_P.\r | |
| 277 | ///\r | |
| 2f88bd3a MK |
278 | UINT32 MCG_TES_P : 1;\r |
| 279 | UINT32 Reserved1 : 4;\r | |
| c67b579c MK |
280 | ///\r |
| 281 | /// [Bits 23:16] MCG_EXT_CNT.\r | |
| 282 | ///\r | |
| 2f88bd3a | 283 | UINT32 MCG_EXT_CNT : 8;\r |
| c67b579c MK |
284 | ///\r |
| 285 | /// [Bit 24] MCG_SER_P.\r | |
| 286 | ///\r | |
| 2f88bd3a | 287 | UINT32 MCG_SER_P : 1;\r |
| c67b579c MK |
288 | ///\r |
| 289 | /// [Bit 25] MCG_EM_P.\r | |
| 290 | ///\r | |
| 2f88bd3a | 291 | UINT32 MCG_EM_P : 1;\r |
| c67b579c MK |
292 | ///\r |
| 293 | /// [Bit 26] MCG_ELOG_P.\r | |
| 294 | ///\r | |
| 2f88bd3a MK |
295 | UINT32 MCG_ELOG_P : 1;\r |
| 296 | UINT32 Reserved2 : 5;\r | |
| 297 | UINT32 Reserved3 : 32;\r | |
| c67b579c MK |
298 | } Bits;\r |
| 299 | ///\r | |
| 300 | /// All bit fields as a 32-bit value\r | |
| 301 | ///\r | |
| 2f88bd3a | 302 | UINT32 Uint32;\r |
| c67b579c MK |
303 | ///\r |
| 304 | /// All bit fields as a 64-bit value\r | |
| 305 | ///\r | |
| 2f88bd3a | 306 | UINT64 Uint64;\r |
| c67b579c MK |
307 | } MSR_HASWELL_E_IA32_MCG_CAP_REGISTER;\r |
| 308 | \r | |
| c67b579c MK |
309 | /**\r |
| 310 | THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r | |
| 311 | Enhancement. Accessible only while in SMM.\r | |
| 312 | \r | |
| 313 | @param ECX MSR_HASWELL_E_SMM_MCA_CAP (0x0000017D)\r | |
| 314 | @param EAX Lower 32-bits of MSR value.\r | |
| 315 | Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.\r | |
| 316 | @param EDX Upper 32-bits of MSR value.\r | |
| 317 | Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.\r | |
| 318 | \r | |
| 319 | <b>Example usage</b>\r | |
| 320 | @code\r | |
| 321 | MSR_HASWELL_E_SMM_MCA_CAP_REGISTER Msr;\r | |
| 322 | \r | |
| 323 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP);\r | |
| 324 | AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64);\r | |
| 325 | @endcode\r | |
| a73ab083 | 326 | @note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r |
| c67b579c | 327 | **/\r |
| 2f88bd3a | 328 | #define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D\r |
| c67b579c MK |
329 | \r |
| 330 | /**\r | |
| 331 | MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP\r | |
| 332 | **/\r | |
| 333 | typedef union {\r | |
| 334 | ///\r | |
| 335 | /// Individual bit fields\r | |
| 336 | ///\r | |
| 337 | struct {\r | |
| 2f88bd3a MK |
338 | UINT32 Reserved1 : 32;\r |
| 339 | UINT32 Reserved2 : 26;\r | |
| c67b579c MK |
340 | ///\r |
| 341 | /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r | |
| 342 | /// SMM code access restriction is supported and a host-space interface\r | |
| 343 | /// available to SMM handler.\r | |
| 344 | ///\r | |
| 2f88bd3a | 345 | UINT32 SMM_Code_Access_Chk : 1;\r |
| c67b579c MK |
346 | ///\r |
| 347 | /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r | |
| 348 | /// SMM long flow indicator is supported and a host-space interface\r | |
| 349 | /// available to SMM handler.\r | |
| 350 | ///\r | |
| 2f88bd3a MK |
351 | UINT32 Long_Flow_Indication : 1;\r |
| 352 | UINT32 Reserved3 : 4;\r | |
| c67b579c MK |
353 | } Bits;\r |
| 354 | ///\r | |
| 355 | /// All bit fields as a 64-bit value\r | |
| 356 | ///\r | |
| 2f88bd3a | 357 | UINT64 Uint64;\r |
| c67b579c MK |
358 | } MSR_HASWELL_E_SMM_MCA_CAP_REGISTER;\r |
| 359 | \r | |
| c67b579c MK |
360 | /**\r |
| 361 | Package. MC Bank Error Configuration (R/W).\r | |
| 362 | \r | |
| 363 | @param ECX MSR_HASWELL_E_ERROR_CONTROL (0x0000017F)\r | |
| 364 | @param EAX Lower 32-bits of MSR value.\r | |
| 365 | Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.\r | |
| 366 | @param EDX Upper 32-bits of MSR value.\r | |
| 367 | Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.\r | |
| 368 | \r | |
| 369 | <b>Example usage</b>\r | |
| 370 | @code\r | |
| 371 | MSR_HASWELL_E_ERROR_CONTROL_REGISTER Msr;\r | |
| 372 | \r | |
| 373 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL);\r | |
| 374 | AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64);\r | |
| 375 | @endcode\r | |
| a73ab083 | 376 | @note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r |
| c67b579c | 377 | **/\r |
| 2f88bd3a | 378 | #define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F\r |
| c67b579c MK |
379 | \r |
| 380 | /**\r | |
| 381 | MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL\r | |
| 382 | **/\r | |
| 383 | typedef union {\r | |
| 384 | ///\r | |
| 385 | /// Individual bit fields\r | |
| 386 | ///\r | |
| 387 | struct {\r | |
| 2f88bd3a | 388 | UINT32 Reserved1 : 1;\r |
| c67b579c MK |
389 | ///\r |
| 390 | /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r | |
| 391 | /// to log additional info in bits 36:32.\r | |
| 392 | ///\r | |
| 2f88bd3a MK |
393 | UINT32 MemErrorLogEnable : 1;\r |
| 394 | UINT32 Reserved2 : 30;\r | |
| 395 | UINT32 Reserved3 : 32;\r | |
| c67b579c MK |
396 | } Bits;\r |
| 397 | ///\r | |
| 398 | /// All bit fields as a 32-bit value\r | |
| 399 | ///\r | |
| 2f88bd3a | 400 | UINT32 Uint32;\r |
| c67b579c MK |
401 | ///\r |
| 402 | /// All bit fields as a 64-bit value\r | |
| 403 | ///\r | |
| 2f88bd3a | 404 | UINT64 Uint64;\r |
| c67b579c MK |
405 | } MSR_HASWELL_E_ERROR_CONTROL_REGISTER;\r |
| 406 | \r | |
| c67b579c MK |
407 | /**\r |
| 408 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r | |
| 409 | RW if MSR_PLATFORM_INFO.[28] = 1.\r | |
| 410 | \r | |
| 411 | @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT (0x000001AD)\r | |
| 412 | @param EAX Lower 32-bits of MSR value.\r | |
| 413 | Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.\r | |
| 414 | @param EDX Upper 32-bits of MSR value.\r | |
| 415 | Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.\r | |
| 416 | \r | |
| 417 | <b>Example usage</b>\r | |
| 418 | @code\r | |
| 419 | MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER Msr;\r | |
| 420 | \r | |
| 421 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT);\r | |
| 422 | @endcode\r | |
| a73ab083 | 423 | @note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r |
| c67b579c | 424 | **/\r |
| 2f88bd3a | 425 | #define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD\r |
| c67b579c MK |
426 | \r |
| 427 | /**\r | |
| 428 | MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT\r | |
| 429 | **/\r | |
| 430 | typedef union {\r | |
| 431 | ///\r | |
| 432 | /// Individual bit fields\r | |
| 433 | ///\r | |
| 434 | struct {\r | |
| 435 | ///\r | |
| 436 | /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r | |
| 437 | /// limit of 1 core active.\r | |
| 438 | ///\r | |
| 2f88bd3a | 439 | UINT32 Maximum1C : 8;\r |
| c67b579c MK |
440 | ///\r |
| 441 | /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r | |
| 442 | /// limit of 2 core active.\r | |
| 443 | ///\r | |
| 2f88bd3a | 444 | UINT32 Maximum2C : 8;\r |
| c67b579c MK |
445 | ///\r |
| 446 | /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r | |
| 447 | /// limit of 3 core active.\r | |
| 448 | ///\r | |
| 2f88bd3a | 449 | UINT32 Maximum3C : 8;\r |
| c67b579c MK |
450 | ///\r |
| 451 | /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r | |
| 452 | /// limit of 4 core active.\r | |
| 453 | ///\r | |
| 2f88bd3a | 454 | UINT32 Maximum4C : 8;\r |
| c67b579c MK |
455 | ///\r |
| 456 | /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r | |
| 457 | /// limit of 5 core active.\r | |
| 458 | ///\r | |
| 2f88bd3a | 459 | UINT32 Maximum5C : 8;\r |
| c67b579c MK |
460 | ///\r |
| 461 | /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r | |
| 462 | /// limit of 6 core active.\r | |
| 463 | ///\r | |
| 2f88bd3a | 464 | UINT32 Maximum6C : 8;\r |
| c67b579c MK |
465 | ///\r |
| 466 | /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r | |
| 467 | /// limit of 7 core active.\r | |
| 468 | ///\r | |
| 2f88bd3a | 469 | UINT32 Maximum7C : 8;\r |
| c67b579c MK |
470 | ///\r |
| 471 | /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r | |
| 472 | /// limit of 8 core active.\r | |
| 473 | ///\r | |
| 2f88bd3a | 474 | UINT32 Maximum8C : 8;\r |
| c67b579c MK |
475 | } Bits;\r |
| 476 | ///\r | |
| 477 | /// All bit fields as a 64-bit value\r | |
| 478 | ///\r | |
| 2f88bd3a | 479 | UINT64 Uint64;\r |
| c67b579c MK |
480 | } MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER;\r |
| 481 | \r | |
| c67b579c MK |
482 | /**\r |
| 483 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r | |
| 484 | RW if MSR_PLATFORM_INFO.[28] = 1.\r | |
| 485 | \r | |
| 486 | @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT1 (0x000001AE)\r | |
| 487 | @param EAX Lower 32-bits of MSR value.\r | |
| 488 | Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.\r | |
| 489 | @param EDX Upper 32-bits of MSR value.\r | |
| 490 | Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.\r | |
| 491 | \r | |
| 492 | <b>Example usage</b>\r | |
| 493 | @code\r | |
| 494 | MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER Msr;\r | |
| 495 | \r | |
| 496 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1);\r | |
| 497 | @endcode\r | |
| a73ab083 | 498 | @note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r |
| c67b579c | 499 | **/\r |
| 2f88bd3a | 500 | #define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE\r |
| c67b579c MK |
501 | \r |
| 502 | /**\r | |
| 503 | MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1\r | |
| 504 | **/\r | |
| 505 | typedef union {\r | |
| 506 | ///\r | |
| 507 | /// Individual bit fields\r | |
| 508 | ///\r | |
| 509 | struct {\r | |
| 510 | ///\r | |
| 511 | /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio\r | |
| 512 | /// limit of 9 core active.\r | |
| 513 | ///\r | |
| 2f88bd3a | 514 | UINT32 Maximum9C : 8;\r |
| c67b579c MK |
515 | ///\r |
| 516 | /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio\r | |
| 517 | /// limit of 10 core active.\r | |
| 518 | ///\r | |
| 2f88bd3a | 519 | UINT32 Maximum10C : 8;\r |
| c67b579c MK |
520 | ///\r |
| 521 | /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio\r | |
| 522 | /// limit of 11 core active.\r | |
| 523 | ///\r | |
| 2f88bd3a | 524 | UINT32 Maximum11C : 8;\r |
| c67b579c MK |
525 | ///\r |
| 526 | /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio\r | |
| 527 | /// limit of 12 core active.\r | |
| 528 | ///\r | |
| 2f88bd3a | 529 | UINT32 Maximum12C : 8;\r |
| c67b579c MK |
530 | ///\r |
| 531 | /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio\r | |
| 532 | /// limit of 13 core active.\r | |
| 533 | ///\r | |
| 2f88bd3a | 534 | UINT32 Maximum13C : 8;\r |
| c67b579c MK |
535 | ///\r |
| 536 | /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio\r | |
| 537 | /// limit of 14 core active.\r | |
| 538 | ///\r | |
| 2f88bd3a | 539 | UINT32 Maximum14C : 8;\r |
| c67b579c MK |
540 | ///\r |
| 541 | /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio\r | |
| 542 | /// limit of 15 core active.\r | |
| 543 | ///\r | |
| 2f88bd3a | 544 | UINT32 Maximum15C : 8;\r |
| c67b579c MK |
545 | ///\r |
| 546 | /// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio\r | |
| 547 | /// limit of 16 core active.\r | |
| 548 | ///\r | |
| 2f88bd3a | 549 | UINT32 Maximum16C : 8;\r |
| c67b579c MK |
550 | } Bits;\r |
| 551 | ///\r | |
| 552 | /// All bit fields as a 64-bit value\r | |
| 553 | ///\r | |
| 2f88bd3a | 554 | UINT64 Uint64;\r |
| c67b579c MK |
555 | } MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER;\r |
| 556 | \r | |
| c67b579c MK |
557 | /**\r |
| 558 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r | |
| 559 | RW if MSR_PLATFORM_INFO.[28] = 1.\r | |
| 560 | \r | |
| 561 | @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT2 (0x000001AF)\r | |
| 562 | @param EAX Lower 32-bits of MSR value.\r | |
| 563 | Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.\r | |
| 564 | @param EDX Upper 32-bits of MSR value.\r | |
| 565 | Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.\r | |
| 566 | \r | |
| 567 | <b>Example usage</b>\r | |
| 568 | @code\r | |
| 569 | MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER Msr;\r | |
| 570 | \r | |
| 571 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2);\r | |
| 572 | @endcode\r | |
| a73ab083 | 573 | @note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.\r |
| c67b579c | 574 | **/\r |
| 2f88bd3a | 575 | #define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF\r |
| c67b579c MK |
576 | \r |
| 577 | /**\r | |
| 578 | MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2\r | |
| 579 | **/\r | |
| 580 | typedef union {\r | |
| 581 | ///\r | |
| 582 | /// Individual bit fields\r | |
| 583 | ///\r | |
| 584 | struct {\r | |
| 585 | ///\r | |
| 586 | /// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio\r | |
| 587 | /// limit of 17 core active.\r | |
| 588 | ///\r | |
| 2f88bd3a | 589 | UINT32 Maximum17C : 8;\r |
| c67b579c MK |
590 | ///\r |
| 591 | /// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio\r | |
| 592 | /// limit of 18 core active.\r | |
| 593 | ///\r | |
| 2f88bd3a MK |
594 | UINT32 Maximum18C : 8;\r |
| 595 | UINT32 Reserved1 : 16;\r | |
| 596 | UINT32 Reserved2 : 31;\r | |
| c67b579c MK |
597 | ///\r |
| 598 | /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r | |
| 599 | /// the processor uses override configuration specified in\r | |
| 600 | /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and\r | |
| 601 | /// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set\r | |
| 602 | /// configuration (Default).\r | |
| 603 | ///\r | |
| 2f88bd3a | 604 | UINT32 TurboRatioLimitConfigurationSemaphore : 1;\r |
| c67b579c MK |
605 | } Bits;\r |
| 606 | ///\r | |
| 607 | /// All bit fields as a 64-bit value\r | |
| 608 | ///\r | |
| 2f88bd3a | 609 | UINT64 Uint64;\r |
| c67b579c MK |
610 | } MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER;\r |
| 611 | \r | |
| c67b579c MK |
612 | /**\r |
| 613 | Package. Unit Multipliers used in RAPL Interfaces (R/O).\r | |
| 614 | \r | |
| 615 | @param ECX MSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606)\r | |
| 616 | @param EAX Lower 32-bits of MSR value.\r | |
| 617 | Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.\r | |
| 618 | @param EDX Upper 32-bits of MSR value.\r | |
| 619 | Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.\r | |
| 620 | \r | |
| 621 | <b>Example usage</b>\r | |
| 622 | @code\r | |
| 623 | MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER Msr;\r | |
| 624 | \r | |
| 625 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT);\r | |
| 626 | @endcode\r | |
| a73ab083 | 627 | @note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r |
| c67b579c | 628 | **/\r |
| 2f88bd3a | 629 | #define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606\r |
| c67b579c MK |
630 | \r |
| 631 | /**\r | |
| 632 | MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT\r | |
| 633 | **/\r | |
| 634 | typedef union {\r | |
| 635 | ///\r | |
| 636 | /// Individual bit fields\r | |
| 637 | ///\r | |
| 638 | struct {\r | |
| 639 | ///\r | |
| 640 | /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r | |
| 641 | ///\r | |
| 2f88bd3a MK |
642 | UINT32 PowerUnits : 4;\r |
| 643 | UINT32 Reserved1 : 4;\r | |
| c67b579c MK |
644 | ///\r |
| 645 | /// [Bits 12:8] Package. Energy Status Units Energy related information\r | |
| 646 | /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r | |
| 647 | /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r | |
| 648 | /// micro-joules).\r | |
| 649 | ///\r | |
| 2f88bd3a MK |
650 | UINT32 EnergyStatusUnits : 5;\r |
| 651 | UINT32 Reserved2 : 3;\r | |
| c67b579c MK |
652 | ///\r |
| 653 | /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r | |
| 654 | /// Interfaces.".\r | |
| 655 | ///\r | |
| 2f88bd3a MK |
656 | UINT32 TimeUnits : 4;\r |
| 657 | UINT32 Reserved3 : 12;\r | |
| 658 | UINT32 Reserved4 : 32;\r | |
| c67b579c MK |
659 | } Bits;\r |
| 660 | ///\r | |
| 661 | /// All bit fields as a 32-bit value\r | |
| 662 | ///\r | |
| 2f88bd3a | 663 | UINT32 Uint32;\r |
| c67b579c MK |
664 | ///\r |
| 665 | /// All bit fields as a 64-bit value\r | |
| 666 | ///\r | |
| 2f88bd3a | 667 | UINT64 Uint64;\r |
| c67b579c MK |
668 | } MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER;\r |
| 669 | \r | |
| c67b579c MK |
670 | /**\r |
| 671 | Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r | |
| 672 | Domain.".\r | |
| 673 | \r | |
| 674 | @param ECX MSR_HASWELL_E_DRAM_POWER_LIMIT (0x00000618)\r | |
| 675 | @param EAX Lower 32-bits of MSR value.\r | |
| 676 | @param EDX Upper 32-bits of MSR value.\r | |
| 677 | \r | |
| 678 | <b>Example usage</b>\r | |
| 679 | @code\r | |
| 680 | UINT64 Msr;\r | |
| 681 | \r | |
| 682 | Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT);\r | |
| 683 | AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr);\r | |
| 684 | @endcode\r | |
| a73ab083 | 685 | @note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r |
| c67b579c | 686 | **/\r |
| 2f88bd3a | 687 | #define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618\r |
| c67b579c MK |
688 | \r |
| 689 | /**\r | |
| 0f16be6d | 690 | Package. DRAM Energy Status (R/O) Energy Consumed by DRAM devices.\r |
| c67b579c MK |
691 | \r |
| 692 | @param ECX MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)\r | |
| 693 | @param EAX Lower 32-bits of MSR value.\r | |
| 0f16be6d | 694 | Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.\r |
| c67b579c | 695 | @param EDX Upper 32-bits of MSR value.\r |
| 0f16be6d | 696 | Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.\r |
| c67b579c MK |
697 | \r |
| 698 | <b>Example usage</b>\r | |
| 699 | @code\r | |
| 0f16be6d | 700 | MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER Msr;\r |
| c67b579c | 701 | \r |
| 0f16be6d | 702 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);\r |
| c67b579c | 703 | @endcode\r |
| a73ab083 | 704 | @note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r |
| c67b579c | 705 | **/\r |
| 2f88bd3a | 706 | #define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619\r |
| c67b579c | 707 | \r |
| 0f16be6d HW |
708 | /**\r |
| 709 | MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS\r | |
| 710 | **/\r | |
| 711 | typedef union {\r | |
| 712 | ///\r | |
| 713 | /// Individual bit fields\r | |
| 714 | ///\r | |
| 715 | struct {\r | |
| 716 | ///\r | |
| 717 | /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r | |
| 718 | /// to enable DRAM RAPL mode 0 (Direct VR).\r | |
| 719 | ///\r | |
| 2f88bd3a MK |
720 | UINT32 Energy : 32;\r |
| 721 | UINT32 Reserved : 32;\r | |
| 0f16be6d HW |
722 | } Bits;\r |
| 723 | ///\r | |
| 724 | /// All bit fields as a 32-bit value\r | |
| 725 | ///\r | |
| 2f88bd3a | 726 | UINT32 Uint32;\r |
| 0f16be6d HW |
727 | ///\r |
| 728 | /// All bit fields as a 64-bit value\r | |
| 729 | ///\r | |
| 2f88bd3a | 730 | UINT64 Uint64;\r |
| 0f16be6d HW |
731 | } MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER;\r |
| 732 | \r | |
| c67b579c MK |
733 | /**\r |
| 734 | Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r | |
| 735 | RAPL Domain.".\r | |
| 736 | \r | |
| 737 | @param ECX MSR_HASWELL_E_DRAM_PERF_STATUS (0x0000061B)\r | |
| 738 | @param EAX Lower 32-bits of MSR value.\r | |
| 739 | @param EDX Upper 32-bits of MSR value.\r | |
| 740 | \r | |
| 741 | <b>Example usage</b>\r | |
| 742 | @code\r | |
| 743 | UINT64 Msr;\r | |
| 744 | \r | |
| 745 | Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS);\r | |
| 746 | @endcode\r | |
| a73ab083 | 747 | @note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r |
| c67b579c | 748 | **/\r |
| 2f88bd3a | 749 | #define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B\r |
| c67b579c MK |
750 | \r |
| 751 | /**\r | |
| 752 | Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
| 753 | \r | |
| 754 | @param ECX MSR_HASWELL_E_DRAM_POWER_INFO (0x0000061C)\r | |
| 755 | @param EAX Lower 32-bits of MSR value.\r | |
| 756 | @param EDX Upper 32-bits of MSR value.\r | |
| 757 | \r | |
| 758 | <b>Example usage</b>\r | |
| 759 | @code\r | |
| 760 | UINT64 Msr;\r | |
| 761 | \r | |
| 762 | Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO);\r | |
| 763 | AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr);\r | |
| 764 | @endcode\r | |
| a73ab083 | 765 | @note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r |
| c67b579c | 766 | **/\r |
| 2f88bd3a | 767 | #define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C\r |
| c67b579c | 768 | \r |
| 0f16be6d HW |
769 | /**\r |
| 770 | Package. Configuration of PCIE PLL Relative to BCLK(R/W).\r | |
| 771 | \r | |
| 772 | @param ECX MSR_HASWELL_E_PCIE_PLL_RATIO (0x0000061E)\r | |
| 773 | @param EAX Lower 32-bits of MSR value.\r | |
| 774 | Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.\r | |
| 775 | @param EDX Upper 32-bits of MSR value.\r | |
| 776 | Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.\r | |
| 777 | \r | |
| 778 | <b>Example usage</b>\r | |
| 779 | @code\r | |
| 780 | MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER Msr;\r | |
| 781 | \r | |
| 782 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO);\r | |
| 783 | AsmWriteMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO, Msr.Uint64);\r | |
| 784 | @endcode\r | |
| 785 | @note MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM.\r | |
| 786 | **/\r | |
| 2f88bd3a | 787 | #define MSR_HASWELL_E_PCIE_PLL_RATIO 0x0000061E\r |
| 0f16be6d HW |
788 | \r |
| 789 | /**\r | |
| 790 | MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO\r | |
| 791 | **/\r | |
| 792 | typedef union {\r | |
| 793 | ///\r | |
| 794 | /// Individual bit fields\r | |
| 795 | ///\r | |
| 796 | struct {\r | |
| 797 | ///\r | |
| 798 | /// [Bits 1:0] Package. PCIE Ratio (R/W) 00b: Use 5:5 mapping for100MHz\r | |
| 799 | /// operation (default) 01b: Use 5:4 mapping for125MHz operation 10b: Use\r | |
| 800 | /// 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz\r | |
| 801 | /// operation.\r | |
| 802 | ///\r | |
| 2f88bd3a | 803 | UINT32 PCIERatio : 2;\r |
| 0f16be6d HW |
804 | ///\r |
| 805 | /// [Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of\r | |
| 806 | /// PCIE Ratio.\r | |
| 807 | ///\r | |
| 2f88bd3a | 808 | UINT32 LPLLSelect : 1;\r |
| 0f16be6d HW |
809 | ///\r |
| 810 | /// [Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out\r | |
| 811 | /// before re-locking Gen2/Gen3 PLLs.\r | |
| 812 | ///\r | |
| 2f88bd3a MK |
813 | UINT32 LONGRESET : 1;\r |
| 814 | UINT32 Reserved1 : 28;\r | |
| 815 | UINT32 Reserved2 : 32;\r | |
| 0f16be6d HW |
816 | } Bits;\r |
| 817 | ///\r | |
| 818 | /// All bit fields as a 32-bit value\r | |
| 819 | ///\r | |
| 2f88bd3a | 820 | UINT32 Uint32;\r |
| 0f16be6d HW |
821 | ///\r |
| 822 | /// All bit fields as a 64-bit value\r | |
| 823 | ///\r | |
| 2f88bd3a | 824 | UINT64 Uint64;\r |
| 0f16be6d HW |
825 | } MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER;\r |
| 826 | \r | |
| 0f16be6d | 827 | /**\r |
| c4b07363 ED |
828 | Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r |
| 829 | fields represent the widest possible range of uncore frequencies. Writing to\r | |
| 830 | these fields allows software to control the minimum and the maximum\r | |
| 831 | frequency that hardware will select.\r | |
| 832 | \r | |
| 833 | @param ECX MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT (0x00000620)\r | |
| 834 | @param EAX Lower 32-bits of MSR value.\r | |
| 835 | Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.\r | |
| 836 | @param EDX Upper 32-bits of MSR value.\r | |
| 837 | Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.\r | |
| 838 | \r | |
| 839 | <b>Example usage</b>\r | |
| 840 | @code\r | |
| 841 | MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r | |
| 842 | \r | |
| 843 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT);\r | |
| 844 | AsmWriteMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r | |
| 845 | @endcode\r | |
| 846 | **/\r | |
| 2f88bd3a | 847 | #define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT 0x00000620\r |
| c4b07363 ED |
848 | \r |
| 849 | /**\r | |
| 850 | MSR information returned for MSR index #MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT\r | |
| 851 | **/\r | |
| 852 | typedef union {\r | |
| 853 | ///\r | |
| 854 | /// Individual bit fields\r | |
| 855 | ///\r | |
| 856 | struct {\r | |
| 857 | ///\r | |
| 858 | /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r | |
| 859 | /// LLC/Ring.\r | |
| 860 | ///\r | |
| 2f88bd3a MK |
861 | UINT32 MAX_RATIO : 7;\r |
| 862 | UINT32 Reserved1 : 1;\r | |
| c4b07363 ED |
863 | ///\r |
| 864 | /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r | |
| 865 | /// possible ratio of the LLC/Ring.\r | |
| 866 | ///\r | |
| 2f88bd3a MK |
867 | UINT32 MIN_RATIO : 7;\r |
| 868 | UINT32 Reserved2 : 17;\r | |
| 869 | UINT32 Reserved3 : 32;\r | |
| c4b07363 ED |
870 | } Bits;\r |
| 871 | ///\r | |
| 872 | /// All bit fields as a 32-bit value\r | |
| 873 | ///\r | |
| 2f88bd3a | 874 | UINT32 Uint32;\r |
| c4b07363 ED |
875 | ///\r |
| 876 | /// All bit fields as a 64-bit value\r | |
| 877 | ///\r | |
| 2f88bd3a | 878 | UINT64 Uint64;\r |
| c4b07363 ED |
879 | } MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER;\r |
| 880 | \r | |
| 881 | /**\r | |
| 882 | Package. Reserved (R/O) Reads return 0.\r | |
| 0f16be6d HW |
883 | \r |
| 884 | @param ECX MSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639)\r | |
| 885 | @param EAX Lower 32-bits of MSR value.\r | |
| 886 | @param EDX Upper 32-bits of MSR value.\r | |
| 887 | \r | |
| 888 | <b>Example usage</b>\r | |
| 889 | @code\r | |
| 890 | UINT64 Msr;\r | |
| 891 | \r | |
| 892 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PP0_ENERGY_STATUS);\r | |
| 893 | @endcode\r | |
| 894 | @note MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r | |
| 895 | **/\r | |
| 2f88bd3a | 896 | #define MSR_HASWELL_E_PP0_ENERGY_STATUS 0x00000639\r |
| 0f16be6d | 897 | \r |
| c67b579c MK |
898 | /**\r |
| 899 | Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r | |
| 900 | refers to processor core frequency).\r | |
| 901 | \r | |
| 902 | @param ECX MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS (0x00000690)\r | |
| 903 | @param EAX Lower 32-bits of MSR value.\r | |
| 904 | Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
| 905 | @param EDX Upper 32-bits of MSR value.\r | |
| 906 | Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
| 907 | \r | |
| 908 | <b>Example usage</b>\r | |
| 909 | @code\r | |
| 910 | MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r | |
| 911 | \r | |
| 912 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS);\r | |
| 913 | AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r | |
| 914 | @endcode\r | |
| a73ab083 | 915 | @note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r |
| c67b579c | 916 | **/\r |
| 2f88bd3a | 917 | #define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690\r |
| c67b579c MK |
918 | \r |
| 919 | /**\r | |
| 920 | MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS\r | |
| 921 | **/\r | |
| 922 | typedef union {\r | |
| 923 | ///\r | |
| 924 | /// Individual bit fields\r | |
| 925 | ///\r | |
| 926 | struct {\r | |
| 927 | ///\r | |
| 928 | /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r | |
| 929 | /// reduced below the operating system request due to assertion of\r | |
| 930 | /// external PROCHOT.\r | |
| 931 | ///\r | |
| 2f88bd3a | 932 | UINT32 PROCHOT_Status : 1;\r |
| c67b579c MK |
933 | ///\r |
| 934 | /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r | |
| 935 | /// operating system request due to a thermal event.\r | |
| 936 | ///\r | |
| 2f88bd3a | 937 | UINT32 ThermalStatus : 1;\r |
| c67b579c MK |
938 | ///\r |
| 939 | /// [Bit 2] Power Budget Management Status (R0) When set, frequency is\r | |
| 940 | /// reduced below the operating system request due to PBM limit.\r | |
| 941 | ///\r | |
| 2f88bd3a | 942 | UINT32 PowerBudgetManagementStatus : 1;\r |
| c67b579c MK |
943 | ///\r |
| 944 | /// [Bit 3] Platform Configuration Services Status (R0) When set,\r | |
| 945 | /// frequency is reduced below the operating system request due to PCS\r | |
| 946 | /// limit.\r | |
| 947 | ///\r | |
| 2f88bd3a MK |
948 | UINT32 PlatformConfigurationServicesStatus : 1;\r |
| 949 | UINT32 Reserved1 : 1;\r | |
| c67b579c MK |
950 | ///\r |
| 951 | /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r | |
| 952 | /// When set, frequency is reduced below the operating system request\r | |
| 953 | /// because the processor has detected that utilization is low.\r | |
| 954 | ///\r | |
| 2f88bd3a | 955 | UINT32 AutonomousUtilizationBasedFrequencyControlStatus : 1;\r |
| c67b579c MK |
956 | ///\r |
| 957 | /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r | |
| 958 | /// below the operating system request due to a thermal alert from the\r | |
| 959 | /// Voltage Regulator.\r | |
| 960 | ///\r | |
| 2f88bd3a MK |
961 | UINT32 VRThermAlertStatus : 1;\r |
| 962 | UINT32 Reserved2 : 1;\r | |
| c67b579c MK |
963 | ///\r |
| 964 | /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r | |
| 965 | /// reduced below the operating system request due to electrical design\r | |
| 966 | /// point constraints (e.g. maximum electrical current consumption).\r | |
| 967 | ///\r | |
| 2f88bd3a MK |
968 | UINT32 ElectricalDesignPointStatus : 1;\r |
| 969 | UINT32 Reserved3 : 1;\r | |
| c67b579c MK |
970 | ///\r |
| 971 | /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced\r | |
| 972 | /// below the operating system request due to Multi-Core Turbo limits.\r | |
| 973 | ///\r | |
| 2f88bd3a MK |
974 | UINT32 MultiCoreTurboStatus : 1;\r |
| 975 | UINT32 Reserved4 : 2;\r | |
| c67b579c MK |
976 | ///\r |
| 977 | /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced\r | |
| 978 | /// below max non-turbo P1.\r | |
| 979 | ///\r | |
| 2f88bd3a | 980 | UINT32 FrequencyP1Status : 1;\r |
| c67b579c MK |
981 | ///\r |
| 982 | /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When\r | |
| 983 | /// set, frequency is reduced below max n-core turbo frequency.\r | |
| 984 | ///\r | |
| 2f88bd3a | 985 | UINT32 TurboFrequencyLimitingStatus : 1;\r |
| c67b579c MK |
986 | ///\r |
| 987 | /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is\r | |
| 988 | /// reduced below the operating system request.\r | |
| 989 | ///\r | |
| 2f88bd3a | 990 | UINT32 FrequencyLimitingStatus : 1;\r |
| c67b579c MK |
991 | ///\r |
| 992 | /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r | |
| 993 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 994 | /// remain set until cleared by software writing 0.\r | |
| 995 | ///\r | |
| 2f88bd3a | 996 | UINT32 PROCHOT_Log : 1;\r |
| c67b579c MK |
997 | ///\r |
| 998 | /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r | |
| 999 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 1000 | /// remain set until cleared by software writing 0.\r | |
| 1001 | ///\r | |
| 2f88bd3a | 1002 | UINT32 ThermalLog : 1;\r |
| c67b579c MK |
1003 | ///\r |
| 1004 | /// [Bit 18] Power Budget Management Log When set, indicates that the PBM\r | |
| 1005 | /// Status bit has asserted since the log bit was last cleared. This log\r | |
| 1006 | /// bit will remain set until cleared by software writing 0.\r | |
| 1007 | ///\r | |
| 2f88bd3a | 1008 | UINT32 PowerBudgetManagementLog : 1;\r |
| c67b579c MK |
1009 | ///\r |
| 1010 | /// [Bit 19] Platform Configuration Services Log When set, indicates that\r | |
| 1011 | /// the PCS Status bit has asserted since the log bit was last cleared.\r | |
| 1012 | /// This log bit will remain set until cleared by software writing 0.\r | |
| 1013 | ///\r | |
| 2f88bd3a MK |
1014 | UINT32 PlatformConfigurationServicesLog : 1;\r |
| 1015 | UINT32 Reserved5 : 1;\r | |
| c67b579c MK |
1016 | ///\r |
| 1017 | /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r | |
| 1018 | /// indicates that the AUBFC Status bit has asserted since the log bit was\r | |
| 1019 | /// last cleared. This log bit will remain set until cleared by software\r | |
| 1020 | /// writing 0.\r | |
| 1021 | ///\r | |
| 2f88bd3a | 1022 | UINT32 AutonomousUtilizationBasedFrequencyControlLog : 1;\r |
| c67b579c MK |
1023 | ///\r |
| 1024 | /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r | |
| 1025 | /// Alert Status bit has asserted since the log bit was last cleared. This\r | |
| 1026 | /// log bit will remain set until cleared by software writing 0.\r | |
| 1027 | ///\r | |
| 2f88bd3a MK |
1028 | UINT32 VRThermAlertLog : 1;\r |
| 1029 | UINT32 Reserved6 : 1;\r | |
| c67b579c MK |
1030 | ///\r |
| 1031 | /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r | |
| 1032 | /// Status bit has asserted since the log bit was last cleared. This log\r | |
| 1033 | /// bit will remain set until cleared by software writing 0.\r | |
| 1034 | ///\r | |
| 2f88bd3a MK |
1035 | UINT32 ElectricalDesignPointLog : 1;\r |
| 1036 | UINT32 Reserved7 : 1;\r | |
| c67b579c MK |
1037 | ///\r |
| 1038 | /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core\r | |
| 1039 | /// Turbo Status bit has asserted since the log bit was last cleared. This\r | |
| 1040 | /// log bit will remain set until cleared by software writing 0.\r | |
| 1041 | ///\r | |
| 2f88bd3a MK |
1042 | UINT32 MultiCoreTurboLog : 1;\r |
| 1043 | UINT32 Reserved8 : 2;\r | |
| c67b579c MK |
1044 | ///\r |
| 1045 | /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core\r | |
| 1046 | /// Frequency P1 Status bit has asserted since the log bit was last\r | |
| 1047 | /// cleared. This log bit will remain set until cleared by software\r | |
| 1048 | /// writing 0.\r | |
| 1049 | ///\r | |
| 2f88bd3a | 1050 | UINT32 CoreFrequencyP1Log : 1;\r |
| c67b579c MK |
1051 | ///\r |
| 1052 | /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,\r | |
| 1053 | /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit\r | |
| 1054 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 1055 | /// remain set until cleared by software writing 0.\r | |
| 1056 | ///\r | |
| 2f88bd3a | 1057 | UINT32 TurboFrequencyLimitingLog : 1;\r |
| c67b579c MK |
1058 | ///\r |
| 1059 | /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core\r | |
| 1060 | /// Frequency Limiting Status bit has asserted since the log bit was last\r | |
| 1061 | /// cleared. This log bit will remain set until cleared by software\r | |
| 1062 | /// writing 0.\r | |
| 1063 | ///\r | |
| 2f88bd3a MK |
1064 | UINT32 CoreFrequencyLimitingLog : 1;\r |
| 1065 | UINT32 Reserved9 : 32;\r | |
| c67b579c MK |
1066 | } Bits;\r |
| 1067 | ///\r | |
| 1068 | /// All bit fields as a 32-bit value\r | |
| 1069 | ///\r | |
| 2f88bd3a | 1070 | UINT32 Uint32;\r |
| c67b579c MK |
1071 | ///\r |
| 1072 | /// All bit fields as a 64-bit value\r | |
| 1073 | ///\r | |
| 2f88bd3a | 1074 | UINT64 Uint64;\r |
| c67b579c MK |
1075 | } MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER;\r |
| 1076 | \r | |
| c67b579c MK |
1077 | /**\r |
| 1078 | THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,\r | |
| 0f16be6d | 1079 | ECX=0):EBX.RDT-M[bit 12] = 1.\r |
| c67b579c MK |
1080 | \r |
| 1081 | @param ECX MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)\r | |
| 1082 | @param EAX Lower 32-bits of MSR value.\r | |
| 1083 | Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.\r | |
| 1084 | @param EDX Upper 32-bits of MSR value.\r | |
| 1085 | Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.\r | |
| 1086 | \r | |
| 1087 | <b>Example usage</b>\r | |
| 1088 | @code\r | |
| 1089 | MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER Msr;\r | |
| 1090 | \r | |
| 1091 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL);\r | |
| 1092 | AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64);\r | |
| 1093 | @endcode\r | |
| a73ab083 | 1094 | @note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r |
| c67b579c | 1095 | **/\r |
| 2f88bd3a | 1096 | #define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D\r |
| c67b579c MK |
1097 | \r |
| 1098 | /**\r | |
| 1099 | MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL\r | |
| 1100 | **/\r | |
| 1101 | typedef union {\r | |
| 1102 | ///\r | |
| 1103 | /// Individual bit fields\r | |
| 1104 | ///\r | |
| 1105 | struct {\r | |
| 1106 | ///\r | |
| 1107 | /// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3\r | |
| 1108 | /// occupancy monitoring all other encoding reserved..\r | |
| 1109 | ///\r | |
| 2f88bd3a MK |
1110 | UINT32 EventID : 8;\r |
| 1111 | UINT32 Reserved1 : 24;\r | |
| c67b579c MK |
1112 | ///\r |
| 1113 | /// [Bits 41:32] RMID (RW).\r | |
| 1114 | ///\r | |
| 2f88bd3a MK |
1115 | UINT32 RMID : 10;\r |
| 1116 | UINT32 Reserved2 : 22;\r | |
| c67b579c MK |
1117 | } Bits;\r |
| 1118 | ///\r | |
| 1119 | /// All bit fields as a 64-bit value\r | |
| 1120 | ///\r | |
| 2f88bd3a | 1121 | UINT64 Uint64;\r |
| c67b579c MK |
1122 | } MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER;\r |
| 1123 | \r | |
| c67b579c MK |
1124 | /**\r |
| 1125 | THREAD. Resource Association Register (R/W)..\r | |
| 1126 | \r | |
| 1127 | @param ECX MSR_HASWELL_E_IA32_PQR_ASSOC (0x00000C8F)\r | |
| 1128 | @param EAX Lower 32-bits of MSR value.\r | |
| 1129 | Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.\r | |
| 1130 | @param EDX Upper 32-bits of MSR value.\r | |
| 1131 | Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.\r | |
| 1132 | \r | |
| 1133 | <b>Example usage</b>\r | |
| 1134 | @code\r | |
| 1135 | MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER Msr;\r | |
| 1136 | \r | |
| 1137 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC);\r | |
| 1138 | AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64);\r | |
| 1139 | @endcode\r | |
| a73ab083 | 1140 | @note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r |
| c67b579c | 1141 | **/\r |
| 2f88bd3a | 1142 | #define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F\r |
| c67b579c MK |
1143 | \r |
| 1144 | /**\r | |
| 1145 | MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC\r | |
| 1146 | **/\r | |
| 1147 | typedef union {\r | |
| 1148 | ///\r | |
| 1149 | /// Individual bit fields\r | |
| 1150 | ///\r | |
| 1151 | struct {\r | |
| 1152 | ///\r | |
| 1153 | /// [Bits 9:0] RMID.\r | |
| 1154 | ///\r | |
| 2f88bd3a MK |
1155 | UINT32 RMID : 10;\r |
| 1156 | UINT32 Reserved1 : 22;\r | |
| 1157 | UINT32 Reserved2 : 32;\r | |
| c67b579c MK |
1158 | } Bits;\r |
| 1159 | ///\r | |
| 1160 | /// All bit fields as a 32-bit value\r | |
| 1161 | ///\r | |
| 2f88bd3a | 1162 | UINT32 Uint32;\r |
| c67b579c MK |
1163 | ///\r |
| 1164 | /// All bit fields as a 64-bit value\r | |
| 1165 | ///\r | |
| 2f88bd3a | 1166 | UINT64 Uint64;\r |
| c67b579c MK |
1167 | } MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER;\r |
| 1168 | \r | |
| c67b579c MK |
1169 | /**\r |
| 1170 | Package. Uncore perfmon per-socket global control.\r | |
| 1171 | \r | |
| 1172 | @param ECX MSR_HASWELL_E_PMON_GLOBAL_CTL (0x00000700)\r | |
| 1173 | @param EAX Lower 32-bits of MSR value.\r | |
| 1174 | @param EDX Upper 32-bits of MSR value.\r | |
| 1175 | \r | |
| 1176 | <b>Example usage</b>\r | |
| 1177 | @code\r | |
| 1178 | UINT64 Msr;\r | |
| 1179 | \r | |
| 1180 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL);\r | |
| 1181 | AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr);\r | |
| 1182 | @endcode\r | |
| a73ab083 | 1183 | @note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.\r |
| c67b579c | 1184 | **/\r |
| 2f88bd3a | 1185 | #define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700\r |
| c67b579c MK |
1186 | \r |
| 1187 | /**\r | |
| 1188 | Package. Uncore perfmon per-socket global status.\r | |
| 1189 | \r | |
| 1190 | @param ECX MSR_HASWELL_E_PMON_GLOBAL_STATUS (0x00000701)\r | |
| 1191 | @param EAX Lower 32-bits of MSR value.\r | |
| 1192 | @param EDX Upper 32-bits of MSR value.\r | |
| 1193 | \r | |
| 1194 | <b>Example usage</b>\r | |
| 1195 | @code\r | |
| 1196 | UINT64 Msr;\r | |
| 1197 | \r | |
| 1198 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS);\r | |
| 1199 | AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr);\r | |
| 1200 | @endcode\r | |
| a73ab083 | 1201 | @note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.\r |
| c67b579c | 1202 | **/\r |
| 2f88bd3a | 1203 | #define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701\r |
| c67b579c MK |
1204 | \r |
| 1205 | /**\r | |
| 1206 | Package. Uncore perfmon per-socket global configuration.\r | |
| 1207 | \r | |
| 1208 | @param ECX MSR_HASWELL_E_PMON_GLOBAL_CONFIG (0x00000702)\r | |
| 1209 | @param EAX Lower 32-bits of MSR value.\r | |
| 1210 | @param EDX Upper 32-bits of MSR value.\r | |
| 1211 | \r | |
| 1212 | <b>Example usage</b>\r | |
| 1213 | @code\r | |
| 1214 | UINT64 Msr;\r | |
| 1215 | \r | |
| 1216 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG);\r | |
| 1217 | AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr);\r | |
| 1218 | @endcode\r | |
| a73ab083 | 1219 | @note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.\r |
| c67b579c | 1220 | **/\r |
| 2f88bd3a | 1221 | #define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702\r |
| c67b579c MK |
1222 | \r |
| 1223 | /**\r | |
| 1224 | Package. Uncore U-box UCLK fixed counter control.\r | |
| 1225 | \r | |
| 1226 | @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL (0x00000703)\r | |
| 1227 | @param EAX Lower 32-bits of MSR value.\r | |
| 1228 | @param EDX Upper 32-bits of MSR value.\r | |
| 1229 | \r | |
| 1230 | <b>Example usage</b>\r | |
| 1231 | @code\r | |
| 1232 | UINT64 Msr;\r | |
| 1233 | \r | |
| 1234 | Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL);\r | |
| 1235 | AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr);\r | |
| 1236 | @endcode\r | |
| a73ab083 | 1237 | @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.\r |
| c67b579c | 1238 | **/\r |
| 2f88bd3a | 1239 | #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703\r |
| c67b579c MK |
1240 | \r |
| 1241 | /**\r | |
| 1242 | Package. Uncore U-box UCLK fixed counter.\r | |
| 1243 | \r | |
| 1244 | @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR (0x00000704)\r | |
| 1245 | @param EAX Lower 32-bits of MSR value.\r | |
| 1246 | @param EDX Upper 32-bits of MSR value.\r | |
| 1247 | \r | |
| 1248 | <b>Example usage</b>\r | |
| 1249 | @code\r | |
| 1250 | UINT64 Msr;\r | |
| 1251 | \r | |
| 1252 | Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR);\r | |
| 1253 | AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr);\r | |
| 1254 | @endcode\r | |
| a73ab083 | 1255 | @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.\r |
| c67b579c | 1256 | **/\r |
| 2f88bd3a | 1257 | #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704\r |
| c67b579c MK |
1258 | \r |
| 1259 | /**\r | |
| 1260 | Package. Uncore U-box perfmon event select for U-box counter 0.\r | |
| 1261 | \r | |
| 1262 | @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL0 (0x00000705)\r | |
| 1263 | @param EAX Lower 32-bits of MSR value.\r | |
| 1264 | @param EDX Upper 32-bits of MSR value.\r | |
| 1265 | \r | |
| 1266 | <b>Example usage</b>\r | |
| 1267 | @code\r | |
| 1268 | UINT64 Msr;\r | |
| 1269 | \r | |
| 1270 | Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0);\r | |
| 1271 | AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr);\r | |
| 1272 | @endcode\r | |
| a73ab083 | 1273 | @note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 1274 | **/\r |
| 2f88bd3a | 1275 | #define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705\r |
| c67b579c MK |
1276 | \r |
| 1277 | /**\r | |
| 1278 | Package. Uncore U-box perfmon event select for U-box counter 1.\r | |
| 1279 | \r | |
| 1280 | @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL1 (0x00000706)\r | |
| 1281 | @param EAX Lower 32-bits of MSR value.\r | |
| 1282 | @param EDX Upper 32-bits of MSR value.\r | |
| 1283 | \r | |
| 1284 | <b>Example usage</b>\r | |
| 1285 | @code\r | |
| 1286 | UINT64 Msr;\r | |
| 1287 | \r | |
| 1288 | Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1);\r | |
| 1289 | AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr);\r | |
| 1290 | @endcode\r | |
| a73ab083 | 1291 | @note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 1292 | **/\r |
| 2f88bd3a | 1293 | #define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706\r |
| c67b579c MK |
1294 | \r |
| 1295 | /**\r | |
| 1296 | Package. Uncore U-box perfmon U-box wide status.\r | |
| 1297 | \r | |
| 1298 | @param ECX MSR_HASWELL_E_U_PMON_BOX_STATUS (0x00000708)\r | |
| 1299 | @param EAX Lower 32-bits of MSR value.\r | |
| 1300 | @param EDX Upper 32-bits of MSR value.\r | |
| 1301 | \r | |
| 1302 | <b>Example usage</b>\r | |
| 1303 | @code\r | |
| 1304 | UINT64 Msr;\r | |
| 1305 | \r | |
| 1306 | Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS);\r | |
| 1307 | AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr);\r | |
| 1308 | @endcode\r | |
| a73ab083 | 1309 | @note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 1310 | **/\r |
| 2f88bd3a | 1311 | #define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708\r |
| c67b579c MK |
1312 | \r |
| 1313 | /**\r | |
| 1314 | Package. Uncore U-box perfmon counter 0.\r | |
| 1315 | \r | |
| 1316 | @param ECX MSR_HASWELL_E_U_PMON_CTR0 (0x00000709)\r | |
| 1317 | @param EAX Lower 32-bits of MSR value.\r | |
| 1318 | @param EDX Upper 32-bits of MSR value.\r | |
| 1319 | \r | |
| 1320 | <b>Example usage</b>\r | |
| 1321 | @code\r | |
| 1322 | UINT64 Msr;\r | |
| 1323 | \r | |
| 1324 | Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0);\r | |
| 1325 | AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr);\r | |
| 1326 | @endcode\r | |
| a73ab083 | 1327 | @note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.\r |
| c67b579c | 1328 | **/\r |
| 2f88bd3a | 1329 | #define MSR_HASWELL_E_U_PMON_CTR0 0x00000709\r |
| c67b579c MK |
1330 | \r |
| 1331 | /**\r | |
| 1332 | Package. Uncore U-box perfmon counter 1.\r | |
| 1333 | \r | |
| 1334 | @param ECX MSR_HASWELL_E_U_PMON_CTR1 (0x0000070A)\r | |
| 1335 | @param EAX Lower 32-bits of MSR value.\r | |
| 1336 | @param EDX Upper 32-bits of MSR value.\r | |
| 1337 | \r | |
| 1338 | <b>Example usage</b>\r | |
| 1339 | @code\r | |
| 1340 | UINT64 Msr;\r | |
| 1341 | \r | |
| 1342 | Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1);\r | |
| 1343 | AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr);\r | |
| 1344 | @endcode\r | |
| a73ab083 | 1345 | @note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.\r |
| c67b579c | 1346 | **/\r |
| 2f88bd3a | 1347 | #define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A\r |
| c67b579c MK |
1348 | \r |
| 1349 | /**\r | |
| 1350 | Package. Uncore PCU perfmon for PCU-box-wide control.\r | |
| 1351 | \r | |
| 1352 | @param ECX MSR_HASWELL_E_PCU_PMON_BOX_CTL (0x00000710)\r | |
| 1353 | @param EAX Lower 32-bits of MSR value.\r | |
| 1354 | @param EDX Upper 32-bits of MSR value.\r | |
| 1355 | \r | |
| 1356 | <b>Example usage</b>\r | |
| 1357 | @code\r | |
| 1358 | UINT64 Msr;\r | |
| 1359 | \r | |
| 1360 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL);\r | |
| 1361 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr);\r | |
| 1362 | @endcode\r | |
| a73ab083 | 1363 | @note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.\r |
| c67b579c | 1364 | **/\r |
| 2f88bd3a | 1365 | #define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710\r |
| c67b579c MK |
1366 | \r |
| 1367 | /**\r | |
| 1368 | Package. Uncore PCU perfmon event select for PCU counter 0.\r | |
| 1369 | \r | |
| 1370 | @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL0 (0x00000711)\r | |
| 1371 | @param EAX Lower 32-bits of MSR value.\r | |
| 1372 | @param EDX Upper 32-bits of MSR value.\r | |
| 1373 | \r | |
| 1374 | <b>Example usage</b>\r | |
| 1375 | @code\r | |
| 1376 | UINT64 Msr;\r | |
| 1377 | \r | |
| 1378 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0);\r | |
| 1379 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr);\r | |
| 1380 | @endcode\r | |
| a73ab083 | 1381 | @note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 1382 | **/\r |
| 2f88bd3a | 1383 | #define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711\r |
| c67b579c MK |
1384 | \r |
| 1385 | /**\r | |
| 1386 | Package. Uncore PCU perfmon event select for PCU counter 1.\r | |
| 1387 | \r | |
| 1388 | @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL1 (0x00000712)\r | |
| 1389 | @param EAX Lower 32-bits of MSR value.\r | |
| 1390 | @param EDX Upper 32-bits of MSR value.\r | |
| 1391 | \r | |
| 1392 | <b>Example usage</b>\r | |
| 1393 | @code\r | |
| 1394 | UINT64 Msr;\r | |
| 1395 | \r | |
| 1396 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1);\r | |
| 1397 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr);\r | |
| 1398 | @endcode\r | |
| a73ab083 | 1399 | @note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 1400 | **/\r |
| 2f88bd3a | 1401 | #define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712\r |
| c67b579c MK |
1402 | \r |
| 1403 | /**\r | |
| 1404 | Package. Uncore PCU perfmon event select for PCU counter 2.\r | |
| 1405 | \r | |
| 1406 | @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL2 (0x00000713)\r | |
| 1407 | @param EAX Lower 32-bits of MSR value.\r | |
| 1408 | @param EDX Upper 32-bits of MSR value.\r | |
| 1409 | \r | |
| 1410 | <b>Example usage</b>\r | |
| 1411 | @code\r | |
| 1412 | UINT64 Msr;\r | |
| 1413 | \r | |
| 1414 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2);\r | |
| 1415 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr);\r | |
| 1416 | @endcode\r | |
| a73ab083 | 1417 | @note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 1418 | **/\r |
| 2f88bd3a | 1419 | #define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713\r |
| c67b579c MK |
1420 | \r |
| 1421 | /**\r | |
| 1422 | Package. Uncore PCU perfmon event select for PCU counter 3.\r | |
| 1423 | \r | |
| 1424 | @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL3 (0x00000714)\r | |
| 1425 | @param EAX Lower 32-bits of MSR value.\r | |
| 1426 | @param EDX Upper 32-bits of MSR value.\r | |
| 1427 | \r | |
| 1428 | <b>Example usage</b>\r | |
| 1429 | @code\r | |
| 1430 | UINT64 Msr;\r | |
| 1431 | \r | |
| 1432 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3);\r | |
| 1433 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr);\r | |
| 1434 | @endcode\r | |
| a73ab083 | 1435 | @note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 1436 | **/\r |
| 2f88bd3a | 1437 | #define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714\r |
| c67b579c MK |
1438 | \r |
| 1439 | /**\r | |
| 1440 | Package. Uncore PCU perfmon box-wide filter.\r | |
| 1441 | \r | |
| 1442 | @param ECX MSR_HASWELL_E_PCU_PMON_BOX_FILTER (0x00000715)\r | |
| 1443 | @param EAX Lower 32-bits of MSR value.\r | |
| 1444 | @param EDX Upper 32-bits of MSR value.\r | |
| 1445 | \r | |
| 1446 | <b>Example usage</b>\r | |
| 1447 | @code\r | |
| 1448 | UINT64 Msr;\r | |
| 1449 | \r | |
| 1450 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER);\r | |
| 1451 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr);\r | |
| 1452 | @endcode\r | |
| a73ab083 | 1453 | @note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.\r |
| c67b579c | 1454 | **/\r |
| 2f88bd3a | 1455 | #define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715\r |
| c67b579c MK |
1456 | \r |
| 1457 | /**\r | |
| 1458 | Package. Uncore PCU perfmon box wide status.\r | |
| 1459 | \r | |
| 1460 | @param ECX MSR_HASWELL_E_PCU_PMON_BOX_STATUS (0x00000716)\r | |
| 1461 | @param EAX Lower 32-bits of MSR value.\r | |
| 1462 | @param EDX Upper 32-bits of MSR value.\r | |
| 1463 | \r | |
| 1464 | <b>Example usage</b>\r | |
| 1465 | @code\r | |
| 1466 | UINT64 Msr;\r | |
| 1467 | \r | |
| 1468 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS);\r | |
| 1469 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr);\r | |
| 1470 | @endcode\r | |
| a73ab083 | 1471 | @note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 1472 | **/\r |
| 2f88bd3a | 1473 | #define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716\r |
| c67b579c MK |
1474 | \r |
| 1475 | /**\r | |
| 1476 | Package. Uncore PCU perfmon counter 0.\r | |
| 1477 | \r | |
| 1478 | @param ECX MSR_HASWELL_E_PCU_PMON_CTR0 (0x00000717)\r | |
| 1479 | @param EAX Lower 32-bits of MSR value.\r | |
| 1480 | @param EDX Upper 32-bits of MSR value.\r | |
| 1481 | \r | |
| 1482 | <b>Example usage</b>\r | |
| 1483 | @code\r | |
| 1484 | UINT64 Msr;\r | |
| 1485 | \r | |
| 1486 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0);\r | |
| 1487 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr);\r | |
| 1488 | @endcode\r | |
| a73ab083 | 1489 | @note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.\r |
| c67b579c | 1490 | **/\r |
| 2f88bd3a | 1491 | #define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717\r |
| c67b579c MK |
1492 | \r |
| 1493 | /**\r | |
| 1494 | Package. Uncore PCU perfmon counter 1.\r | |
| 1495 | \r | |
| 1496 | @param ECX MSR_HASWELL_E_PCU_PMON_CTR1 (0x00000718)\r | |
| 1497 | @param EAX Lower 32-bits of MSR value.\r | |
| 1498 | @param EDX Upper 32-bits of MSR value.\r | |
| 1499 | \r | |
| 1500 | <b>Example usage</b>\r | |
| 1501 | @code\r | |
| 1502 | UINT64 Msr;\r | |
| 1503 | \r | |
| 1504 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1);\r | |
| 1505 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr);\r | |
| 1506 | @endcode\r | |
| a73ab083 | 1507 | @note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.\r |
| c67b579c | 1508 | **/\r |
| 2f88bd3a | 1509 | #define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718\r |
| c67b579c MK |
1510 | \r |
| 1511 | /**\r | |
| 1512 | Package. Uncore PCU perfmon counter 2.\r | |
| 1513 | \r | |
| 1514 | @param ECX MSR_HASWELL_E_PCU_PMON_CTR2 (0x00000719)\r | |
| 1515 | @param EAX Lower 32-bits of MSR value.\r | |
| 1516 | @param EDX Upper 32-bits of MSR value.\r | |
| 1517 | \r | |
| 1518 | <b>Example usage</b>\r | |
| 1519 | @code\r | |
| 1520 | UINT64 Msr;\r | |
| 1521 | \r | |
| 1522 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2);\r | |
| 1523 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr);\r | |
| 1524 | @endcode\r | |
| a73ab083 | 1525 | @note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.\r |
| c67b579c | 1526 | **/\r |
| 2f88bd3a | 1527 | #define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719\r |
| c67b579c MK |
1528 | \r |
| 1529 | /**\r | |
| 1530 | Package. Uncore PCU perfmon counter 3.\r | |
| 1531 | \r | |
| 1532 | @param ECX MSR_HASWELL_E_PCU_PMON_CTR3 (0x0000071A)\r | |
| 1533 | @param EAX Lower 32-bits of MSR value.\r | |
| 1534 | @param EDX Upper 32-bits of MSR value.\r | |
| 1535 | \r | |
| 1536 | <b>Example usage</b>\r | |
| 1537 | @code\r | |
| 1538 | UINT64 Msr;\r | |
| 1539 | \r | |
| 1540 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3);\r | |
| 1541 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr);\r | |
| 1542 | @endcode\r | |
| a73ab083 | 1543 | @note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.\r |
| c67b579c | 1544 | **/\r |
| 2f88bd3a | 1545 | #define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A\r |
| c67b579c MK |
1546 | \r |
| 1547 | /**\r | |
| 1548 | Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.\r | |
| 1549 | \r | |
| 1550 | @param ECX MSR_HASWELL_E_S0_PMON_BOX_CTL (0x00000720)\r | |
| 1551 | @param EAX Lower 32-bits of MSR value.\r | |
| 1552 | @param EDX Upper 32-bits of MSR value.\r | |
| 1553 | \r | |
| 1554 | <b>Example usage</b>\r | |
| 1555 | @code\r | |
| 1556 | UINT64 Msr;\r | |
| 1557 | \r | |
| 1558 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL);\r | |
| 1559 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr);\r | |
| 1560 | @endcode\r | |
| a73ab083 | 1561 | @note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.\r |
| c67b579c | 1562 | **/\r |
| 2f88bd3a | 1563 | #define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720\r |
| c67b579c MK |
1564 | \r |
| 1565 | /**\r | |
| 1566 | Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.\r | |
| 1567 | \r | |
| 1568 | @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL0 (0x00000721)\r | |
| 1569 | @param EAX Lower 32-bits of MSR value.\r | |
| 1570 | @param EDX Upper 32-bits of MSR value.\r | |
| 1571 | \r | |
| 1572 | <b>Example usage</b>\r | |
| 1573 | @code\r | |
| 1574 | UINT64 Msr;\r | |
| 1575 | \r | |
| 1576 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0);\r | |
| 1577 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr);\r | |
| 1578 | @endcode\r | |
| a73ab083 | 1579 | @note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 1580 | **/\r |
| 2f88bd3a | 1581 | #define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721\r |
| c67b579c MK |
1582 | \r |
| 1583 | /**\r | |
| 1584 | Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.\r | |
| 1585 | \r | |
| 1586 | @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL1 (0x00000722)\r | |
| 1587 | @param EAX Lower 32-bits of MSR value.\r | |
| 1588 | @param EDX Upper 32-bits of MSR value.\r | |
| 1589 | \r | |
| 1590 | <b>Example usage</b>\r | |
| 1591 | @code\r | |
| 1592 | UINT64 Msr;\r | |
| 1593 | \r | |
| 1594 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1);\r | |
| 1595 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr);\r | |
| 1596 | @endcode\r | |
| a73ab083 | 1597 | @note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 1598 | **/\r |
| 2f88bd3a | 1599 | #define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722\r |
| c67b579c MK |
1600 | \r |
| 1601 | /**\r | |
| 1602 | Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.\r | |
| 1603 | \r | |
| 1604 | @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL2 (0x00000723)\r | |
| 1605 | @param EAX Lower 32-bits of MSR value.\r | |
| 1606 | @param EDX Upper 32-bits of MSR value.\r | |
| 1607 | \r | |
| 1608 | <b>Example usage</b>\r | |
| 1609 | @code\r | |
| 1610 | UINT64 Msr;\r | |
| 1611 | \r | |
| 1612 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2);\r | |
| 1613 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr);\r | |
| 1614 | @endcode\r | |
| a73ab083 | 1615 | @note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 1616 | **/\r |
| 2f88bd3a | 1617 | #define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723\r |
| c67b579c MK |
1618 | \r |
| 1619 | /**\r | |
| 1620 | Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.\r | |
| 1621 | \r | |
| 1622 | @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL3 (0x00000724)\r | |
| 1623 | @param EAX Lower 32-bits of MSR value.\r | |
| 1624 | @param EDX Upper 32-bits of MSR value.\r | |
| 1625 | \r | |
| 1626 | <b>Example usage</b>\r | |
| 1627 | @code\r | |
| 1628 | UINT64 Msr;\r | |
| 1629 | \r | |
| 1630 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3);\r | |
| 1631 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr);\r | |
| 1632 | @endcode\r | |
| a73ab083 | 1633 | @note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 1634 | **/\r |
| 2f88bd3a | 1635 | #define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724\r |
| c67b579c MK |
1636 | \r |
| 1637 | /**\r | |
| 1638 | Package. Uncore SBo 0 perfmon box-wide filter.\r | |
| 1639 | \r | |
| 1640 | @param ECX MSR_HASWELL_E_S0_PMON_BOX_FILTER (0x00000725)\r | |
| 1641 | @param EAX Lower 32-bits of MSR value.\r | |
| 1642 | @param EDX Upper 32-bits of MSR value.\r | |
| 1643 | \r | |
| 1644 | <b>Example usage</b>\r | |
| 1645 | @code\r | |
| 1646 | UINT64 Msr;\r | |
| 1647 | \r | |
| 1648 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER);\r | |
| 1649 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr);\r | |
| 1650 | @endcode\r | |
| a73ab083 | 1651 | @note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.\r |
| c67b579c | 1652 | **/\r |
| 2f88bd3a | 1653 | #define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725\r |
| c67b579c MK |
1654 | \r |
| 1655 | /**\r | |
| 1656 | Package. Uncore SBo 0 perfmon counter 0.\r | |
| 1657 | \r | |
| 1658 | @param ECX MSR_HASWELL_E_S0_PMON_CTR0 (0x00000726)\r | |
| 1659 | @param EAX Lower 32-bits of MSR value.\r | |
| 1660 | @param EDX Upper 32-bits of MSR value.\r | |
| 1661 | \r | |
| 1662 | <b>Example usage</b>\r | |
| 1663 | @code\r | |
| 1664 | UINT64 Msr;\r | |
| 1665 | \r | |
| 1666 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0);\r | |
| 1667 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr);\r | |
| 1668 | @endcode\r | |
| a73ab083 | 1669 | @note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.\r |
| c67b579c | 1670 | **/\r |
| 2f88bd3a | 1671 | #define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726\r |
| c67b579c MK |
1672 | \r |
| 1673 | /**\r | |
| 1674 | Package. Uncore SBo 0 perfmon counter 1.\r | |
| 1675 | \r | |
| 1676 | @param ECX MSR_HASWELL_E_S0_PMON_CTR1 (0x00000727)\r | |
| 1677 | @param EAX Lower 32-bits of MSR value.\r | |
| 1678 | @param EDX Upper 32-bits of MSR value.\r | |
| 1679 | \r | |
| 1680 | <b>Example usage</b>\r | |
| 1681 | @code\r | |
| 1682 | UINT64 Msr;\r | |
| 1683 | \r | |
| 1684 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1);\r | |
| 1685 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr);\r | |
| 1686 | @endcode\r | |
| a73ab083 | 1687 | @note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.\r |
| c67b579c | 1688 | **/\r |
| 2f88bd3a | 1689 | #define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727\r |
| c67b579c MK |
1690 | \r |
| 1691 | /**\r | |
| 1692 | Package. Uncore SBo 0 perfmon counter 2.\r | |
| 1693 | \r | |
| 1694 | @param ECX MSR_HASWELL_E_S0_PMON_CTR2 (0x00000728)\r | |
| 1695 | @param EAX Lower 32-bits of MSR value.\r | |
| 1696 | @param EDX Upper 32-bits of MSR value.\r | |
| 1697 | \r | |
| 1698 | <b>Example usage</b>\r | |
| 1699 | @code\r | |
| 1700 | UINT64 Msr;\r | |
| 1701 | \r | |
| 1702 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2);\r | |
| 1703 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr);\r | |
| 1704 | @endcode\r | |
| a73ab083 | 1705 | @note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.\r |
| c67b579c | 1706 | **/\r |
| 2f88bd3a | 1707 | #define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728\r |
| c67b579c MK |
1708 | \r |
| 1709 | /**\r | |
| 1710 | Package. Uncore SBo 0 perfmon counter 3.\r | |
| 1711 | \r | |
| 1712 | @param ECX MSR_HASWELL_E_S0_PMON_CTR3 (0x00000729)\r | |
| 1713 | @param EAX Lower 32-bits of MSR value.\r | |
| 1714 | @param EDX Upper 32-bits of MSR value.\r | |
| 1715 | \r | |
| 1716 | <b>Example usage</b>\r | |
| 1717 | @code\r | |
| 1718 | UINT64 Msr;\r | |
| 1719 | \r | |
| 1720 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3);\r | |
| 1721 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr);\r | |
| 1722 | @endcode\r | |
| a73ab083 | 1723 | @note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.\r |
| c67b579c | 1724 | **/\r |
| 2f88bd3a | 1725 | #define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729\r |
| c67b579c MK |
1726 | \r |
| 1727 | /**\r | |
| 1728 | Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.\r | |
| 1729 | \r | |
| 1730 | @param ECX MSR_HASWELL_E_S1_PMON_BOX_CTL (0x0000072A)\r | |
| 1731 | @param EAX Lower 32-bits of MSR value.\r | |
| 1732 | @param EDX Upper 32-bits of MSR value.\r | |
| 1733 | \r | |
| 1734 | <b>Example usage</b>\r | |
| 1735 | @code\r | |
| 1736 | UINT64 Msr;\r | |
| 1737 | \r | |
| 1738 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL);\r | |
| 1739 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr);\r | |
| 1740 | @endcode\r | |
| a73ab083 | 1741 | @note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.\r |
| c67b579c | 1742 | **/\r |
| 2f88bd3a | 1743 | #define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A\r |
| c67b579c MK |
1744 | \r |
| 1745 | /**\r | |
| 1746 | Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.\r | |
| 1747 | \r | |
| 1748 | @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL0 (0x0000072B)\r | |
| 1749 | @param EAX Lower 32-bits of MSR value.\r | |
| 1750 | @param EDX Upper 32-bits of MSR value.\r | |
| 1751 | \r | |
| 1752 | <b>Example usage</b>\r | |
| 1753 | @code\r | |
| 1754 | UINT64 Msr;\r | |
| 1755 | \r | |
| 1756 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0);\r | |
| 1757 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr);\r | |
| 1758 | @endcode\r | |
| a73ab083 | 1759 | @note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 1760 | **/\r |
| 2f88bd3a | 1761 | #define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B\r |
| c67b579c MK |
1762 | \r |
| 1763 | /**\r | |
| 1764 | Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.\r | |
| 1765 | \r | |
| 1766 | @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL1 (0x0000072C)\r | |
| 1767 | @param EAX Lower 32-bits of MSR value.\r | |
| 1768 | @param EDX Upper 32-bits of MSR value.\r | |
| 1769 | \r | |
| 1770 | <b>Example usage</b>\r | |
| 1771 | @code\r | |
| 1772 | UINT64 Msr;\r | |
| 1773 | \r | |
| 1774 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1);\r | |
| 1775 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr);\r | |
| 1776 | @endcode\r | |
| a73ab083 | 1777 | @note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 1778 | **/\r |
| 2f88bd3a | 1779 | #define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C\r |
| c67b579c MK |
1780 | \r |
| 1781 | /**\r | |
| 1782 | Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.\r | |
| 1783 | \r | |
| 1784 | @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL2 (0x0000072D)\r | |
| 1785 | @param EAX Lower 32-bits of MSR value.\r | |
| 1786 | @param EDX Upper 32-bits of MSR value.\r | |
| 1787 | \r | |
| 1788 | <b>Example usage</b>\r | |
| 1789 | @code\r | |
| 1790 | UINT64 Msr;\r | |
| 1791 | \r | |
| 1792 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2);\r | |
| 1793 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr);\r | |
| 1794 | @endcode\r | |
| a73ab083 | 1795 | @note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 1796 | **/\r |
| 2f88bd3a | 1797 | #define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D\r |
| c67b579c MK |
1798 | \r |
| 1799 | /**\r | |
| 1800 | Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.\r | |
| 1801 | \r | |
| 1802 | @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL3 (0x0000072E)\r | |
| 1803 | @param EAX Lower 32-bits of MSR value.\r | |
| 1804 | @param EDX Upper 32-bits of MSR value.\r | |
| 1805 | \r | |
| 1806 | <b>Example usage</b>\r | |
| 1807 | @code\r | |
| 1808 | UINT64 Msr;\r | |
| 1809 | \r | |
| 1810 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3);\r | |
| 1811 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr);\r | |
| 1812 | @endcode\r | |
| a73ab083 | 1813 | @note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 1814 | **/\r |
| 2f88bd3a | 1815 | #define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E\r |
| c67b579c MK |
1816 | \r |
| 1817 | /**\r | |
| 1818 | Package. Uncore SBo 1 perfmon box-wide filter.\r | |
| 1819 | \r | |
| 1820 | @param ECX MSR_HASWELL_E_S1_PMON_BOX_FILTER (0x0000072F)\r | |
| 1821 | @param EAX Lower 32-bits of MSR value.\r | |
| 1822 | @param EDX Upper 32-bits of MSR value.\r | |
| 1823 | \r | |
| 1824 | <b>Example usage</b>\r | |
| 1825 | @code\r | |
| 1826 | UINT64 Msr;\r | |
| 1827 | \r | |
| 1828 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER);\r | |
| 1829 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr);\r | |
| 1830 | @endcode\r | |
| a73ab083 | 1831 | @note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.\r |
| c67b579c | 1832 | **/\r |
| 2f88bd3a | 1833 | #define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F\r |
| c67b579c MK |
1834 | \r |
| 1835 | /**\r | |
| 1836 | Package. Uncore SBo 1 perfmon counter 0.\r | |
| 1837 | \r | |
| 1838 | @param ECX MSR_HASWELL_E_S1_PMON_CTR0 (0x00000730)\r | |
| 1839 | @param EAX Lower 32-bits of MSR value.\r | |
| 1840 | @param EDX Upper 32-bits of MSR value.\r | |
| 1841 | \r | |
| 1842 | <b>Example usage</b>\r | |
| 1843 | @code\r | |
| 1844 | UINT64 Msr;\r | |
| 1845 | \r | |
| 1846 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0);\r | |
| 1847 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr);\r | |
| 1848 | @endcode\r | |
| a73ab083 | 1849 | @note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.\r |
| c67b579c | 1850 | **/\r |
| 2f88bd3a | 1851 | #define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730\r |
| c67b579c MK |
1852 | \r |
| 1853 | /**\r | |
| 1854 | Package. Uncore SBo 1 perfmon counter 1.\r | |
| 1855 | \r | |
| 1856 | @param ECX MSR_HASWELL_E_S1_PMON_CTR1 (0x00000731)\r | |
| 1857 | @param EAX Lower 32-bits of MSR value.\r | |
| 1858 | @param EDX Upper 32-bits of MSR value.\r | |
| 1859 | \r | |
| 1860 | <b>Example usage</b>\r | |
| 1861 | @code\r | |
| 1862 | UINT64 Msr;\r | |
| 1863 | \r | |
| 1864 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1);\r | |
| 1865 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr);\r | |
| 1866 | @endcode\r | |
| a73ab083 | 1867 | @note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.\r |
| c67b579c | 1868 | **/\r |
| 2f88bd3a | 1869 | #define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731\r |
| c67b579c MK |
1870 | \r |
| 1871 | /**\r | |
| 1872 | Package. Uncore SBo 1 perfmon counter 2.\r | |
| 1873 | \r | |
| 1874 | @param ECX MSR_HASWELL_E_S1_PMON_CTR2 (0x00000732)\r | |
| 1875 | @param EAX Lower 32-bits of MSR value.\r | |
| 1876 | @param EDX Upper 32-bits of MSR value.\r | |
| 1877 | \r | |
| 1878 | <b>Example usage</b>\r | |
| 1879 | @code\r | |
| 1880 | UINT64 Msr;\r | |
| 1881 | \r | |
| 1882 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2);\r | |
| 1883 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr);\r | |
| 1884 | @endcode\r | |
| a73ab083 | 1885 | @note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.\r |
| c67b579c | 1886 | **/\r |
| 2f88bd3a | 1887 | #define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732\r |
| c67b579c MK |
1888 | \r |
| 1889 | /**\r | |
| 1890 | Package. Uncore SBo 1 perfmon counter 3.\r | |
| 1891 | \r | |
| 1892 | @param ECX MSR_HASWELL_E_S1_PMON_CTR3 (0x00000733)\r | |
| 1893 | @param EAX Lower 32-bits of MSR value.\r | |
| 1894 | @param EDX Upper 32-bits of MSR value.\r | |
| 1895 | \r | |
| 1896 | <b>Example usage</b>\r | |
| 1897 | @code\r | |
| 1898 | UINT64 Msr;\r | |
| 1899 | \r | |
| 1900 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3);\r | |
| 1901 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr);\r | |
| 1902 | @endcode\r | |
| a73ab083 | 1903 | @note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.\r |
| c67b579c | 1904 | **/\r |
| 2f88bd3a | 1905 | #define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733\r |
| c67b579c MK |
1906 | \r |
| 1907 | /**\r | |
| 1908 | Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.\r | |
| 1909 | \r | |
| 1910 | @param ECX MSR_HASWELL_E_S2_PMON_BOX_CTL (0x00000734)\r | |
| 1911 | @param EAX Lower 32-bits of MSR value.\r | |
| 1912 | @param EDX Upper 32-bits of MSR value.\r | |
| 1913 | \r | |
| 1914 | <b>Example usage</b>\r | |
| 1915 | @code\r | |
| 1916 | UINT64 Msr;\r | |
| 1917 | \r | |
| 1918 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL);\r | |
| 1919 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr);\r | |
| 1920 | @endcode\r | |
| a73ab083 | 1921 | @note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.\r |
| c67b579c | 1922 | **/\r |
| 2f88bd3a | 1923 | #define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734\r |
| c67b579c MK |
1924 | \r |
| 1925 | /**\r | |
| 1926 | Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.\r | |
| 1927 | \r | |
| 1928 | @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL0 (0x00000735)\r | |
| 1929 | @param EAX Lower 32-bits of MSR value.\r | |
| 1930 | @param EDX Upper 32-bits of MSR value.\r | |
| 1931 | \r | |
| 1932 | <b>Example usage</b>\r | |
| 1933 | @code\r | |
| 1934 | UINT64 Msr;\r | |
| 1935 | \r | |
| 1936 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0);\r | |
| 1937 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr);\r | |
| 1938 | @endcode\r | |
| a73ab083 | 1939 | @note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 1940 | **/\r |
| 2f88bd3a | 1941 | #define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735\r |
| c67b579c MK |
1942 | \r |
| 1943 | /**\r | |
| 1944 | Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.\r | |
| 1945 | \r | |
| 1946 | @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL1 (0x00000736)\r | |
| 1947 | @param EAX Lower 32-bits of MSR value.\r | |
| 1948 | @param EDX Upper 32-bits of MSR value.\r | |
| 1949 | \r | |
| 1950 | <b>Example usage</b>\r | |
| 1951 | @code\r | |
| 1952 | UINT64 Msr;\r | |
| 1953 | \r | |
| 1954 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1);\r | |
| 1955 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr);\r | |
| 1956 | @endcode\r | |
| a73ab083 | 1957 | @note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 1958 | **/\r |
| 2f88bd3a | 1959 | #define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736\r |
| c67b579c MK |
1960 | \r |
| 1961 | /**\r | |
| 1962 | Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.\r | |
| 1963 | \r | |
| 1964 | @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL2 (0x00000737)\r | |
| 1965 | @param EAX Lower 32-bits of MSR value.\r | |
| 1966 | @param EDX Upper 32-bits of MSR value.\r | |
| 1967 | \r | |
| 1968 | <b>Example usage</b>\r | |
| 1969 | @code\r | |
| 1970 | UINT64 Msr;\r | |
| 1971 | \r | |
| 1972 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2);\r | |
| 1973 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr);\r | |
| 1974 | @endcode\r | |
| a73ab083 | 1975 | @note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 1976 | **/\r |
| 2f88bd3a | 1977 | #define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737\r |
| c67b579c MK |
1978 | \r |
| 1979 | /**\r | |
| 1980 | Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.\r | |
| 1981 | \r | |
| 1982 | @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL3 (0x00000738)\r | |
| 1983 | @param EAX Lower 32-bits of MSR value.\r | |
| 1984 | @param EDX Upper 32-bits of MSR value.\r | |
| 1985 | \r | |
| 1986 | <b>Example usage</b>\r | |
| 1987 | @code\r | |
| 1988 | UINT64 Msr;\r | |
| 1989 | \r | |
| 1990 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3);\r | |
| 1991 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr);\r | |
| 1992 | @endcode\r | |
| a73ab083 | 1993 | @note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 1994 | **/\r |
| 2f88bd3a | 1995 | #define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738\r |
| c67b579c MK |
1996 | \r |
| 1997 | /**\r | |
| 1998 | Package. Uncore SBo 2 perfmon box-wide filter.\r | |
| 1999 | \r | |
| 2000 | @param ECX MSR_HASWELL_E_S2_PMON_BOX_FILTER (0x00000739)\r | |
| 2001 | @param EAX Lower 32-bits of MSR value.\r | |
| 2002 | @param EDX Upper 32-bits of MSR value.\r | |
| 2003 | \r | |
| 2004 | <b>Example usage</b>\r | |
| 2005 | @code\r | |
| 2006 | UINT64 Msr;\r | |
| 2007 | \r | |
| 2008 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER);\r | |
| 2009 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr);\r | |
| 2010 | @endcode\r | |
| a73ab083 | 2011 | @note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.\r |
| c67b579c | 2012 | **/\r |
| 2f88bd3a | 2013 | #define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739\r |
| c67b579c MK |
2014 | \r |
| 2015 | /**\r | |
| 2016 | Package. Uncore SBo 2 perfmon counter 0.\r | |
| 2017 | \r | |
| 2018 | @param ECX MSR_HASWELL_E_S2_PMON_CTR0 (0x0000073A)\r | |
| 2019 | @param EAX Lower 32-bits of MSR value.\r | |
| 2020 | @param EDX Upper 32-bits of MSR value.\r | |
| 2021 | \r | |
| 2022 | <b>Example usage</b>\r | |
| 2023 | @code\r | |
| 2024 | UINT64 Msr;\r | |
| 2025 | \r | |
| 2026 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0);\r | |
| 2027 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr);\r | |
| 2028 | @endcode\r | |
| a73ab083 | 2029 | @note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.\r |
| c67b579c | 2030 | **/\r |
| 2f88bd3a | 2031 | #define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A\r |
| c67b579c MK |
2032 | \r |
| 2033 | /**\r | |
| 2034 | Package. Uncore SBo 2 perfmon counter 1.\r | |
| 2035 | \r | |
| 2036 | @param ECX MSR_HASWELL_E_S2_PMON_CTR1 (0x0000073B)\r | |
| 2037 | @param EAX Lower 32-bits of MSR value.\r | |
| 2038 | @param EDX Upper 32-bits of MSR value.\r | |
| 2039 | \r | |
| 2040 | <b>Example usage</b>\r | |
| 2041 | @code\r | |
| 2042 | UINT64 Msr;\r | |
| 2043 | \r | |
| 2044 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1);\r | |
| 2045 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr);\r | |
| 2046 | @endcode\r | |
| a73ab083 | 2047 | @note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.\r |
| c67b579c | 2048 | **/\r |
| 2f88bd3a | 2049 | #define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B\r |
| c67b579c MK |
2050 | \r |
| 2051 | /**\r | |
| 2052 | Package. Uncore SBo 2 perfmon counter 2.\r | |
| 2053 | \r | |
| 2054 | @param ECX MSR_HASWELL_E_S2_PMON_CTR2 (0x0000073C)\r | |
| 2055 | @param EAX Lower 32-bits of MSR value.\r | |
| 2056 | @param EDX Upper 32-bits of MSR value.\r | |
| 2057 | \r | |
| 2058 | <b>Example usage</b>\r | |
| 2059 | @code\r | |
| 2060 | UINT64 Msr;\r | |
| 2061 | \r | |
| 2062 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2);\r | |
| 2063 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr);\r | |
| 2064 | @endcode\r | |
| a73ab083 | 2065 | @note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.\r |
| c67b579c | 2066 | **/\r |
| 2f88bd3a | 2067 | #define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C\r |
| c67b579c MK |
2068 | \r |
| 2069 | /**\r | |
| 2070 | Package. Uncore SBo 2 perfmon counter 3.\r | |
| 2071 | \r | |
| 2072 | @param ECX MSR_HASWELL_E_S2_PMON_CTR3 (0x0000073D)\r | |
| 2073 | @param EAX Lower 32-bits of MSR value.\r | |
| 2074 | @param EDX Upper 32-bits of MSR value.\r | |
| 2075 | \r | |
| 2076 | <b>Example usage</b>\r | |
| 2077 | @code\r | |
| 2078 | UINT64 Msr;\r | |
| 2079 | \r | |
| 2080 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3);\r | |
| 2081 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr);\r | |
| 2082 | @endcode\r | |
| a73ab083 | 2083 | @note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.\r |
| c67b579c | 2084 | **/\r |
| 2f88bd3a | 2085 | #define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D\r |
| c67b579c MK |
2086 | \r |
| 2087 | /**\r | |
| 2088 | Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.\r | |
| 2089 | \r | |
| 2090 | @param ECX MSR_HASWELL_E_S3_PMON_BOX_CTL (0x0000073E)\r | |
| 2091 | @param EAX Lower 32-bits of MSR value.\r | |
| 2092 | @param EDX Upper 32-bits of MSR value.\r | |
| 2093 | \r | |
| 2094 | <b>Example usage</b>\r | |
| 2095 | @code\r | |
| 2096 | UINT64 Msr;\r | |
| 2097 | \r | |
| 2098 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL);\r | |
| 2099 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr);\r | |
| 2100 | @endcode\r | |
| a73ab083 | 2101 | @note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.\r |
| c67b579c | 2102 | **/\r |
| 2f88bd3a | 2103 | #define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E\r |
| c67b579c MK |
2104 | \r |
| 2105 | /**\r | |
| 2106 | Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.\r | |
| 2107 | \r | |
| 2108 | @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL0 (0x0000073F)\r | |
| 2109 | @param EAX Lower 32-bits of MSR value.\r | |
| 2110 | @param EDX Upper 32-bits of MSR value.\r | |
| 2111 | \r | |
| 2112 | <b>Example usage</b>\r | |
| 2113 | @code\r | |
| 2114 | UINT64 Msr;\r | |
| 2115 | \r | |
| 2116 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0);\r | |
| 2117 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr);\r | |
| 2118 | @endcode\r | |
| a73ab083 | 2119 | @note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 2120 | **/\r |
| 2f88bd3a | 2121 | #define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F\r |
| c67b579c MK |
2122 | \r |
| 2123 | /**\r | |
| 2124 | Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.\r | |
| 2125 | \r | |
| 2126 | @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL1 (0x00000740)\r | |
| 2127 | @param EAX Lower 32-bits of MSR value.\r | |
| 2128 | @param EDX Upper 32-bits of MSR value.\r | |
| 2129 | \r | |
| 2130 | <b>Example usage</b>\r | |
| 2131 | @code\r | |
| 2132 | UINT64 Msr;\r | |
| 2133 | \r | |
| 2134 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1);\r | |
| 2135 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr);\r | |
| 2136 | @endcode\r | |
| a73ab083 | 2137 | @note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 2138 | **/\r |
| 2f88bd3a | 2139 | #define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740\r |
| c67b579c MK |
2140 | \r |
| 2141 | /**\r | |
| 2142 | Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.\r | |
| 2143 | \r | |
| 2144 | @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL2 (0x00000741)\r | |
| 2145 | @param EAX Lower 32-bits of MSR value.\r | |
| 2146 | @param EDX Upper 32-bits of MSR value.\r | |
| 2147 | \r | |
| 2148 | <b>Example usage</b>\r | |
| 2149 | @code\r | |
| 2150 | UINT64 Msr;\r | |
| 2151 | \r | |
| 2152 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2);\r | |
| 2153 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr);\r | |
| 2154 | @endcode\r | |
| a73ab083 | 2155 | @note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 2156 | **/\r |
| 2f88bd3a | 2157 | #define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741\r |
| c67b579c MK |
2158 | \r |
| 2159 | /**\r | |
| 2160 | Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.\r | |
| 2161 | \r | |
| 2162 | @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL3 (0x00000742)\r | |
| 2163 | @param EAX Lower 32-bits of MSR value.\r | |
| 2164 | @param EDX Upper 32-bits of MSR value.\r | |
| 2165 | \r | |
| 2166 | <b>Example usage</b>\r | |
| 2167 | @code\r | |
| 2168 | UINT64 Msr;\r | |
| 2169 | \r | |
| 2170 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3);\r | |
| 2171 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr);\r | |
| 2172 | @endcode\r | |
| a73ab083 | 2173 | @note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 2174 | **/\r |
| 2f88bd3a | 2175 | #define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742\r |
| c67b579c MK |
2176 | \r |
| 2177 | /**\r | |
| 2178 | Package. Uncore SBo 3 perfmon box-wide filter.\r | |
| 2179 | \r | |
| 2180 | @param ECX MSR_HASWELL_E_S3_PMON_BOX_FILTER (0x00000743)\r | |
| 2181 | @param EAX Lower 32-bits of MSR value.\r | |
| 2182 | @param EDX Upper 32-bits of MSR value.\r | |
| 2183 | \r | |
| 2184 | <b>Example usage</b>\r | |
| 2185 | @code\r | |
| 2186 | UINT64 Msr;\r | |
| 2187 | \r | |
| 2188 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER);\r | |
| 2189 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr);\r | |
| 2190 | @endcode\r | |
| a73ab083 | 2191 | @note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.\r |
| c67b579c | 2192 | **/\r |
| 2f88bd3a | 2193 | #define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743\r |
| c67b579c MK |
2194 | \r |
| 2195 | /**\r | |
| 2196 | Package. Uncore SBo 3 perfmon counter 0.\r | |
| 2197 | \r | |
| 2198 | @param ECX MSR_HASWELL_E_S3_PMON_CTR0 (0x00000744)\r | |
| 2199 | @param EAX Lower 32-bits of MSR value.\r | |
| 2200 | @param EDX Upper 32-bits of MSR value.\r | |
| 2201 | \r | |
| 2202 | <b>Example usage</b>\r | |
| 2203 | @code\r | |
| 2204 | UINT64 Msr;\r | |
| 2205 | \r | |
| 2206 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0);\r | |
| 2207 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr);\r | |
| 2208 | @endcode\r | |
| a73ab083 | 2209 | @note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.\r |
| c67b579c | 2210 | **/\r |
| 2f88bd3a | 2211 | #define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744\r |
| c67b579c MK |
2212 | \r |
| 2213 | /**\r | |
| 2214 | Package. Uncore SBo 3 perfmon counter 1.\r | |
| 2215 | \r | |
| 2216 | @param ECX MSR_HASWELL_E_S3_PMON_CTR1 (0x00000745)\r | |
| 2217 | @param EAX Lower 32-bits of MSR value.\r | |
| 2218 | @param EDX Upper 32-bits of MSR value.\r | |
| 2219 | \r | |
| 2220 | <b>Example usage</b>\r | |
| 2221 | @code\r | |
| 2222 | UINT64 Msr;\r | |
| 2223 | \r | |
| 2224 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1);\r | |
| 2225 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr);\r | |
| 2226 | @endcode\r | |
| a73ab083 | 2227 | @note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.\r |
| c67b579c | 2228 | **/\r |
| 2f88bd3a | 2229 | #define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745\r |
| c67b579c MK |
2230 | \r |
| 2231 | /**\r | |
| 2232 | Package. Uncore SBo 3 perfmon counter 2.\r | |
| 2233 | \r | |
| 2234 | @param ECX MSR_HASWELL_E_S3_PMON_CTR2 (0x00000746)\r | |
| 2235 | @param EAX Lower 32-bits of MSR value.\r | |
| 2236 | @param EDX Upper 32-bits of MSR value.\r | |
| 2237 | \r | |
| 2238 | <b>Example usage</b>\r | |
| 2239 | @code\r | |
| 2240 | UINT64 Msr;\r | |
| 2241 | \r | |
| 2242 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2);\r | |
| 2243 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr);\r | |
| 2244 | @endcode\r | |
| a73ab083 | 2245 | @note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.\r |
| c67b579c | 2246 | **/\r |
| 2f88bd3a | 2247 | #define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746\r |
| c67b579c MK |
2248 | \r |
| 2249 | /**\r | |
| 2250 | Package. Uncore SBo 3 perfmon counter 3.\r | |
| 2251 | \r | |
| 2252 | @param ECX MSR_HASWELL_E_S3_PMON_CTR3 (0x00000747)\r | |
| 2253 | @param EAX Lower 32-bits of MSR value.\r | |
| 2254 | @param EDX Upper 32-bits of MSR value.\r | |
| 2255 | \r | |
| 2256 | <b>Example usage</b>\r | |
| 2257 | @code\r | |
| 2258 | UINT64 Msr;\r | |
| 2259 | \r | |
| 2260 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3);\r | |
| 2261 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr);\r | |
| 2262 | @endcode\r | |
| a73ab083 | 2263 | @note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.\r |
| c67b579c | 2264 | **/\r |
| 2f88bd3a | 2265 | #define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747\r |
| c67b579c MK |
2266 | \r |
| 2267 | /**\r | |
| 2268 | Package. Uncore C-box 0 perfmon for box-wide control.\r | |
| 2269 | \r | |
| 2270 | @param ECX MSR_HASWELL_E_C0_PMON_BOX_CTL (0x00000E00)\r | |
| 2271 | @param EAX Lower 32-bits of MSR value.\r | |
| 2272 | @param EDX Upper 32-bits of MSR value.\r | |
| 2273 | \r | |
| 2274 | <b>Example usage</b>\r | |
| 2275 | @code\r | |
| 2276 | UINT64 Msr;\r | |
| 2277 | \r | |
| 2278 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL);\r | |
| 2279 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr);\r | |
| 2280 | @endcode\r | |
| a73ab083 | 2281 | @note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.\r |
| c67b579c | 2282 | **/\r |
| 2f88bd3a | 2283 | #define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00\r |
| c67b579c MK |
2284 | \r |
| 2285 | /**\r | |
| 2286 | Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.\r | |
| 2287 | \r | |
| 2288 | @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL0 (0x00000E01)\r | |
| 2289 | @param EAX Lower 32-bits of MSR value.\r | |
| 2290 | @param EDX Upper 32-bits of MSR value.\r | |
| 2291 | \r | |
| 2292 | <b>Example usage</b>\r | |
| 2293 | @code\r | |
| 2294 | UINT64 Msr;\r | |
| 2295 | \r | |
| 2296 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0);\r | |
| 2297 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr);\r | |
| 2298 | @endcode\r | |
| a73ab083 | 2299 | @note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 2300 | **/\r |
| 2f88bd3a | 2301 | #define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01\r |
| c67b579c MK |
2302 | \r |
| 2303 | /**\r | |
| 2304 | Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.\r | |
| 2305 | \r | |
| 2306 | @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL1 (0x00000E02)\r | |
| 2307 | @param EAX Lower 32-bits of MSR value.\r | |
| 2308 | @param EDX Upper 32-bits of MSR value.\r | |
| 2309 | \r | |
| 2310 | <b>Example usage</b>\r | |
| 2311 | @code\r | |
| 2312 | UINT64 Msr;\r | |
| 2313 | \r | |
| 2314 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1);\r | |
| 2315 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr);\r | |
| 2316 | @endcode\r | |
| a73ab083 | 2317 | @note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 2318 | **/\r |
| 2f88bd3a | 2319 | #define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02\r |
| c67b579c MK |
2320 | \r |
| 2321 | /**\r | |
| 2322 | Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.\r | |
| 2323 | \r | |
| 2324 | @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL2 (0x00000E03)\r | |
| 2325 | @param EAX Lower 32-bits of MSR value.\r | |
| 2326 | @param EDX Upper 32-bits of MSR value.\r | |
| 2327 | \r | |
| 2328 | <b>Example usage</b>\r | |
| 2329 | @code\r | |
| 2330 | UINT64 Msr;\r | |
| 2331 | \r | |
| 2332 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2);\r | |
| 2333 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr);\r | |
| 2334 | @endcode\r | |
| a73ab083 | 2335 | @note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 2336 | **/\r |
| 2f88bd3a | 2337 | #define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03\r |
| c67b579c MK |
2338 | \r |
| 2339 | /**\r | |
| 2340 | Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.\r | |
| 2341 | \r | |
| 2342 | @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL3 (0x00000E04)\r | |
| 2343 | @param EAX Lower 32-bits of MSR value.\r | |
| 2344 | @param EDX Upper 32-bits of MSR value.\r | |
| 2345 | \r | |
| 2346 | <b>Example usage</b>\r | |
| 2347 | @code\r | |
| 2348 | UINT64 Msr;\r | |
| 2349 | \r | |
| 2350 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3);\r | |
| 2351 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr);\r | |
| 2352 | @endcode\r | |
| a73ab083 | 2353 | @note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 2354 | **/\r |
| 2f88bd3a | 2355 | #define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04\r |
| c67b579c MK |
2356 | \r |
| 2357 | /**\r | |
| 2358 | Package. Uncore C-box 0 perfmon box wide filter 0.\r | |
| 2359 | \r | |
| 2360 | @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER0 (0x00000E05)\r | |
| 2361 | @param EAX Lower 32-bits of MSR value.\r | |
| 2362 | @param EDX Upper 32-bits of MSR value.\r | |
| 2363 | \r | |
| 2364 | <b>Example usage</b>\r | |
| 2365 | @code\r | |
| 2366 | UINT64 Msr;\r | |
| 2367 | \r | |
| 2368 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0);\r | |
| 2369 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr);\r | |
| 2370 | @endcode\r | |
| a73ab083 | 2371 | @note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c | 2372 | **/\r |
| 2f88bd3a | 2373 | #define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05\r |
| c67b579c MK |
2374 | \r |
| 2375 | /**\r | |
| 2376 | Package. Uncore C-box 0 perfmon box wide filter 1.\r | |
| 2377 | \r | |
| 2378 | @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER1 (0x00000E06)\r | |
| 2379 | @param EAX Lower 32-bits of MSR value.\r | |
| 2380 | @param EDX Upper 32-bits of MSR value.\r | |
| 2381 | \r | |
| 2382 | <b>Example usage</b>\r | |
| 2383 | @code\r | |
| 2384 | UINT64 Msr;\r | |
| 2385 | \r | |
| 2386 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1);\r | |
| 2387 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr);\r | |
| 2388 | @endcode\r | |
| a73ab083 | 2389 | @note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c | 2390 | **/\r |
| 2f88bd3a | 2391 | #define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06\r |
| c67b579c MK |
2392 | \r |
| 2393 | /**\r | |
| 2394 | Package. Uncore C-box 0 perfmon box wide status.\r | |
| 2395 | \r | |
| 2396 | @param ECX MSR_HASWELL_E_C0_PMON_BOX_STATUS (0x00000E07)\r | |
| 2397 | @param EAX Lower 32-bits of MSR value.\r | |
| 2398 | @param EDX Upper 32-bits of MSR value.\r | |
| 2399 | \r | |
| 2400 | <b>Example usage</b>\r | |
| 2401 | @code\r | |
| 2402 | UINT64 Msr;\r | |
| 2403 | \r | |
| 2404 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS);\r | |
| 2405 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr);\r | |
| 2406 | @endcode\r | |
| a73ab083 | 2407 | @note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 2408 | **/\r |
| 2f88bd3a | 2409 | #define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07\r |
| c67b579c MK |
2410 | \r |
| 2411 | /**\r | |
| 2412 | Package. Uncore C-box 0 perfmon counter 0.\r | |
| 2413 | \r | |
| 2414 | @param ECX MSR_HASWELL_E_C0_PMON_CTR0 (0x00000E08)\r | |
| 2415 | @param EAX Lower 32-bits of MSR value.\r | |
| 2416 | @param EDX Upper 32-bits of MSR value.\r | |
| 2417 | \r | |
| 2418 | <b>Example usage</b>\r | |
| 2419 | @code\r | |
| 2420 | UINT64 Msr;\r | |
| 2421 | \r | |
| 2422 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0);\r | |
| 2423 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr);\r | |
| 2424 | @endcode\r | |
| a73ab083 | 2425 | @note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r |
| c67b579c | 2426 | **/\r |
| 2f88bd3a | 2427 | #define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08\r |
| c67b579c MK |
2428 | \r |
| 2429 | /**\r | |
| 2430 | Package. Uncore C-box 0 perfmon counter 1.\r | |
| 2431 | \r | |
| 2432 | @param ECX MSR_HASWELL_E_C0_PMON_CTR1 (0x00000E09)\r | |
| 2433 | @param EAX Lower 32-bits of MSR value.\r | |
| 2434 | @param EDX Upper 32-bits of MSR value.\r | |
| 2435 | \r | |
| 2436 | <b>Example usage</b>\r | |
| 2437 | @code\r | |
| 2438 | UINT64 Msr;\r | |
| 2439 | \r | |
| 2440 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1);\r | |
| 2441 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr);\r | |
| 2442 | @endcode\r | |
| a73ab083 | 2443 | @note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r |
| c67b579c | 2444 | **/\r |
| 2f88bd3a | 2445 | #define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09\r |
| c67b579c MK |
2446 | \r |
| 2447 | /**\r | |
| 2448 | Package. Uncore C-box 0 perfmon counter 2.\r | |
| 2449 | \r | |
| 2450 | @param ECX MSR_HASWELL_E_C0_PMON_CTR2 (0x00000E0A)\r | |
| 2451 | @param EAX Lower 32-bits of MSR value.\r | |
| 2452 | @param EDX Upper 32-bits of MSR value.\r | |
| 2453 | \r | |
| 2454 | <b>Example usage</b>\r | |
| 2455 | @code\r | |
| 2456 | UINT64 Msr;\r | |
| 2457 | \r | |
| 2458 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2);\r | |
| 2459 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr);\r | |
| 2460 | @endcode\r | |
| a73ab083 | 2461 | @note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r |
| c67b579c | 2462 | **/\r |
| 2f88bd3a | 2463 | #define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A\r |
| c67b579c MK |
2464 | \r |
| 2465 | /**\r | |
| 2466 | Package. Uncore C-box 0 perfmon counter 3.\r | |
| 2467 | \r | |
| 2468 | @param ECX MSR_HASWELL_E_C0_PMON_CTR3 (0x00000E0B)\r | |
| 2469 | @param EAX Lower 32-bits of MSR value.\r | |
| 2470 | @param EDX Upper 32-bits of MSR value.\r | |
| 2471 | \r | |
| 2472 | <b>Example usage</b>\r | |
| 2473 | @code\r | |
| 2474 | UINT64 Msr;\r | |
| 2475 | \r | |
| 2476 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3);\r | |
| 2477 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr);\r | |
| 2478 | @endcode\r | |
| a73ab083 | 2479 | @note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r |
| c67b579c | 2480 | **/\r |
| 2f88bd3a | 2481 | #define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B\r |
| c67b579c MK |
2482 | \r |
| 2483 | /**\r | |
| 2484 | Package. Uncore C-box 1 perfmon for box-wide control.\r | |
| 2485 | \r | |
| 2486 | @param ECX MSR_HASWELL_E_C1_PMON_BOX_CTL (0x00000E10)\r | |
| 2487 | @param EAX Lower 32-bits of MSR value.\r | |
| 2488 | @param EDX Upper 32-bits of MSR value.\r | |
| 2489 | \r | |
| 2490 | <b>Example usage</b>\r | |
| 2491 | @code\r | |
| 2492 | UINT64 Msr;\r | |
| 2493 | \r | |
| 2494 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL);\r | |
| 2495 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr);\r | |
| 2496 | @endcode\r | |
| a73ab083 | 2497 | @note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.\r |
| c67b579c | 2498 | **/\r |
| 2f88bd3a | 2499 | #define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10\r |
| c67b579c MK |
2500 | \r |
| 2501 | /**\r | |
| 2502 | Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.\r | |
| 2503 | \r | |
| 2504 | @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL0 (0x00000E11)\r | |
| 2505 | @param EAX Lower 32-bits of MSR value.\r | |
| 2506 | @param EDX Upper 32-bits of MSR value.\r | |
| 2507 | \r | |
| 2508 | <b>Example usage</b>\r | |
| 2509 | @code\r | |
| 2510 | UINT64 Msr;\r | |
| 2511 | \r | |
| 2512 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0);\r | |
| 2513 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr);\r | |
| 2514 | @endcode\r | |
| a73ab083 | 2515 | @note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 2516 | **/\r |
| 2f88bd3a | 2517 | #define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11\r |
| c67b579c MK |
2518 | \r |
| 2519 | /**\r | |
| 2520 | Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.\r | |
| 2521 | \r | |
| 2522 | @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL1 (0x00000E12)\r | |
| 2523 | @param EAX Lower 32-bits of MSR value.\r | |
| 2524 | @param EDX Upper 32-bits of MSR value.\r | |
| 2525 | \r | |
| 2526 | <b>Example usage</b>\r | |
| 2527 | @code\r | |
| 2528 | UINT64 Msr;\r | |
| 2529 | \r | |
| 2530 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1);\r | |
| 2531 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr);\r | |
| 2532 | @endcode\r | |
| a73ab083 | 2533 | @note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 2534 | **/\r |
| 2f88bd3a | 2535 | #define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12\r |
| c67b579c MK |
2536 | \r |
| 2537 | /**\r | |
| 2538 | Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.\r | |
| 2539 | \r | |
| 2540 | @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL2 (0x00000E13)\r | |
| 2541 | @param EAX Lower 32-bits of MSR value.\r | |
| 2542 | @param EDX Upper 32-bits of MSR value.\r | |
| 2543 | \r | |
| 2544 | <b>Example usage</b>\r | |
| 2545 | @code\r | |
| 2546 | UINT64 Msr;\r | |
| 2547 | \r | |
| 2548 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2);\r | |
| 2549 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr);\r | |
| 2550 | @endcode\r | |
| a73ab083 | 2551 | @note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 2552 | **/\r |
| 2f88bd3a | 2553 | #define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13\r |
| c67b579c MK |
2554 | \r |
| 2555 | /**\r | |
| 2556 | Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.\r | |
| 2557 | \r | |
| 2558 | @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL3 (0x00000E14)\r | |
| 2559 | @param EAX Lower 32-bits of MSR value.\r | |
| 2560 | @param EDX Upper 32-bits of MSR value.\r | |
| 2561 | \r | |
| 2562 | <b>Example usage</b>\r | |
| 2563 | @code\r | |
| 2564 | UINT64 Msr;\r | |
| 2565 | \r | |
| 2566 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3);\r | |
| 2567 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr);\r | |
| 2568 | @endcode\r | |
| a73ab083 | 2569 | @note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 2570 | **/\r |
| 2f88bd3a | 2571 | #define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14\r |
| c67b579c MK |
2572 | \r |
| 2573 | /**\r | |
| 2574 | Package. Uncore C-box 1 perfmon box wide filter 0.\r | |
| 2575 | \r | |
| 2576 | @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER0 (0x00000E15)\r | |
| 2577 | @param EAX Lower 32-bits of MSR value.\r | |
| 2578 | @param EDX Upper 32-bits of MSR value.\r | |
| 2579 | \r | |
| 2580 | <b>Example usage</b>\r | |
| 2581 | @code\r | |
| 2582 | UINT64 Msr;\r | |
| 2583 | \r | |
| 2584 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0);\r | |
| 2585 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr);\r | |
| 2586 | @endcode\r | |
| a73ab083 | 2587 | @note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c | 2588 | **/\r |
| 2f88bd3a | 2589 | #define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15\r |
| c67b579c MK |
2590 | \r |
| 2591 | /**\r | |
| 2592 | Package. Uncore C-box 1 perfmon box wide filter1.\r | |
| 2593 | \r | |
| 2594 | @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER1 (0x00000E16)\r | |
| 2595 | @param EAX Lower 32-bits of MSR value.\r | |
| 2596 | @param EDX Upper 32-bits of MSR value.\r | |
| 2597 | \r | |
| 2598 | <b>Example usage</b>\r | |
| 2599 | @code\r | |
| 2600 | UINT64 Msr;\r | |
| 2601 | \r | |
| 2602 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1);\r | |
| 2603 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr);\r | |
| 2604 | @endcode\r | |
| a73ab083 | 2605 | @note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c | 2606 | **/\r |
| 2f88bd3a | 2607 | #define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16\r |
| c67b579c MK |
2608 | \r |
| 2609 | /**\r | |
| 2610 | Package. Uncore C-box 1 perfmon box wide status.\r | |
| 2611 | \r | |
| 2612 | @param ECX MSR_HASWELL_E_C1_PMON_BOX_STATUS (0x00000E17)\r | |
| 2613 | @param EAX Lower 32-bits of MSR value.\r | |
| 2614 | @param EDX Upper 32-bits of MSR value.\r | |
| 2615 | \r | |
| 2616 | <b>Example usage</b>\r | |
| 2617 | @code\r | |
| 2618 | UINT64 Msr;\r | |
| 2619 | \r | |
| 2620 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS);\r | |
| 2621 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr);\r | |
| 2622 | @endcode\r | |
| a73ab083 | 2623 | @note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 2624 | **/\r |
| 2f88bd3a | 2625 | #define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17\r |
| c67b579c MK |
2626 | \r |
| 2627 | /**\r | |
| 2628 | Package. Uncore C-box 1 perfmon counter 0.\r | |
| 2629 | \r | |
| 2630 | @param ECX MSR_HASWELL_E_C1_PMON_CTR0 (0x00000E18)\r | |
| 2631 | @param EAX Lower 32-bits of MSR value.\r | |
| 2632 | @param EDX Upper 32-bits of MSR value.\r | |
| 2633 | \r | |
| 2634 | <b>Example usage</b>\r | |
| 2635 | @code\r | |
| 2636 | UINT64 Msr;\r | |
| 2637 | \r | |
| 2638 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0);\r | |
| 2639 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr);\r | |
| 2640 | @endcode\r | |
| a73ab083 | 2641 | @note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r |
| c67b579c | 2642 | **/\r |
| 2f88bd3a | 2643 | #define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18\r |
| c67b579c MK |
2644 | \r |
| 2645 | /**\r | |
| 2646 | Package. Uncore C-box 1 perfmon counter 1.\r | |
| 2647 | \r | |
| 2648 | @param ECX MSR_HASWELL_E_C1_PMON_CTR1 (0x00000E19)\r | |
| 2649 | @param EAX Lower 32-bits of MSR value.\r | |
| 2650 | @param EDX Upper 32-bits of MSR value.\r | |
| 2651 | \r | |
| 2652 | <b>Example usage</b>\r | |
| 2653 | @code\r | |
| 2654 | UINT64 Msr;\r | |
| 2655 | \r | |
| 2656 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1);\r | |
| 2657 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr);\r | |
| 2658 | @endcode\r | |
| a73ab083 | 2659 | @note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r |
| c67b579c | 2660 | **/\r |
| 2f88bd3a | 2661 | #define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19\r |
| c67b579c MK |
2662 | \r |
| 2663 | /**\r | |
| 2664 | Package. Uncore C-box 1 perfmon counter 2.\r | |
| 2665 | \r | |
| 2666 | @param ECX MSR_HASWELL_E_C1_PMON_CTR2 (0x00000E1A)\r | |
| 2667 | @param EAX Lower 32-bits of MSR value.\r | |
| 2668 | @param EDX Upper 32-bits of MSR value.\r | |
| 2669 | \r | |
| 2670 | <b>Example usage</b>\r | |
| 2671 | @code\r | |
| 2672 | UINT64 Msr;\r | |
| 2673 | \r | |
| 2674 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2);\r | |
| 2675 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr);\r | |
| 2676 | @endcode\r | |
| a73ab083 | 2677 | @note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r |
| c67b579c | 2678 | **/\r |
| 2f88bd3a | 2679 | #define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A\r |
| c67b579c MK |
2680 | \r |
| 2681 | /**\r | |
| 2682 | Package. Uncore C-box 1 perfmon counter 3.\r | |
| 2683 | \r | |
| 2684 | @param ECX MSR_HASWELL_E_C1_PMON_CTR3 (0x00000E1B)\r | |
| 2685 | @param EAX Lower 32-bits of MSR value.\r | |
| 2686 | @param EDX Upper 32-bits of MSR value.\r | |
| 2687 | \r | |
| 2688 | <b>Example usage</b>\r | |
| 2689 | @code\r | |
| 2690 | UINT64 Msr;\r | |
| 2691 | \r | |
| 2692 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3);\r | |
| 2693 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr);\r | |
| 2694 | @endcode\r | |
| a73ab083 | 2695 | @note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r |
| c67b579c | 2696 | **/\r |
| 2f88bd3a | 2697 | #define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B\r |
| c67b579c MK |
2698 | \r |
| 2699 | /**\r | |
| 2700 | Package. Uncore C-box 2 perfmon for box-wide control.\r | |
| 2701 | \r | |
| 2702 | @param ECX MSR_HASWELL_E_C2_PMON_BOX_CTL (0x00000E20)\r | |
| 2703 | @param EAX Lower 32-bits of MSR value.\r | |
| 2704 | @param EDX Upper 32-bits of MSR value.\r | |
| 2705 | \r | |
| 2706 | <b>Example usage</b>\r | |
| 2707 | @code\r | |
| 2708 | UINT64 Msr;\r | |
| 2709 | \r | |
| 2710 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL);\r | |
| 2711 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr);\r | |
| 2712 | @endcode\r | |
| a73ab083 | 2713 | @note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.\r |
| c67b579c | 2714 | **/\r |
| 2f88bd3a | 2715 | #define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20\r |
| c67b579c MK |
2716 | \r |
| 2717 | /**\r | |
| 2718 | Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.\r | |
| 2719 | \r | |
| 2720 | @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL0 (0x00000E21)\r | |
| 2721 | @param EAX Lower 32-bits of MSR value.\r | |
| 2722 | @param EDX Upper 32-bits of MSR value.\r | |
| 2723 | \r | |
| 2724 | <b>Example usage</b>\r | |
| 2725 | @code\r | |
| 2726 | UINT64 Msr;\r | |
| 2727 | \r | |
| 2728 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0);\r | |
| 2729 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr);\r | |
| 2730 | @endcode\r | |
| a73ab083 | 2731 | @note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 2732 | **/\r |
| 2f88bd3a | 2733 | #define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21\r |
| c67b579c MK |
2734 | \r |
| 2735 | /**\r | |
| 2736 | Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.\r | |
| 2737 | \r | |
| 2738 | @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL1 (0x00000E22)\r | |
| 2739 | @param EAX Lower 32-bits of MSR value.\r | |
| 2740 | @param EDX Upper 32-bits of MSR value.\r | |
| 2741 | \r | |
| 2742 | <b>Example usage</b>\r | |
| 2743 | @code\r | |
| 2744 | UINT64 Msr;\r | |
| 2745 | \r | |
| 2746 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1);\r | |
| 2747 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr);\r | |
| 2748 | @endcode\r | |
| a73ab083 | 2749 | @note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 2750 | **/\r |
| 2f88bd3a | 2751 | #define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22\r |
| c67b579c MK |
2752 | \r |
| 2753 | /**\r | |
| 2754 | Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.\r | |
| 2755 | \r | |
| 2756 | @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL2 (0x00000E23)\r | |
| 2757 | @param EAX Lower 32-bits of MSR value.\r | |
| 2758 | @param EDX Upper 32-bits of MSR value.\r | |
| 2759 | \r | |
| 2760 | <b>Example usage</b>\r | |
| 2761 | @code\r | |
| 2762 | UINT64 Msr;\r | |
| 2763 | \r | |
| 2764 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2);\r | |
| 2765 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr);\r | |
| 2766 | @endcode\r | |
| a73ab083 | 2767 | @note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 2768 | **/\r |
| 2f88bd3a | 2769 | #define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23\r |
| c67b579c MK |
2770 | \r |
| 2771 | /**\r | |
| 2772 | Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.\r | |
| 2773 | \r | |
| 2774 | @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL3 (0x00000E24)\r | |
| 2775 | @param EAX Lower 32-bits of MSR value.\r | |
| 2776 | @param EDX Upper 32-bits of MSR value.\r | |
| 2777 | \r | |
| 2778 | <b>Example usage</b>\r | |
| 2779 | @code\r | |
| 2780 | UINT64 Msr;\r | |
| 2781 | \r | |
| 2782 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3);\r | |
| 2783 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr);\r | |
| 2784 | @endcode\r | |
| a73ab083 | 2785 | @note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 2786 | **/\r |
| 2f88bd3a | 2787 | #define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24\r |
| c67b579c MK |
2788 | \r |
| 2789 | /**\r | |
| 2790 | Package. Uncore C-box 2 perfmon box wide filter 0.\r | |
| 2791 | \r | |
| 2792 | @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER0 (0x00000E25)\r | |
| 2793 | @param EAX Lower 32-bits of MSR value.\r | |
| 2794 | @param EDX Upper 32-bits of MSR value.\r | |
| 2795 | \r | |
| 2796 | <b>Example usage</b>\r | |
| 2797 | @code\r | |
| 2798 | UINT64 Msr;\r | |
| 2799 | \r | |
| 2800 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0);\r | |
| 2801 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr);\r | |
| 2802 | @endcode\r | |
| a73ab083 | 2803 | @note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c | 2804 | **/\r |
| 2f88bd3a | 2805 | #define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25\r |
| c67b579c MK |
2806 | \r |
| 2807 | /**\r | |
| 2808 | Package. Uncore C-box 2 perfmon box wide filter1.\r | |
| 2809 | \r | |
| 2810 | @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER1 (0x00000E26)\r | |
| 2811 | @param EAX Lower 32-bits of MSR value.\r | |
| 2812 | @param EDX Upper 32-bits of MSR value.\r | |
| 2813 | \r | |
| 2814 | <b>Example usage</b>\r | |
| 2815 | @code\r | |
| 2816 | UINT64 Msr;\r | |
| 2817 | \r | |
| 2818 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1);\r | |
| 2819 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr);\r | |
| 2820 | @endcode\r | |
| a73ab083 | 2821 | @note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c | 2822 | **/\r |
| 2f88bd3a | 2823 | #define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26\r |
| c67b579c MK |
2824 | \r |
| 2825 | /**\r | |
| 2826 | Package. Uncore C-box 2 perfmon box wide status.\r | |
| 2827 | \r | |
| 2828 | @param ECX MSR_HASWELL_E_C2_PMON_BOX_STATUS (0x00000E27)\r | |
| 2829 | @param EAX Lower 32-bits of MSR value.\r | |
| 2830 | @param EDX Upper 32-bits of MSR value.\r | |
| 2831 | \r | |
| 2832 | <b>Example usage</b>\r | |
| 2833 | @code\r | |
| 2834 | UINT64 Msr;\r | |
| 2835 | \r | |
| 2836 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS);\r | |
| 2837 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr);\r | |
| 2838 | @endcode\r | |
| a73ab083 | 2839 | @note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 2840 | **/\r |
| 2f88bd3a | 2841 | #define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27\r |
| c67b579c MK |
2842 | \r |
| 2843 | /**\r | |
| 2844 | Package. Uncore C-box 2 perfmon counter 0.\r | |
| 2845 | \r | |
| 2846 | @param ECX MSR_HASWELL_E_C2_PMON_CTR0 (0x00000E28)\r | |
| 2847 | @param EAX Lower 32-bits of MSR value.\r | |
| 2848 | @param EDX Upper 32-bits of MSR value.\r | |
| 2849 | \r | |
| 2850 | <b>Example usage</b>\r | |
| 2851 | @code\r | |
| 2852 | UINT64 Msr;\r | |
| 2853 | \r | |
| 2854 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0);\r | |
| 2855 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr);\r | |
| 2856 | @endcode\r | |
| a73ab083 | 2857 | @note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r |
| c67b579c | 2858 | **/\r |
| 2f88bd3a | 2859 | #define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28\r |
| c67b579c MK |
2860 | \r |
| 2861 | /**\r | |
| 2862 | Package. Uncore C-box 2 perfmon counter 1.\r | |
| 2863 | \r | |
| 2864 | @param ECX MSR_HASWELL_E_C2_PMON_CTR1 (0x00000E29)\r | |
| 2865 | @param EAX Lower 32-bits of MSR value.\r | |
| 2866 | @param EDX Upper 32-bits of MSR value.\r | |
| 2867 | \r | |
| 2868 | <b>Example usage</b>\r | |
| 2869 | @code\r | |
| 2870 | UINT64 Msr;\r | |
| 2871 | \r | |
| 2872 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1);\r | |
| 2873 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr);\r | |
| 2874 | @endcode\r | |
| a73ab083 | 2875 | @note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r |
| c67b579c | 2876 | **/\r |
| 2f88bd3a | 2877 | #define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29\r |
| c67b579c MK |
2878 | \r |
| 2879 | /**\r | |
| 2880 | Package. Uncore C-box 2 perfmon counter 2.\r | |
| 2881 | \r | |
| 2882 | @param ECX MSR_HASWELL_E_C2_PMON_CTR2 (0x00000E2A)\r | |
| 2883 | @param EAX Lower 32-bits of MSR value.\r | |
| 2884 | @param EDX Upper 32-bits of MSR value.\r | |
| 2885 | \r | |
| 2886 | <b>Example usage</b>\r | |
| 2887 | @code\r | |
| 2888 | UINT64 Msr;\r | |
| 2889 | \r | |
| 2890 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2);\r | |
| 2891 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr);\r | |
| 2892 | @endcode\r | |
| a73ab083 | 2893 | @note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r |
| c67b579c | 2894 | **/\r |
| 2f88bd3a | 2895 | #define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A\r |
| c67b579c MK |
2896 | \r |
| 2897 | /**\r | |
| 2898 | Package. Uncore C-box 2 perfmon counter 3.\r | |
| 2899 | \r | |
| 2900 | @param ECX MSR_HASWELL_E_C2_PMON_CTR3 (0x00000E2B)\r | |
| 2901 | @param EAX Lower 32-bits of MSR value.\r | |
| 2902 | @param EDX Upper 32-bits of MSR value.\r | |
| 2903 | \r | |
| 2904 | <b>Example usage</b>\r | |
| 2905 | @code\r | |
| 2906 | UINT64 Msr;\r | |
| 2907 | \r | |
| 2908 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3);\r | |
| 2909 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr);\r | |
| 2910 | @endcode\r | |
| a73ab083 | 2911 | @note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r |
| c67b579c | 2912 | **/\r |
| 2f88bd3a | 2913 | #define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B\r |
| c67b579c MK |
2914 | \r |
| 2915 | /**\r | |
| 2916 | Package. Uncore C-box 3 perfmon for box-wide control.\r | |
| 2917 | \r | |
| 2918 | @param ECX MSR_HASWELL_E_C3_PMON_BOX_CTL (0x00000E30)\r | |
| 2919 | @param EAX Lower 32-bits of MSR value.\r | |
| 2920 | @param EDX Upper 32-bits of MSR value.\r | |
| 2921 | \r | |
| 2922 | <b>Example usage</b>\r | |
| 2923 | @code\r | |
| 2924 | UINT64 Msr;\r | |
| 2925 | \r | |
| 2926 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL);\r | |
| 2927 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr);\r | |
| 2928 | @endcode\r | |
| a73ab083 | 2929 | @note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.\r |
| c67b579c | 2930 | **/\r |
| 2f88bd3a | 2931 | #define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30\r |
| c67b579c MK |
2932 | \r |
| 2933 | /**\r | |
| 2934 | Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.\r | |
| 2935 | \r | |
| 2936 | @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL0 (0x00000E31)\r | |
| 2937 | @param EAX Lower 32-bits of MSR value.\r | |
| 2938 | @param EDX Upper 32-bits of MSR value.\r | |
| 2939 | \r | |
| 2940 | <b>Example usage</b>\r | |
| 2941 | @code\r | |
| 2942 | UINT64 Msr;\r | |
| 2943 | \r | |
| 2944 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0);\r | |
| 2945 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr);\r | |
| 2946 | @endcode\r | |
| a73ab083 | 2947 | @note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 2948 | **/\r |
| 2f88bd3a | 2949 | #define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31\r |
| c67b579c MK |
2950 | \r |
| 2951 | /**\r | |
| 2952 | Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.\r | |
| 2953 | \r | |
| 2954 | @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL1 (0x00000E32)\r | |
| 2955 | @param EAX Lower 32-bits of MSR value.\r | |
| 2956 | @param EDX Upper 32-bits of MSR value.\r | |
| 2957 | \r | |
| 2958 | <b>Example usage</b>\r | |
| 2959 | @code\r | |
| 2960 | UINT64 Msr;\r | |
| 2961 | \r | |
| 2962 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1);\r | |
| 2963 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr);\r | |
| 2964 | @endcode\r | |
| a73ab083 | 2965 | @note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 2966 | **/\r |
| 2f88bd3a | 2967 | #define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32\r |
| c67b579c MK |
2968 | \r |
| 2969 | /**\r | |
| 2970 | Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.\r | |
| 2971 | \r | |
| 2972 | @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL2 (0x00000E33)\r | |
| 2973 | @param EAX Lower 32-bits of MSR value.\r | |
| 2974 | @param EDX Upper 32-bits of MSR value.\r | |
| 2975 | \r | |
| 2976 | <b>Example usage</b>\r | |
| 2977 | @code\r | |
| 2978 | UINT64 Msr;\r | |
| 2979 | \r | |
| 2980 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2);\r | |
| 2981 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr);\r | |
| 2982 | @endcode\r | |
| a73ab083 | 2983 | @note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 2984 | **/\r |
| 2f88bd3a | 2985 | #define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33\r |
| c67b579c MK |
2986 | \r |
| 2987 | /**\r | |
| 2988 | Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.\r | |
| 2989 | \r | |
| 2990 | @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL3 (0x00000E34)\r | |
| 2991 | @param EAX Lower 32-bits of MSR value.\r | |
| 2992 | @param EDX Upper 32-bits of MSR value.\r | |
| 2993 | \r | |
| 2994 | <b>Example usage</b>\r | |
| 2995 | @code\r | |
| 2996 | UINT64 Msr;\r | |
| 2997 | \r | |
| 2998 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3);\r | |
| 2999 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr);\r | |
| 3000 | @endcode\r | |
| a73ab083 | 3001 | @note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 3002 | **/\r |
| 2f88bd3a | 3003 | #define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34\r |
| c67b579c MK |
3004 | \r |
| 3005 | /**\r | |
| 3006 | Package. Uncore C-box 3 perfmon box wide filter 0.\r | |
| 3007 | \r | |
| 3008 | @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER0 (0x00000E35)\r | |
| 3009 | @param EAX Lower 32-bits of MSR value.\r | |
| 3010 | @param EDX Upper 32-bits of MSR value.\r | |
| 3011 | \r | |
| 3012 | <b>Example usage</b>\r | |
| 3013 | @code\r | |
| 3014 | UINT64 Msr;\r | |
| 3015 | \r | |
| 3016 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0);\r | |
| 3017 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr);\r | |
| 3018 | @endcode\r | |
| a73ab083 | 3019 | @note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c | 3020 | **/\r |
| 2f88bd3a | 3021 | #define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35\r |
| c67b579c MK |
3022 | \r |
| 3023 | /**\r | |
| 3024 | Package. Uncore C-box 3 perfmon box wide filter1.\r | |
| 3025 | \r | |
| 3026 | @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER1 (0x00000E36)\r | |
| 3027 | @param EAX Lower 32-bits of MSR value.\r | |
| 3028 | @param EDX Upper 32-bits of MSR value.\r | |
| 3029 | \r | |
| 3030 | <b>Example usage</b>\r | |
| 3031 | @code\r | |
| 3032 | UINT64 Msr;\r | |
| 3033 | \r | |
| 3034 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1);\r | |
| 3035 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr);\r | |
| 3036 | @endcode\r | |
| a73ab083 | 3037 | @note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c | 3038 | **/\r |
| 2f88bd3a | 3039 | #define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36\r |
| c67b579c MK |
3040 | \r |
| 3041 | /**\r | |
| 3042 | Package. Uncore C-box 3 perfmon box wide status.\r | |
| 3043 | \r | |
| 3044 | @param ECX MSR_HASWELL_E_C3_PMON_BOX_STATUS (0x00000E37)\r | |
| 3045 | @param EAX Lower 32-bits of MSR value.\r | |
| 3046 | @param EDX Upper 32-bits of MSR value.\r | |
| 3047 | \r | |
| 3048 | <b>Example usage</b>\r | |
| 3049 | @code\r | |
| 3050 | UINT64 Msr;\r | |
| 3051 | \r | |
| 3052 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS);\r | |
| 3053 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr);\r | |
| 3054 | @endcode\r | |
| a73ab083 | 3055 | @note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 3056 | **/\r |
| 2f88bd3a | 3057 | #define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37\r |
| c67b579c MK |
3058 | \r |
| 3059 | /**\r | |
| 3060 | Package. Uncore C-box 3 perfmon counter 0.\r | |
| 3061 | \r | |
| 3062 | @param ECX MSR_HASWELL_E_C3_PMON_CTR0 (0x00000E38)\r | |
| 3063 | @param EAX Lower 32-bits of MSR value.\r | |
| 3064 | @param EDX Upper 32-bits of MSR value.\r | |
| 3065 | \r | |
| 3066 | <b>Example usage</b>\r | |
| 3067 | @code\r | |
| 3068 | UINT64 Msr;\r | |
| 3069 | \r | |
| 3070 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0);\r | |
| 3071 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr);\r | |
| 3072 | @endcode\r | |
| a73ab083 | 3073 | @note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r |
| c67b579c | 3074 | **/\r |
| 2f88bd3a | 3075 | #define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38\r |
| c67b579c MK |
3076 | \r |
| 3077 | /**\r | |
| 3078 | Package. Uncore C-box 3 perfmon counter 1.\r | |
| 3079 | \r | |
| 3080 | @param ECX MSR_HASWELL_E_C3_PMON_CTR1 (0x00000E39)\r | |
| 3081 | @param EAX Lower 32-bits of MSR value.\r | |
| 3082 | @param EDX Upper 32-bits of MSR value.\r | |
| 3083 | \r | |
| 3084 | <b>Example usage</b>\r | |
| 3085 | @code\r | |
| 3086 | UINT64 Msr;\r | |
| 3087 | \r | |
| 3088 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1);\r | |
| 3089 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr);\r | |
| 3090 | @endcode\r | |
| a73ab083 | 3091 | @note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r |
| c67b579c | 3092 | **/\r |
| 2f88bd3a | 3093 | #define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39\r |
| c67b579c MK |
3094 | \r |
| 3095 | /**\r | |
| 3096 | Package. Uncore C-box 3 perfmon counter 2.\r | |
| 3097 | \r | |
| 3098 | @param ECX MSR_HASWELL_E_C3_PMON_CTR2 (0x00000E3A)\r | |
| 3099 | @param EAX Lower 32-bits of MSR value.\r | |
| 3100 | @param EDX Upper 32-bits of MSR value.\r | |
| 3101 | \r | |
| 3102 | <b>Example usage</b>\r | |
| 3103 | @code\r | |
| 3104 | UINT64 Msr;\r | |
| 3105 | \r | |
| 3106 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2);\r | |
| 3107 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr);\r | |
| 3108 | @endcode\r | |
| a73ab083 | 3109 | @note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r |
| c67b579c | 3110 | **/\r |
| 2f88bd3a | 3111 | #define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A\r |
| c67b579c MK |
3112 | \r |
| 3113 | /**\r | |
| 3114 | Package. Uncore C-box 3 perfmon counter 3.\r | |
| 3115 | \r | |
| 3116 | @param ECX MSR_HASWELL_E_C3_PMON_CTR3 (0x00000E3B)\r | |
| 3117 | @param EAX Lower 32-bits of MSR value.\r | |
| 3118 | @param EDX Upper 32-bits of MSR value.\r | |
| 3119 | \r | |
| 3120 | <b>Example usage</b>\r | |
| 3121 | @code\r | |
| 3122 | UINT64 Msr;\r | |
| 3123 | \r | |
| 3124 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3);\r | |
| 3125 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr);\r | |
| 3126 | @endcode\r | |
| a73ab083 | 3127 | @note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r |
| c67b579c | 3128 | **/\r |
| 2f88bd3a | 3129 | #define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B\r |
| c67b579c MK |
3130 | \r |
| 3131 | /**\r | |
| 3132 | Package. Uncore C-box 4 perfmon for box-wide control.\r | |
| 3133 | \r | |
| 3134 | @param ECX MSR_HASWELL_E_C4_PMON_BOX_CTL (0x00000E40)\r | |
| 3135 | @param EAX Lower 32-bits of MSR value.\r | |
| 3136 | @param EDX Upper 32-bits of MSR value.\r | |
| 3137 | \r | |
| 3138 | <b>Example usage</b>\r | |
| 3139 | @code\r | |
| 3140 | UINT64 Msr;\r | |
| 3141 | \r | |
| 3142 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL);\r | |
| 3143 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr);\r | |
| 3144 | @endcode\r | |
| a73ab083 | 3145 | @note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.\r |
| c67b579c | 3146 | **/\r |
| 2f88bd3a | 3147 | #define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40\r |
| c67b579c MK |
3148 | \r |
| 3149 | /**\r | |
| 3150 | Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.\r | |
| 3151 | \r | |
| 3152 | @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL0 (0x00000E41)\r | |
| 3153 | @param EAX Lower 32-bits of MSR value.\r | |
| 3154 | @param EDX Upper 32-bits of MSR value.\r | |
| 3155 | \r | |
| 3156 | <b>Example usage</b>\r | |
| 3157 | @code\r | |
| 3158 | UINT64 Msr;\r | |
| 3159 | \r | |
| 3160 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0);\r | |
| 3161 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr);\r | |
| 3162 | @endcode\r | |
| a73ab083 | 3163 | @note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 3164 | **/\r |
| 2f88bd3a | 3165 | #define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41\r |
| c67b579c MK |
3166 | \r |
| 3167 | /**\r | |
| 3168 | Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.\r | |
| 3169 | \r | |
| 3170 | @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL1 (0x00000E42)\r | |
| 3171 | @param EAX Lower 32-bits of MSR value.\r | |
| 3172 | @param EDX Upper 32-bits of MSR value.\r | |
| 3173 | \r | |
| 3174 | <b>Example usage</b>\r | |
| 3175 | @code\r | |
| 3176 | UINT64 Msr;\r | |
| 3177 | \r | |
| 3178 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1);\r | |
| 3179 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr);\r | |
| 3180 | @endcode\r | |
| a73ab083 | 3181 | @note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 3182 | **/\r |
| 2f88bd3a | 3183 | #define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42\r |
| c67b579c MK |
3184 | \r |
| 3185 | /**\r | |
| 3186 | Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.\r | |
| 3187 | \r | |
| 3188 | @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL2 (0x00000E43)\r | |
| 3189 | @param EAX Lower 32-bits of MSR value.\r | |
| 3190 | @param EDX Upper 32-bits of MSR value.\r | |
| 3191 | \r | |
| 3192 | <b>Example usage</b>\r | |
| 3193 | @code\r | |
| 3194 | UINT64 Msr;\r | |
| 3195 | \r | |
| 3196 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2);\r | |
| 3197 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr);\r | |
| 3198 | @endcode\r | |
| a73ab083 | 3199 | @note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 3200 | **/\r |
| 2f88bd3a | 3201 | #define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43\r |
| c67b579c MK |
3202 | \r |
| 3203 | /**\r | |
| 3204 | Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.\r | |
| 3205 | \r | |
| 3206 | @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL3 (0x00000E44)\r | |
| 3207 | @param EAX Lower 32-bits of MSR value.\r | |
| 3208 | @param EDX Upper 32-bits of MSR value.\r | |
| 3209 | \r | |
| 3210 | <b>Example usage</b>\r | |
| 3211 | @code\r | |
| 3212 | UINT64 Msr;\r | |
| 3213 | \r | |
| 3214 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3);\r | |
| 3215 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr);\r | |
| 3216 | @endcode\r | |
| a73ab083 | 3217 | @note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 3218 | **/\r |
| 2f88bd3a | 3219 | #define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44\r |
| c67b579c MK |
3220 | \r |
| 3221 | /**\r | |
| 3222 | Package. Uncore C-box 4 perfmon box wide filter 0.\r | |
| 3223 | \r | |
| 3224 | @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER0 (0x00000E45)\r | |
| 3225 | @param EAX Lower 32-bits of MSR value.\r | |
| 3226 | @param EDX Upper 32-bits of MSR value.\r | |
| 3227 | \r | |
| 3228 | <b>Example usage</b>\r | |
| 3229 | @code\r | |
| 3230 | UINT64 Msr;\r | |
| 3231 | \r | |
| 3232 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0);\r | |
| 3233 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr);\r | |
| 3234 | @endcode\r | |
| a73ab083 | 3235 | @note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c | 3236 | **/\r |
| 2f88bd3a | 3237 | #define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45\r |
| c67b579c MK |
3238 | \r |
| 3239 | /**\r | |
| 3240 | Package. Uncore C-box 4 perfmon box wide filter1.\r | |
| 3241 | \r | |
| 3242 | @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER1 (0x00000E46)\r | |
| 3243 | @param EAX Lower 32-bits of MSR value.\r | |
| 3244 | @param EDX Upper 32-bits of MSR value.\r | |
| 3245 | \r | |
| 3246 | <b>Example usage</b>\r | |
| 3247 | @code\r | |
| 3248 | UINT64 Msr;\r | |
| 3249 | \r | |
| 3250 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1);\r | |
| 3251 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr);\r | |
| 3252 | @endcode\r | |
| a73ab083 | 3253 | @note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c | 3254 | **/\r |
| 2f88bd3a | 3255 | #define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46\r |
| c67b579c MK |
3256 | \r |
| 3257 | /**\r | |
| 3258 | Package. Uncore C-box 4 perfmon box wide status.\r | |
| 3259 | \r | |
| 3260 | @param ECX MSR_HASWELL_E_C4_PMON_BOX_STATUS (0x00000E47)\r | |
| 3261 | @param EAX Lower 32-bits of MSR value.\r | |
| 3262 | @param EDX Upper 32-bits of MSR value.\r | |
| 3263 | \r | |
| 3264 | <b>Example usage</b>\r | |
| 3265 | @code\r | |
| 3266 | UINT64 Msr;\r | |
| 3267 | \r | |
| 3268 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS);\r | |
| 3269 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr);\r | |
| 3270 | @endcode\r | |
| a73ab083 | 3271 | @note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 3272 | **/\r |
| 2f88bd3a | 3273 | #define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47\r |
| c67b579c MK |
3274 | \r |
| 3275 | /**\r | |
| 3276 | Package. Uncore C-box 4 perfmon counter 0.\r | |
| 3277 | \r | |
| 3278 | @param ECX MSR_HASWELL_E_C4_PMON_CTR0 (0x00000E48)\r | |
| 3279 | @param EAX Lower 32-bits of MSR value.\r | |
| 3280 | @param EDX Upper 32-bits of MSR value.\r | |
| 3281 | \r | |
| 3282 | <b>Example usage</b>\r | |
| 3283 | @code\r | |
| 3284 | UINT64 Msr;\r | |
| 3285 | \r | |
| 3286 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0);\r | |
| 3287 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr);\r | |
| 3288 | @endcode\r | |
| a73ab083 | 3289 | @note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r |
| c67b579c | 3290 | **/\r |
| 2f88bd3a | 3291 | #define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48\r |
| c67b579c MK |
3292 | \r |
| 3293 | /**\r | |
| 3294 | Package. Uncore C-box 4 perfmon counter 1.\r | |
| 3295 | \r | |
| 3296 | @param ECX MSR_HASWELL_E_C4_PMON_CTR1 (0x00000E49)\r | |
| 3297 | @param EAX Lower 32-bits of MSR value.\r | |
| 3298 | @param EDX Upper 32-bits of MSR value.\r | |
| 3299 | \r | |
| 3300 | <b>Example usage</b>\r | |
| 3301 | @code\r | |
| 3302 | UINT64 Msr;\r | |
| 3303 | \r | |
| 3304 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1);\r | |
| 3305 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr);\r | |
| 3306 | @endcode\r | |
| a73ab083 | 3307 | @note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r |
| c67b579c | 3308 | **/\r |
| 2f88bd3a | 3309 | #define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49\r |
| c67b579c MK |
3310 | \r |
| 3311 | /**\r | |
| 3312 | Package. Uncore C-box 4 perfmon counter 2.\r | |
| 3313 | \r | |
| 3314 | @param ECX MSR_HASWELL_E_C4_PMON_CTR2 (0x00000E4A)\r | |
| 3315 | @param EAX Lower 32-bits of MSR value.\r | |
| 3316 | @param EDX Upper 32-bits of MSR value.\r | |
| 3317 | \r | |
| 3318 | <b>Example usage</b>\r | |
| 3319 | @code\r | |
| 3320 | UINT64 Msr;\r | |
| 3321 | \r | |
| 3322 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2);\r | |
| 3323 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr);\r | |
| 3324 | @endcode\r | |
| a73ab083 | 3325 | @note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r |
| c67b579c | 3326 | **/\r |
| 2f88bd3a | 3327 | #define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A\r |
| c67b579c MK |
3328 | \r |
| 3329 | /**\r | |
| 3330 | Package. Uncore C-box 4 perfmon counter 3.\r | |
| 3331 | \r | |
| 3332 | @param ECX MSR_HASWELL_E_C4_PMON_CTR3 (0x00000E4B)\r | |
| 3333 | @param EAX Lower 32-bits of MSR value.\r | |
| 3334 | @param EDX Upper 32-bits of MSR value.\r | |
| 3335 | \r | |
| 3336 | <b>Example usage</b>\r | |
| 3337 | @code\r | |
| 3338 | UINT64 Msr;\r | |
| 3339 | \r | |
| 3340 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3);\r | |
| 3341 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr);\r | |
| 3342 | @endcode\r | |
| a73ab083 | 3343 | @note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r |
| c67b579c | 3344 | **/\r |
| 2f88bd3a | 3345 | #define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B\r |
| c67b579c MK |
3346 | \r |
| 3347 | /**\r | |
| 3348 | Package. Uncore C-box 5 perfmon for box-wide control.\r | |
| 3349 | \r | |
| 3350 | @param ECX MSR_HASWELL_E_C5_PMON_BOX_CTL (0x00000E50)\r | |
| 3351 | @param EAX Lower 32-bits of MSR value.\r | |
| 3352 | @param EDX Upper 32-bits of MSR value.\r | |
| 3353 | \r | |
| 3354 | <b>Example usage</b>\r | |
| 3355 | @code\r | |
| 3356 | UINT64 Msr;\r | |
| 3357 | \r | |
| 3358 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL);\r | |
| 3359 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr);\r | |
| 3360 | @endcode\r | |
| a73ab083 | 3361 | @note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.\r |
| c67b579c | 3362 | **/\r |
| 2f88bd3a | 3363 | #define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50\r |
| c67b579c MK |
3364 | \r |
| 3365 | /**\r | |
| 3366 | Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.\r | |
| 3367 | \r | |
| 3368 | @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL0 (0x00000E51)\r | |
| 3369 | @param EAX Lower 32-bits of MSR value.\r | |
| 3370 | @param EDX Upper 32-bits of MSR value.\r | |
| 3371 | \r | |
| 3372 | <b>Example usage</b>\r | |
| 3373 | @code\r | |
| 3374 | UINT64 Msr;\r | |
| 3375 | \r | |
| 3376 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0);\r | |
| 3377 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr);\r | |
| 3378 | @endcode\r | |
| a73ab083 | 3379 | @note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 3380 | **/\r |
| 2f88bd3a | 3381 | #define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51\r |
| c67b579c MK |
3382 | \r |
| 3383 | /**\r | |
| 3384 | Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.\r | |
| 3385 | \r | |
| 3386 | @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL1 (0x00000E52)\r | |
| 3387 | @param EAX Lower 32-bits of MSR value.\r | |
| 3388 | @param EDX Upper 32-bits of MSR value.\r | |
| 3389 | \r | |
| 3390 | <b>Example usage</b>\r | |
| 3391 | @code\r | |
| 3392 | UINT64 Msr;\r | |
| 3393 | \r | |
| 3394 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1);\r | |
| 3395 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr);\r | |
| 3396 | @endcode\r | |
| a73ab083 | 3397 | @note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 3398 | **/\r |
| 2f88bd3a | 3399 | #define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52\r |
| c67b579c MK |
3400 | \r |
| 3401 | /**\r | |
| 3402 | Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.\r | |
| 3403 | \r | |
| 3404 | @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL2 (0x00000E53)\r | |
| 3405 | @param EAX Lower 32-bits of MSR value.\r | |
| 3406 | @param EDX Upper 32-bits of MSR value.\r | |
| 3407 | \r | |
| 3408 | <b>Example usage</b>\r | |
| 3409 | @code\r | |
| 3410 | UINT64 Msr;\r | |
| 3411 | \r | |
| 3412 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2);\r | |
| 3413 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr);\r | |
| 3414 | @endcode\r | |
| a73ab083 | 3415 | @note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 3416 | **/\r |
| 2f88bd3a | 3417 | #define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53\r |
| c67b579c MK |
3418 | \r |
| 3419 | /**\r | |
| 3420 | Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.\r | |
| 3421 | \r | |
| 3422 | @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL3 (0x00000E54)\r | |
| 3423 | @param EAX Lower 32-bits of MSR value.\r | |
| 3424 | @param EDX Upper 32-bits of MSR value.\r | |
| 3425 | \r | |
| 3426 | <b>Example usage</b>\r | |
| 3427 | @code\r | |
| 3428 | UINT64 Msr;\r | |
| 3429 | \r | |
| 3430 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3);\r | |
| 3431 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr);\r | |
| 3432 | @endcode\r | |
| a73ab083 | 3433 | @note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 3434 | **/\r |
| 2f88bd3a | 3435 | #define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54\r |
| c67b579c MK |
3436 | \r |
| 3437 | /**\r | |
| 3438 | Package. Uncore C-box 5 perfmon box wide filter 0.\r | |
| 3439 | \r | |
| 3440 | @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER0 (0x00000E55)\r | |
| 3441 | @param EAX Lower 32-bits of MSR value.\r | |
| 3442 | @param EDX Upper 32-bits of MSR value.\r | |
| 3443 | \r | |
| 3444 | <b>Example usage</b>\r | |
| 3445 | @code\r | |
| 3446 | UINT64 Msr;\r | |
| 3447 | \r | |
| 3448 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0);\r | |
| 3449 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr);\r | |
| 3450 | @endcode\r | |
| a73ab083 | 3451 | @note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c | 3452 | **/\r |
| 2f88bd3a | 3453 | #define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55\r |
| c67b579c MK |
3454 | \r |
| 3455 | /**\r | |
| 3456 | Package. Uncore C-box 5 perfmon box wide filter1.\r | |
| 3457 | \r | |
| 3458 | @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER1 (0x00000E56)\r | |
| 3459 | @param EAX Lower 32-bits of MSR value.\r | |
| 3460 | @param EDX Upper 32-bits of MSR value.\r | |
| 3461 | \r | |
| 3462 | <b>Example usage</b>\r | |
| 3463 | @code\r | |
| 3464 | UINT64 Msr;\r | |
| 3465 | \r | |
| 3466 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1);\r | |
| 3467 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr);\r | |
| 3468 | @endcode\r | |
| a73ab083 | 3469 | @note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c | 3470 | **/\r |
| 2f88bd3a | 3471 | #define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56\r |
| c67b579c MK |
3472 | \r |
| 3473 | /**\r | |
| 3474 | Package. Uncore C-box 5 perfmon box wide status.\r | |
| 3475 | \r | |
| 3476 | @param ECX MSR_HASWELL_E_C5_PMON_BOX_STATUS (0x00000E57)\r | |
| 3477 | @param EAX Lower 32-bits of MSR value.\r | |
| 3478 | @param EDX Upper 32-bits of MSR value.\r | |
| 3479 | \r | |
| 3480 | <b>Example usage</b>\r | |
| 3481 | @code\r | |
| 3482 | UINT64 Msr;\r | |
| 3483 | \r | |
| 3484 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS);\r | |
| 3485 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr);\r | |
| 3486 | @endcode\r | |
| a73ab083 | 3487 | @note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 3488 | **/\r |
| 2f88bd3a | 3489 | #define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57\r |
| c67b579c MK |
3490 | \r |
| 3491 | /**\r | |
| 3492 | Package. Uncore C-box 5 perfmon counter 0.\r | |
| 3493 | \r | |
| 3494 | @param ECX MSR_HASWELL_E_C5_PMON_CTR0 (0x00000E58)\r | |
| 3495 | @param EAX Lower 32-bits of MSR value.\r | |
| 3496 | @param EDX Upper 32-bits of MSR value.\r | |
| 3497 | \r | |
| 3498 | <b>Example usage</b>\r | |
| 3499 | @code\r | |
| 3500 | UINT64 Msr;\r | |
| 3501 | \r | |
| 3502 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0);\r | |
| 3503 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr);\r | |
| 3504 | @endcode\r | |
| a73ab083 | 3505 | @note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r |
| c67b579c | 3506 | **/\r |
| 2f88bd3a | 3507 | #define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58\r |
| c67b579c MK |
3508 | \r |
| 3509 | /**\r | |
| 3510 | Package. Uncore C-box 5 perfmon counter 1.\r | |
| 3511 | \r | |
| 3512 | @param ECX MSR_HASWELL_E_C5_PMON_CTR1 (0x00000E59)\r | |
| 3513 | @param EAX Lower 32-bits of MSR value.\r | |
| 3514 | @param EDX Upper 32-bits of MSR value.\r | |
| 3515 | \r | |
| 3516 | <b>Example usage</b>\r | |
| 3517 | @code\r | |
| 3518 | UINT64 Msr;\r | |
| 3519 | \r | |
| 3520 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1);\r | |
| 3521 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr);\r | |
| 3522 | @endcode\r | |
| a73ab083 | 3523 | @note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r |
| c67b579c | 3524 | **/\r |
| 2f88bd3a | 3525 | #define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59\r |
| c67b579c MK |
3526 | \r |
| 3527 | /**\r | |
| 3528 | Package. Uncore C-box 5 perfmon counter 2.\r | |
| 3529 | \r | |
| 3530 | @param ECX MSR_HASWELL_E_C5_PMON_CTR2 (0x00000E5A)\r | |
| 3531 | @param EAX Lower 32-bits of MSR value.\r | |
| 3532 | @param EDX Upper 32-bits of MSR value.\r | |
| 3533 | \r | |
| 3534 | <b>Example usage</b>\r | |
| 3535 | @code\r | |
| 3536 | UINT64 Msr;\r | |
| 3537 | \r | |
| 3538 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2);\r | |
| 3539 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr);\r | |
| 3540 | @endcode\r | |
| a73ab083 | 3541 | @note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r |
| c67b579c | 3542 | **/\r |
| 2f88bd3a | 3543 | #define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A\r |
| c67b579c MK |
3544 | \r |
| 3545 | /**\r | |
| 3546 | Package. Uncore C-box 5 perfmon counter 3.\r | |
| 3547 | \r | |
| 3548 | @param ECX MSR_HASWELL_E_C5_PMON_CTR3 (0x00000E5B)\r | |
| 3549 | @param EAX Lower 32-bits of MSR value.\r | |
| 3550 | @param EDX Upper 32-bits of MSR value.\r | |
| 3551 | \r | |
| 3552 | <b>Example usage</b>\r | |
| 3553 | @code\r | |
| 3554 | UINT64 Msr;\r | |
| 3555 | \r | |
| 3556 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3);\r | |
| 3557 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr);\r | |
| 3558 | @endcode\r | |
| a73ab083 | 3559 | @note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r |
| c67b579c | 3560 | **/\r |
| 2f88bd3a | 3561 | #define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B\r |
| c67b579c MK |
3562 | \r |
| 3563 | /**\r | |
| 3564 | Package. Uncore C-box 6 perfmon for box-wide control.\r | |
| 3565 | \r | |
| 3566 | @param ECX MSR_HASWELL_E_C6_PMON_BOX_CTL (0x00000E60)\r | |
| 3567 | @param EAX Lower 32-bits of MSR value.\r | |
| 3568 | @param EDX Upper 32-bits of MSR value.\r | |
| 3569 | \r | |
| 3570 | <b>Example usage</b>\r | |
| 3571 | @code\r | |
| 3572 | UINT64 Msr;\r | |
| 3573 | \r | |
| 3574 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL);\r | |
| 3575 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr);\r | |
| 3576 | @endcode\r | |
| a73ab083 | 3577 | @note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.\r |
| c67b579c | 3578 | **/\r |
| 2f88bd3a | 3579 | #define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60\r |
| c67b579c MK |
3580 | \r |
| 3581 | /**\r | |
| 3582 | Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.\r | |
| 3583 | \r | |
| 3584 | @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL0 (0x00000E61)\r | |
| 3585 | @param EAX Lower 32-bits of MSR value.\r | |
| 3586 | @param EDX Upper 32-bits of MSR value.\r | |
| 3587 | \r | |
| 3588 | <b>Example usage</b>\r | |
| 3589 | @code\r | |
| 3590 | UINT64 Msr;\r | |
| 3591 | \r | |
| 3592 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0);\r | |
| 3593 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr);\r | |
| 3594 | @endcode\r | |
| a73ab083 | 3595 | @note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 3596 | **/\r |
| 2f88bd3a | 3597 | #define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61\r |
| c67b579c MK |
3598 | \r |
| 3599 | /**\r | |
| 3600 | Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.\r | |
| 3601 | \r | |
| 3602 | @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL1 (0x00000E62)\r | |
| 3603 | @param EAX Lower 32-bits of MSR value.\r | |
| 3604 | @param EDX Upper 32-bits of MSR value.\r | |
| 3605 | \r | |
| 3606 | <b>Example usage</b>\r | |
| 3607 | @code\r | |
| 3608 | UINT64 Msr;\r | |
| 3609 | \r | |
| 3610 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1);\r | |
| 3611 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr);\r | |
| 3612 | @endcode\r | |
| a73ab083 | 3613 | @note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 3614 | **/\r |
| 2f88bd3a | 3615 | #define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62\r |
| c67b579c MK |
3616 | \r |
| 3617 | /**\r | |
| 3618 | Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.\r | |
| 3619 | \r | |
| 3620 | @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL2 (0x00000E63)\r | |
| 3621 | @param EAX Lower 32-bits of MSR value.\r | |
| 3622 | @param EDX Upper 32-bits of MSR value.\r | |
| 3623 | \r | |
| 3624 | <b>Example usage</b>\r | |
| 3625 | @code\r | |
| 3626 | UINT64 Msr;\r | |
| 3627 | \r | |
| 3628 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2);\r | |
| 3629 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr);\r | |
| 3630 | @endcode\r | |
| a73ab083 | 3631 | @note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 3632 | **/\r |
| 2f88bd3a | 3633 | #define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63\r |
| c67b579c MK |
3634 | \r |
| 3635 | /**\r | |
| 3636 | Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.\r | |
| 3637 | \r | |
| 3638 | @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL3 (0x00000E64)\r | |
| 3639 | @param EAX Lower 32-bits of MSR value.\r | |
| 3640 | @param EDX Upper 32-bits of MSR value.\r | |
| 3641 | \r | |
| 3642 | <b>Example usage</b>\r | |
| 3643 | @code\r | |
| 3644 | UINT64 Msr;\r | |
| 3645 | \r | |
| 3646 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3);\r | |
| 3647 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr);\r | |
| 3648 | @endcode\r | |
| a73ab083 | 3649 | @note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 3650 | **/\r |
| 2f88bd3a | 3651 | #define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64\r |
| c67b579c MK |
3652 | \r |
| 3653 | /**\r | |
| 3654 | Package. Uncore C-box 6 perfmon box wide filter 0.\r | |
| 3655 | \r | |
| 3656 | @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER0 (0x00000E65)\r | |
| 3657 | @param EAX Lower 32-bits of MSR value.\r | |
| 3658 | @param EDX Upper 32-bits of MSR value.\r | |
| 3659 | \r | |
| 3660 | <b>Example usage</b>\r | |
| 3661 | @code\r | |
| 3662 | UINT64 Msr;\r | |
| 3663 | \r | |
| 3664 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0);\r | |
| 3665 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr);\r | |
| 3666 | @endcode\r | |
| a73ab083 | 3667 | @note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c | 3668 | **/\r |
| 2f88bd3a | 3669 | #define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65\r |
| c67b579c MK |
3670 | \r |
| 3671 | /**\r | |
| 3672 | Package. Uncore C-box 6 perfmon box wide filter1.\r | |
| 3673 | \r | |
| 3674 | @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER1 (0x00000E66)\r | |
| 3675 | @param EAX Lower 32-bits of MSR value.\r | |
| 3676 | @param EDX Upper 32-bits of MSR value.\r | |
| 3677 | \r | |
| 3678 | <b>Example usage</b>\r | |
| 3679 | @code\r | |
| 3680 | UINT64 Msr;\r | |
| 3681 | \r | |
| 3682 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1);\r | |
| 3683 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr);\r | |
| 3684 | @endcode\r | |
| a73ab083 | 3685 | @note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c | 3686 | **/\r |
| 2f88bd3a | 3687 | #define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66\r |
| c67b579c MK |
3688 | \r |
| 3689 | /**\r | |
| 3690 | Package. Uncore C-box 6 perfmon box wide status.\r | |
| 3691 | \r | |
| 3692 | @param ECX MSR_HASWELL_E_C6_PMON_BOX_STATUS (0x00000E67)\r | |
| 3693 | @param EAX Lower 32-bits of MSR value.\r | |
| 3694 | @param EDX Upper 32-bits of MSR value.\r | |
| 3695 | \r | |
| 3696 | <b>Example usage</b>\r | |
| 3697 | @code\r | |
| 3698 | UINT64 Msr;\r | |
| 3699 | \r | |
| 3700 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS);\r | |
| 3701 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr);\r | |
| 3702 | @endcode\r | |
| a73ab083 | 3703 | @note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 3704 | **/\r |
| 2f88bd3a | 3705 | #define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67\r |
| c67b579c MK |
3706 | \r |
| 3707 | /**\r | |
| 3708 | Package. Uncore C-box 6 perfmon counter 0.\r | |
| 3709 | \r | |
| 3710 | @param ECX MSR_HASWELL_E_C6_PMON_CTR0 (0x00000E68)\r | |
| 3711 | @param EAX Lower 32-bits of MSR value.\r | |
| 3712 | @param EDX Upper 32-bits of MSR value.\r | |
| 3713 | \r | |
| 3714 | <b>Example usage</b>\r | |
| 3715 | @code\r | |
| 3716 | UINT64 Msr;\r | |
| 3717 | \r | |
| 3718 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0);\r | |
| 3719 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr);\r | |
| 3720 | @endcode\r | |
| a73ab083 | 3721 | @note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r |
| c67b579c | 3722 | **/\r |
| 2f88bd3a | 3723 | #define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68\r |
| c67b579c MK |
3724 | \r |
| 3725 | /**\r | |
| 3726 | Package. Uncore C-box 6 perfmon counter 1.\r | |
| 3727 | \r | |
| 3728 | @param ECX MSR_HASWELL_E_C6_PMON_CTR1 (0x00000E69)\r | |
| 3729 | @param EAX Lower 32-bits of MSR value.\r | |
| 3730 | @param EDX Upper 32-bits of MSR value.\r | |
| 3731 | \r | |
| 3732 | <b>Example usage</b>\r | |
| 3733 | @code\r | |
| 3734 | UINT64 Msr;\r | |
| 3735 | \r | |
| 3736 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1);\r | |
| 3737 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr);\r | |
| 3738 | @endcode\r | |
| a73ab083 | 3739 | @note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r |
| c67b579c | 3740 | **/\r |
| 2f88bd3a | 3741 | #define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69\r |
| c67b579c MK |
3742 | \r |
| 3743 | /**\r | |
| 3744 | Package. Uncore C-box 6 perfmon counter 2.\r | |
| 3745 | \r | |
| 3746 | @param ECX MSR_HASWELL_E_C6_PMON_CTR2 (0x00000E6A)\r | |
| 3747 | @param EAX Lower 32-bits of MSR value.\r | |
| 3748 | @param EDX Upper 32-bits of MSR value.\r | |
| 3749 | \r | |
| 3750 | <b>Example usage</b>\r | |
| 3751 | @code\r | |
| 3752 | UINT64 Msr;\r | |
| 3753 | \r | |
| 3754 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2);\r | |
| 3755 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr);\r | |
| 3756 | @endcode\r | |
| a73ab083 | 3757 | @note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r |
| c67b579c | 3758 | **/\r |
| 2f88bd3a | 3759 | #define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A\r |
| c67b579c MK |
3760 | \r |
| 3761 | /**\r | |
| 3762 | Package. Uncore C-box 6 perfmon counter 3.\r | |
| 3763 | \r | |
| 3764 | @param ECX MSR_HASWELL_E_C6_PMON_CTR3 (0x00000E6B)\r | |
| 3765 | @param EAX Lower 32-bits of MSR value.\r | |
| 3766 | @param EDX Upper 32-bits of MSR value.\r | |
| 3767 | \r | |
| 3768 | <b>Example usage</b>\r | |
| 3769 | @code\r | |
| 3770 | UINT64 Msr;\r | |
| 3771 | \r | |
| 3772 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3);\r | |
| 3773 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr);\r | |
| 3774 | @endcode\r | |
| a73ab083 | 3775 | @note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r |
| c67b579c | 3776 | **/\r |
| 2f88bd3a | 3777 | #define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B\r |
| c67b579c MK |
3778 | \r |
| 3779 | /**\r | |
| 3780 | Package. Uncore C-box 7 perfmon for box-wide control.\r | |
| 3781 | \r | |
| 3782 | @param ECX MSR_HASWELL_E_C7_PMON_BOX_CTL (0x00000E70)\r | |
| 3783 | @param EAX Lower 32-bits of MSR value.\r | |
| 3784 | @param EDX Upper 32-bits of MSR value.\r | |
| 3785 | \r | |
| 3786 | <b>Example usage</b>\r | |
| 3787 | @code\r | |
| 3788 | UINT64 Msr;\r | |
| 3789 | \r | |
| 3790 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL);\r | |
| 3791 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr);\r | |
| 3792 | @endcode\r | |
| a73ab083 | 3793 | @note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.\r |
| c67b579c | 3794 | **/\r |
| 2f88bd3a | 3795 | #define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70\r |
| c67b579c MK |
3796 | \r |
| 3797 | /**\r | |
| 3798 | Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.\r | |
| 3799 | \r | |
| 3800 | @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL0 (0x00000E71)\r | |
| 3801 | @param EAX Lower 32-bits of MSR value.\r | |
| 3802 | @param EDX Upper 32-bits of MSR value.\r | |
| 3803 | \r | |
| 3804 | <b>Example usage</b>\r | |
| 3805 | @code\r | |
| 3806 | UINT64 Msr;\r | |
| 3807 | \r | |
| 3808 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0);\r | |
| 3809 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr);\r | |
| 3810 | @endcode\r | |
| a73ab083 | 3811 | @note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 3812 | **/\r |
| 2f88bd3a | 3813 | #define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71\r |
| c67b579c MK |
3814 | \r |
| 3815 | /**\r | |
| 3816 | Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.\r | |
| 3817 | \r | |
| 3818 | @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL1 (0x00000E72)\r | |
| 3819 | @param EAX Lower 32-bits of MSR value.\r | |
| 3820 | @param EDX Upper 32-bits of MSR value.\r | |
| 3821 | \r | |
| 3822 | <b>Example usage</b>\r | |
| 3823 | @code\r | |
| 3824 | UINT64 Msr;\r | |
| 3825 | \r | |
| 3826 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1);\r | |
| 3827 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr);\r | |
| 3828 | @endcode\r | |
| a73ab083 | 3829 | @note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 3830 | **/\r |
| 2f88bd3a | 3831 | #define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72\r |
| c67b579c MK |
3832 | \r |
| 3833 | /**\r | |
| 3834 | Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.\r | |
| 3835 | \r | |
| 3836 | @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL2 (0x00000E73)\r | |
| 3837 | @param EAX Lower 32-bits of MSR value.\r | |
| 3838 | @param EDX Upper 32-bits of MSR value.\r | |
| 3839 | \r | |
| 3840 | <b>Example usage</b>\r | |
| 3841 | @code\r | |
| 3842 | UINT64 Msr;\r | |
| 3843 | \r | |
| 3844 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2);\r | |
| 3845 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr);\r | |
| 3846 | @endcode\r | |
| a73ab083 | 3847 | @note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 3848 | **/\r |
| 2f88bd3a | 3849 | #define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73\r |
| c67b579c MK |
3850 | \r |
| 3851 | /**\r | |
| 3852 | Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.\r | |
| 3853 | \r | |
| 3854 | @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL3 (0x00000E74)\r | |
| 3855 | @param EAX Lower 32-bits of MSR value.\r | |
| 3856 | @param EDX Upper 32-bits of MSR value.\r | |
| 3857 | \r | |
| 3858 | <b>Example usage</b>\r | |
| 3859 | @code\r | |
| 3860 | UINT64 Msr;\r | |
| 3861 | \r | |
| 3862 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3);\r | |
| 3863 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr);\r | |
| 3864 | @endcode\r | |
| a73ab083 | 3865 | @note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 3866 | **/\r |
| 2f88bd3a | 3867 | #define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74\r |
| c67b579c MK |
3868 | \r |
| 3869 | /**\r | |
| 3870 | Package. Uncore C-box 7 perfmon box wide filter 0.\r | |
| 3871 | \r | |
| 3872 | @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER0 (0x00000E75)\r | |
| 3873 | @param EAX Lower 32-bits of MSR value.\r | |
| 3874 | @param EDX Upper 32-bits of MSR value.\r | |
| 3875 | \r | |
| 3876 | <b>Example usage</b>\r | |
| 3877 | @code\r | |
| 3878 | UINT64 Msr;\r | |
| 3879 | \r | |
| 3880 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0);\r | |
| 3881 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr);\r | |
| 3882 | @endcode\r | |
| a73ab083 | 3883 | @note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c | 3884 | **/\r |
| 2f88bd3a | 3885 | #define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75\r |
| c67b579c MK |
3886 | \r |
| 3887 | /**\r | |
| 3888 | Package. Uncore C-box 7 perfmon box wide filter1.\r | |
| 3889 | \r | |
| 3890 | @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER1 (0x00000E76)\r | |
| 3891 | @param EAX Lower 32-bits of MSR value.\r | |
| 3892 | @param EDX Upper 32-bits of MSR value.\r | |
| 3893 | \r | |
| 3894 | <b>Example usage</b>\r | |
| 3895 | @code\r | |
| 3896 | UINT64 Msr;\r | |
| 3897 | \r | |
| 3898 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1);\r | |
| 3899 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr);\r | |
| 3900 | @endcode\r | |
| a73ab083 | 3901 | @note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c | 3902 | **/\r |
| 2f88bd3a | 3903 | #define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76\r |
| c67b579c MK |
3904 | \r |
| 3905 | /**\r | |
| 3906 | Package. Uncore C-box 7 perfmon box wide status.\r | |
| 3907 | \r | |
| 3908 | @param ECX MSR_HASWELL_E_C7_PMON_BOX_STATUS (0x00000E77)\r | |
| 3909 | @param EAX Lower 32-bits of MSR value.\r | |
| 3910 | @param EDX Upper 32-bits of MSR value.\r | |
| 3911 | \r | |
| 3912 | <b>Example usage</b>\r | |
| 3913 | @code\r | |
| 3914 | UINT64 Msr;\r | |
| 3915 | \r | |
| 3916 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS);\r | |
| 3917 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr);\r | |
| 3918 | @endcode\r | |
| a73ab083 | 3919 | @note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 3920 | **/\r |
| 2f88bd3a | 3921 | #define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77\r |
| c67b579c MK |
3922 | \r |
| 3923 | /**\r | |
| 3924 | Package. Uncore C-box 7 perfmon counter 0.\r | |
| 3925 | \r | |
| 3926 | @param ECX MSR_HASWELL_E_C7_PMON_CTR0 (0x00000E78)\r | |
| 3927 | @param EAX Lower 32-bits of MSR value.\r | |
| 3928 | @param EDX Upper 32-bits of MSR value.\r | |
| 3929 | \r | |
| 3930 | <b>Example usage</b>\r | |
| 3931 | @code\r | |
| 3932 | UINT64 Msr;\r | |
| 3933 | \r | |
| 3934 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0);\r | |
| 3935 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr);\r | |
| 3936 | @endcode\r | |
| a73ab083 | 3937 | @note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r |
| c67b579c | 3938 | **/\r |
| 2f88bd3a | 3939 | #define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78\r |
| c67b579c MK |
3940 | \r |
| 3941 | /**\r | |
| 3942 | Package. Uncore C-box 7 perfmon counter 1.\r | |
| 3943 | \r | |
| 3944 | @param ECX MSR_HASWELL_E_C7_PMON_CTR1 (0x00000E79)\r | |
| 3945 | @param EAX Lower 32-bits of MSR value.\r | |
| 3946 | @param EDX Upper 32-bits of MSR value.\r | |
| 3947 | \r | |
| 3948 | <b>Example usage</b>\r | |
| 3949 | @code\r | |
| 3950 | UINT64 Msr;\r | |
| 3951 | \r | |
| 3952 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1);\r | |
| 3953 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr);\r | |
| 3954 | @endcode\r | |
| a73ab083 | 3955 | @note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r |
| c67b579c | 3956 | **/\r |
| 2f88bd3a | 3957 | #define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79\r |
| c67b579c MK |
3958 | \r |
| 3959 | /**\r | |
| 3960 | Package. Uncore C-box 7 perfmon counter 2.\r | |
| 3961 | \r | |
| 3962 | @param ECX MSR_HASWELL_E_C7_PMON_CTR2 (0x00000E7A)\r | |
| 3963 | @param EAX Lower 32-bits of MSR value.\r | |
| 3964 | @param EDX Upper 32-bits of MSR value.\r | |
| 3965 | \r | |
| 3966 | <b>Example usage</b>\r | |
| 3967 | @code\r | |
| 3968 | UINT64 Msr;\r | |
| 3969 | \r | |
| 3970 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2);\r | |
| 3971 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr);\r | |
| 3972 | @endcode\r | |
| a73ab083 | 3973 | @note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r |
| c67b579c | 3974 | **/\r |
| 2f88bd3a | 3975 | #define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A\r |
| c67b579c MK |
3976 | \r |
| 3977 | /**\r | |
| 3978 | Package. Uncore C-box 7 perfmon counter 3.\r | |
| 3979 | \r | |
| 3980 | @param ECX MSR_HASWELL_E_C7_PMON_CTR3 (0x00000E7B)\r | |
| 3981 | @param EAX Lower 32-bits of MSR value.\r | |
| 3982 | @param EDX Upper 32-bits of MSR value.\r | |
| 3983 | \r | |
| 3984 | <b>Example usage</b>\r | |
| 3985 | @code\r | |
| 3986 | UINT64 Msr;\r | |
| 3987 | \r | |
| 3988 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3);\r | |
| 3989 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr);\r | |
| 3990 | @endcode\r | |
| a73ab083 | 3991 | @note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r |
| c67b579c | 3992 | **/\r |
| 2f88bd3a | 3993 | #define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B\r |
| c67b579c MK |
3994 | \r |
| 3995 | /**\r | |
| 3996 | Package. Uncore C-box 8 perfmon local box wide control.\r | |
| 3997 | \r | |
| 3998 | @param ECX MSR_HASWELL_E_C8_PMON_BOX_CTL (0x00000E80)\r | |
| 3999 | @param EAX Lower 32-bits of MSR value.\r | |
| 4000 | @param EDX Upper 32-bits of MSR value.\r | |
| 4001 | \r | |
| 4002 | <b>Example usage</b>\r | |
| 4003 | @code\r | |
| 4004 | UINT64 Msr;\r | |
| 4005 | \r | |
| 4006 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL);\r | |
| 4007 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr);\r | |
| 4008 | @endcode\r | |
| a73ab083 | 4009 | @note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.\r |
| c67b579c | 4010 | **/\r |
| 2f88bd3a | 4011 | #define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80\r |
| c67b579c MK |
4012 | \r |
| 4013 | /**\r | |
| 4014 | Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.\r | |
| 4015 | \r | |
| 4016 | @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL0 (0x00000E81)\r | |
| 4017 | @param EAX Lower 32-bits of MSR value.\r | |
| 4018 | @param EDX Upper 32-bits of MSR value.\r | |
| 4019 | \r | |
| 4020 | <b>Example usage</b>\r | |
| 4021 | @code\r | |
| 4022 | UINT64 Msr;\r | |
| 4023 | \r | |
| 4024 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0);\r | |
| 4025 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr);\r | |
| 4026 | @endcode\r | |
| a73ab083 | 4027 | @note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 4028 | **/\r |
| 2f88bd3a | 4029 | #define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81\r |
| c67b579c MK |
4030 | \r |
| 4031 | /**\r | |
| 4032 | Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.\r | |
| 4033 | \r | |
| 4034 | @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL1 (0x00000E82)\r | |
| 4035 | @param EAX Lower 32-bits of MSR value.\r | |
| 4036 | @param EDX Upper 32-bits of MSR value.\r | |
| 4037 | \r | |
| 4038 | <b>Example usage</b>\r | |
| 4039 | @code\r | |
| 4040 | UINT64 Msr;\r | |
| 4041 | \r | |
| 4042 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1);\r | |
| 4043 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr);\r | |
| 4044 | @endcode\r | |
| a73ab083 | 4045 | @note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 4046 | **/\r |
| 2f88bd3a | 4047 | #define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82\r |
| c67b579c MK |
4048 | \r |
| 4049 | /**\r | |
| 4050 | Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.\r | |
| 4051 | \r | |
| 4052 | @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL2 (0x00000E83)\r | |
| 4053 | @param EAX Lower 32-bits of MSR value.\r | |
| 4054 | @param EDX Upper 32-bits of MSR value.\r | |
| 4055 | \r | |
| 4056 | <b>Example usage</b>\r | |
| 4057 | @code\r | |
| 4058 | UINT64 Msr;\r | |
| 4059 | \r | |
| 4060 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2);\r | |
| 4061 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr);\r | |
| 4062 | @endcode\r | |
| a73ab083 | 4063 | @note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 4064 | **/\r |
| 2f88bd3a | 4065 | #define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83\r |
| c67b579c MK |
4066 | \r |
| 4067 | /**\r | |
| 4068 | Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.\r | |
| 4069 | \r | |
| 4070 | @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL3 (0x00000E84)\r | |
| 4071 | @param EAX Lower 32-bits of MSR value.\r | |
| 4072 | @param EDX Upper 32-bits of MSR value.\r | |
| 4073 | \r | |
| 4074 | <b>Example usage</b>\r | |
| 4075 | @code\r | |
| 4076 | UINT64 Msr;\r | |
| 4077 | \r | |
| 4078 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3);\r | |
| 4079 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr);\r | |
| 4080 | @endcode\r | |
| a73ab083 | 4081 | @note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 4082 | **/\r |
| 2f88bd3a | 4083 | #define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84\r |
| c67b579c MK |
4084 | \r |
| 4085 | /**\r | |
| 4086 | Package. Uncore C-box 8 perfmon box wide filter0.\r | |
| 4087 | \r | |
| 4088 | @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER0 (0x00000E85)\r | |
| 4089 | @param EAX Lower 32-bits of MSR value.\r | |
| 4090 | @param EDX Upper 32-bits of MSR value.\r | |
| 4091 | \r | |
| 4092 | <b>Example usage</b>\r | |
| 4093 | @code\r | |
| 4094 | UINT64 Msr;\r | |
| 4095 | \r | |
| 4096 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0);\r | |
| 4097 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr);\r | |
| 4098 | @endcode\r | |
| a73ab083 | 4099 | @note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c | 4100 | **/\r |
| 2f88bd3a | 4101 | #define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85\r |
| c67b579c MK |
4102 | \r |
| 4103 | /**\r | |
| 4104 | Package. Uncore C-box 8 perfmon box wide filter1.\r | |
| 4105 | \r | |
| 4106 | @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER1 (0x00000E86)\r | |
| 4107 | @param EAX Lower 32-bits of MSR value.\r | |
| 4108 | @param EDX Upper 32-bits of MSR value.\r | |
| 4109 | \r | |
| 4110 | <b>Example usage</b>\r | |
| 4111 | @code\r | |
| 4112 | UINT64 Msr;\r | |
| 4113 | \r | |
| 4114 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1);\r | |
| 4115 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr);\r | |
| 4116 | @endcode\r | |
| a73ab083 | 4117 | @note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c | 4118 | **/\r |
| 2f88bd3a | 4119 | #define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86\r |
| c67b579c MK |
4120 | \r |
| 4121 | /**\r | |
| 4122 | Package. Uncore C-box 8 perfmon box wide status.\r | |
| 4123 | \r | |
| 4124 | @param ECX MSR_HASWELL_E_C8_PMON_BOX_STATUS (0x00000E87)\r | |
| 4125 | @param EAX Lower 32-bits of MSR value.\r | |
| 4126 | @param EDX Upper 32-bits of MSR value.\r | |
| 4127 | \r | |
| 4128 | <b>Example usage</b>\r | |
| 4129 | @code\r | |
| 4130 | UINT64 Msr;\r | |
| 4131 | \r | |
| 4132 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS);\r | |
| 4133 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr);\r | |
| 4134 | @endcode\r | |
| a73ab083 | 4135 | @note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 4136 | **/\r |
| 2f88bd3a | 4137 | #define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87\r |
| c67b579c MK |
4138 | \r |
| 4139 | /**\r | |
| 4140 | Package. Uncore C-box 8 perfmon counter 0.\r | |
| 4141 | \r | |
| 4142 | @param ECX MSR_HASWELL_E_C8_PMON_CTR0 (0x00000E88)\r | |
| 4143 | @param EAX Lower 32-bits of MSR value.\r | |
| 4144 | @param EDX Upper 32-bits of MSR value.\r | |
| 4145 | \r | |
| 4146 | <b>Example usage</b>\r | |
| 4147 | @code\r | |
| 4148 | UINT64 Msr;\r | |
| 4149 | \r | |
| 4150 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0);\r | |
| 4151 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr);\r | |
| 4152 | @endcode\r | |
| a73ab083 | 4153 | @note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r |
| c67b579c | 4154 | **/\r |
| 2f88bd3a | 4155 | #define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88\r |
| c67b579c MK |
4156 | \r |
| 4157 | /**\r | |
| 4158 | Package. Uncore C-box 8 perfmon counter 1.\r | |
| 4159 | \r | |
| 4160 | @param ECX MSR_HASWELL_E_C8_PMON_CTR1 (0x00000E89)\r | |
| 4161 | @param EAX Lower 32-bits of MSR value.\r | |
| 4162 | @param EDX Upper 32-bits of MSR value.\r | |
| 4163 | \r | |
| 4164 | <b>Example usage</b>\r | |
| 4165 | @code\r | |
| 4166 | UINT64 Msr;\r | |
| 4167 | \r | |
| 4168 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1);\r | |
| 4169 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr);\r | |
| 4170 | @endcode\r | |
| a73ab083 | 4171 | @note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r |
| c67b579c | 4172 | **/\r |
| 2f88bd3a | 4173 | #define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89\r |
| c67b579c MK |
4174 | \r |
| 4175 | /**\r | |
| 4176 | Package. Uncore C-box 8 perfmon counter 2.\r | |
| 4177 | \r | |
| 4178 | @param ECX MSR_HASWELL_E_C8_PMON_CTR2 (0x00000E8A)\r | |
| 4179 | @param EAX Lower 32-bits of MSR value.\r | |
| 4180 | @param EDX Upper 32-bits of MSR value.\r | |
| 4181 | \r | |
| 4182 | <b>Example usage</b>\r | |
| 4183 | @code\r | |
| 4184 | UINT64 Msr;\r | |
| 4185 | \r | |
| 4186 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2);\r | |
| 4187 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr);\r | |
| 4188 | @endcode\r | |
| a73ab083 | 4189 | @note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r |
| c67b579c | 4190 | **/\r |
| 2f88bd3a | 4191 | #define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A\r |
| c67b579c MK |
4192 | \r |
| 4193 | /**\r | |
| 4194 | Package. Uncore C-box 8 perfmon counter 3.\r | |
| 4195 | \r | |
| 4196 | @param ECX MSR_HASWELL_E_C8_PMON_CTR3 (0x00000E8B)\r | |
| 4197 | @param EAX Lower 32-bits of MSR value.\r | |
| 4198 | @param EDX Upper 32-bits of MSR value.\r | |
| 4199 | \r | |
| 4200 | <b>Example usage</b>\r | |
| 4201 | @code\r | |
| 4202 | UINT64 Msr;\r | |
| 4203 | \r | |
| 4204 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3);\r | |
| 4205 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr);\r | |
| 4206 | @endcode\r | |
| a73ab083 | 4207 | @note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r |
| c67b579c | 4208 | **/\r |
| 2f88bd3a | 4209 | #define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B\r |
| c67b579c MK |
4210 | \r |
| 4211 | /**\r | |
| 4212 | Package. Uncore C-box 9 perfmon local box wide control.\r | |
| 4213 | \r | |
| 4214 | @param ECX MSR_HASWELL_E_C9_PMON_BOX_CTL (0x00000E90)\r | |
| 4215 | @param EAX Lower 32-bits of MSR value.\r | |
| 4216 | @param EDX Upper 32-bits of MSR value.\r | |
| 4217 | \r | |
| 4218 | <b>Example usage</b>\r | |
| 4219 | @code\r | |
| 4220 | UINT64 Msr;\r | |
| 4221 | \r | |
| 4222 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL);\r | |
| 4223 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr);\r | |
| 4224 | @endcode\r | |
| a73ab083 | 4225 | @note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.\r |
| c67b579c | 4226 | **/\r |
| 2f88bd3a | 4227 | #define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90\r |
| c67b579c MK |
4228 | \r |
| 4229 | /**\r | |
| 4230 | Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.\r | |
| 4231 | \r | |
| 4232 | @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL0 (0x00000E91)\r | |
| 4233 | @param EAX Lower 32-bits of MSR value.\r | |
| 4234 | @param EDX Upper 32-bits of MSR value.\r | |
| 4235 | \r | |
| 4236 | <b>Example usage</b>\r | |
| 4237 | @code\r | |
| 4238 | UINT64 Msr;\r | |
| 4239 | \r | |
| 4240 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0);\r | |
| 4241 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr);\r | |
| 4242 | @endcode\r | |
| a73ab083 | 4243 | @note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 4244 | **/\r |
| 2f88bd3a | 4245 | #define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91\r |
| c67b579c MK |
4246 | \r |
| 4247 | /**\r | |
| 4248 | Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.\r | |
| 4249 | \r | |
| 4250 | @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL1 (0x00000E92)\r | |
| 4251 | @param EAX Lower 32-bits of MSR value.\r | |
| 4252 | @param EDX Upper 32-bits of MSR value.\r | |
| 4253 | \r | |
| 4254 | <b>Example usage</b>\r | |
| 4255 | @code\r | |
| 4256 | UINT64 Msr;\r | |
| 4257 | \r | |
| 4258 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1);\r | |
| 4259 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr);\r | |
| 4260 | @endcode\r | |
| a73ab083 | 4261 | @note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 4262 | **/\r |
| 2f88bd3a | 4263 | #define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92\r |
| c67b579c MK |
4264 | \r |
| 4265 | /**\r | |
| 4266 | Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.\r | |
| 4267 | \r | |
| 4268 | @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL2 (0x00000E93)\r | |
| 4269 | @param EAX Lower 32-bits of MSR value.\r | |
| 4270 | @param EDX Upper 32-bits of MSR value.\r | |
| 4271 | \r | |
| 4272 | <b>Example usage</b>\r | |
| 4273 | @code\r | |
| 4274 | UINT64 Msr;\r | |
| 4275 | \r | |
| 4276 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2);\r | |
| 4277 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr);\r | |
| 4278 | @endcode\r | |
| a73ab083 | 4279 | @note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 4280 | **/\r |
| 2f88bd3a | 4281 | #define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93\r |
| c67b579c MK |
4282 | \r |
| 4283 | /**\r | |
| 4284 | Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.\r | |
| 4285 | \r | |
| 4286 | @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL3 (0x00000E94)\r | |
| 4287 | @param EAX Lower 32-bits of MSR value.\r | |
| 4288 | @param EDX Upper 32-bits of MSR value.\r | |
| 4289 | \r | |
| 4290 | <b>Example usage</b>\r | |
| 4291 | @code\r | |
| 4292 | UINT64 Msr;\r | |
| 4293 | \r | |
| 4294 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3);\r | |
| 4295 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr);\r | |
| 4296 | @endcode\r | |
| a73ab083 | 4297 | @note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 4298 | **/\r |
| 2f88bd3a | 4299 | #define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94\r |
| c67b579c MK |
4300 | \r |
| 4301 | /**\r | |
| 4302 | Package. Uncore C-box 9 perfmon box wide filter0.\r | |
| 4303 | \r | |
| 4304 | @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER0 (0x00000E95)\r | |
| 4305 | @param EAX Lower 32-bits of MSR value.\r | |
| 4306 | @param EDX Upper 32-bits of MSR value.\r | |
| 4307 | \r | |
| 4308 | <b>Example usage</b>\r | |
| 4309 | @code\r | |
| 4310 | UINT64 Msr;\r | |
| 4311 | \r | |
| 4312 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0);\r | |
| 4313 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr);\r | |
| 4314 | @endcode\r | |
| a73ab083 | 4315 | @note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c | 4316 | **/\r |
| 2f88bd3a | 4317 | #define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95\r |
| c67b579c MK |
4318 | \r |
| 4319 | /**\r | |
| 4320 | Package. Uncore C-box 9 perfmon box wide filter1.\r | |
| 4321 | \r | |
| 4322 | @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER1 (0x00000E96)\r | |
| 4323 | @param EAX Lower 32-bits of MSR value.\r | |
| 4324 | @param EDX Upper 32-bits of MSR value.\r | |
| 4325 | \r | |
| 4326 | <b>Example usage</b>\r | |
| 4327 | @code\r | |
| 4328 | UINT64 Msr;\r | |
| 4329 | \r | |
| 4330 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1);\r | |
| 4331 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr);\r | |
| 4332 | @endcode\r | |
| a73ab083 | 4333 | @note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c | 4334 | **/\r |
| 2f88bd3a | 4335 | #define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96\r |
| c67b579c MK |
4336 | \r |
| 4337 | /**\r | |
| 4338 | Package. Uncore C-box 9 perfmon box wide status.\r | |
| 4339 | \r | |
| 4340 | @param ECX MSR_HASWELL_E_C9_PMON_BOX_STATUS (0x00000E97)\r | |
| 4341 | @param EAX Lower 32-bits of MSR value.\r | |
| 4342 | @param EDX Upper 32-bits of MSR value.\r | |
| 4343 | \r | |
| 4344 | <b>Example usage</b>\r | |
| 4345 | @code\r | |
| 4346 | UINT64 Msr;\r | |
| 4347 | \r | |
| 4348 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS);\r | |
| 4349 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr);\r | |
| 4350 | @endcode\r | |
| a73ab083 | 4351 | @note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 4352 | **/\r |
| 2f88bd3a | 4353 | #define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97\r |
| c67b579c MK |
4354 | \r |
| 4355 | /**\r | |
| 4356 | Package. Uncore C-box 9 perfmon counter 0.\r | |
| 4357 | \r | |
| 4358 | @param ECX MSR_HASWELL_E_C9_PMON_CTR0 (0x00000E98)\r | |
| 4359 | @param EAX Lower 32-bits of MSR value.\r | |
| 4360 | @param EDX Upper 32-bits of MSR value.\r | |
| 4361 | \r | |
| 4362 | <b>Example usage</b>\r | |
| 4363 | @code\r | |
| 4364 | UINT64 Msr;\r | |
| 4365 | \r | |
| 4366 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0);\r | |
| 4367 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr);\r | |
| 4368 | @endcode\r | |
| a73ab083 | 4369 | @note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r |
| c67b579c | 4370 | **/\r |
| 2f88bd3a | 4371 | #define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98\r |
| c67b579c MK |
4372 | \r |
| 4373 | /**\r | |
| 4374 | Package. Uncore C-box 9 perfmon counter 1.\r | |
| 4375 | \r | |
| 4376 | @param ECX MSR_HASWELL_E_C9_PMON_CTR1 (0x00000E99)\r | |
| 4377 | @param EAX Lower 32-bits of MSR value.\r | |
| 4378 | @param EDX Upper 32-bits of MSR value.\r | |
| 4379 | \r | |
| 4380 | <b>Example usage</b>\r | |
| 4381 | @code\r | |
| 4382 | UINT64 Msr;\r | |
| 4383 | \r | |
| 4384 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1);\r | |
| 4385 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr);\r | |
| 4386 | @endcode\r | |
| a73ab083 | 4387 | @note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r |
| c67b579c | 4388 | **/\r |
| 2f88bd3a | 4389 | #define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99\r |
| c67b579c MK |
4390 | \r |
| 4391 | /**\r | |
| 4392 | Package. Uncore C-box 9 perfmon counter 2.\r | |
| 4393 | \r | |
| 4394 | @param ECX MSR_HASWELL_E_C9_PMON_CTR2 (0x00000E9A)\r | |
| 4395 | @param EAX Lower 32-bits of MSR value.\r | |
| 4396 | @param EDX Upper 32-bits of MSR value.\r | |
| 4397 | \r | |
| 4398 | <b>Example usage</b>\r | |
| 4399 | @code\r | |
| 4400 | UINT64 Msr;\r | |
| 4401 | \r | |
| 4402 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2);\r | |
| 4403 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr);\r | |
| 4404 | @endcode\r | |
| a73ab083 | 4405 | @note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r |
| c67b579c | 4406 | **/\r |
| 2f88bd3a | 4407 | #define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A\r |
| c67b579c MK |
4408 | \r |
| 4409 | /**\r | |
| 4410 | Package. Uncore C-box 9 perfmon counter 3.\r | |
| 4411 | \r | |
| 4412 | @param ECX MSR_HASWELL_E_C9_PMON_CTR3 (0x00000E9B)\r | |
| 4413 | @param EAX Lower 32-bits of MSR value.\r | |
| 4414 | @param EDX Upper 32-bits of MSR value.\r | |
| 4415 | \r | |
| 4416 | <b>Example usage</b>\r | |
| 4417 | @code\r | |
| 4418 | UINT64 Msr;\r | |
| 4419 | \r | |
| 4420 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3);\r | |
| 4421 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr);\r | |
| 4422 | @endcode\r | |
| a73ab083 | 4423 | @note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r |
| c67b579c | 4424 | **/\r |
| 2f88bd3a | 4425 | #define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B\r |
| c67b579c MK |
4426 | \r |
| 4427 | /**\r | |
| 4428 | Package. Uncore C-box 10 perfmon local box wide control.\r | |
| 4429 | \r | |
| 4430 | @param ECX MSR_HASWELL_E_C10_PMON_BOX_CTL (0x00000EA0)\r | |
| 4431 | @param EAX Lower 32-bits of MSR value.\r | |
| 4432 | @param EDX Upper 32-bits of MSR value.\r | |
| 4433 | \r | |
| 4434 | <b>Example usage</b>\r | |
| 4435 | @code\r | |
| 4436 | UINT64 Msr;\r | |
| 4437 | \r | |
| 4438 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL);\r | |
| 4439 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr);\r | |
| 4440 | @endcode\r | |
| a73ab083 | 4441 | @note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.\r |
| c67b579c | 4442 | **/\r |
| 2f88bd3a | 4443 | #define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0\r |
| c67b579c MK |
4444 | \r |
| 4445 | /**\r | |
| 4446 | Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.\r | |
| 4447 | \r | |
| 4448 | @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL0 (0x00000EA1)\r | |
| 4449 | @param EAX Lower 32-bits of MSR value.\r | |
| 4450 | @param EDX Upper 32-bits of MSR value.\r | |
| 4451 | \r | |
| 4452 | <b>Example usage</b>\r | |
| 4453 | @code\r | |
| 4454 | UINT64 Msr;\r | |
| 4455 | \r | |
| 4456 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0);\r | |
| 4457 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr);\r | |
| 4458 | @endcode\r | |
| a73ab083 | 4459 | @note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 4460 | **/\r |
| 2f88bd3a | 4461 | #define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1\r |
| c67b579c MK |
4462 | \r |
| 4463 | /**\r | |
| 4464 | Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.\r | |
| 4465 | \r | |
| 4466 | @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL1 (0x00000EA2)\r | |
| 4467 | @param EAX Lower 32-bits of MSR value.\r | |
| 4468 | @param EDX Upper 32-bits of MSR value.\r | |
| 4469 | \r | |
| 4470 | <b>Example usage</b>\r | |
| 4471 | @code\r | |
| 4472 | UINT64 Msr;\r | |
| 4473 | \r | |
| 4474 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1);\r | |
| 4475 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr);\r | |
| 4476 | @endcode\r | |
| a73ab083 | 4477 | @note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 4478 | **/\r |
| 2f88bd3a | 4479 | #define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2\r |
| c67b579c MK |
4480 | \r |
| 4481 | /**\r | |
| 4482 | Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.\r | |
| 4483 | \r | |
| 4484 | @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL2 (0x00000EA3)\r | |
| 4485 | @param EAX Lower 32-bits of MSR value.\r | |
| 4486 | @param EDX Upper 32-bits of MSR value.\r | |
| 4487 | \r | |
| 4488 | <b>Example usage</b>\r | |
| 4489 | @code\r | |
| 4490 | UINT64 Msr;\r | |
| 4491 | \r | |
| 4492 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2);\r | |
| 4493 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr);\r | |
| 4494 | @endcode\r | |
| a73ab083 | 4495 | @note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 4496 | **/\r |
| 2f88bd3a | 4497 | #define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3\r |
| c67b579c MK |
4498 | \r |
| 4499 | /**\r | |
| 4500 | Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.\r | |
| 4501 | \r | |
| 4502 | @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL3 (0x00000EA4)\r | |
| 4503 | @param EAX Lower 32-bits of MSR value.\r | |
| 4504 | @param EDX Upper 32-bits of MSR value.\r | |
| 4505 | \r | |
| 4506 | <b>Example usage</b>\r | |
| 4507 | @code\r | |
| 4508 | UINT64 Msr;\r | |
| 4509 | \r | |
| 4510 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3);\r | |
| 4511 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr);\r | |
| 4512 | @endcode\r | |
| a73ab083 | 4513 | @note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 4514 | **/\r |
| 2f88bd3a | 4515 | #define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4\r |
| c67b579c MK |
4516 | \r |
| 4517 | /**\r | |
| 4518 | Package. Uncore C-box 10 perfmon box wide filter0.\r | |
| 4519 | \r | |
| 4520 | @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER0 (0x00000EA5)\r | |
| 4521 | @param EAX Lower 32-bits of MSR value.\r | |
| 4522 | @param EDX Upper 32-bits of MSR value.\r | |
| 4523 | \r | |
| 4524 | <b>Example usage</b>\r | |
| 4525 | @code\r | |
| 4526 | UINT64 Msr;\r | |
| 4527 | \r | |
| 4528 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0);\r | |
| 4529 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr);\r | |
| 4530 | @endcode\r | |
| a73ab083 | 4531 | @note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c | 4532 | **/\r |
| 2f88bd3a | 4533 | #define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5\r |
| c67b579c MK |
4534 | \r |
| 4535 | /**\r | |
| 4536 | Package. Uncore C-box 10 perfmon box wide filter1.\r | |
| 4537 | \r | |
| 4538 | @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER1 (0x00000EA6)\r | |
| 4539 | @param EAX Lower 32-bits of MSR value.\r | |
| 4540 | @param EDX Upper 32-bits of MSR value.\r | |
| 4541 | \r | |
| 4542 | <b>Example usage</b>\r | |
| 4543 | @code\r | |
| 4544 | UINT64 Msr;\r | |
| 4545 | \r | |
| 4546 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1);\r | |
| 4547 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr);\r | |
| 4548 | @endcode\r | |
| a73ab083 | 4549 | @note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c | 4550 | **/\r |
| 2f88bd3a | 4551 | #define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6\r |
| c67b579c MK |
4552 | \r |
| 4553 | /**\r | |
| 4554 | Package. Uncore C-box 10 perfmon box wide status.\r | |
| 4555 | \r | |
| 4556 | @param ECX MSR_HASWELL_E_C10_PMON_BOX_STATUS (0x00000EA7)\r | |
| 4557 | @param EAX Lower 32-bits of MSR value.\r | |
| 4558 | @param EDX Upper 32-bits of MSR value.\r | |
| 4559 | \r | |
| 4560 | <b>Example usage</b>\r | |
| 4561 | @code\r | |
| 4562 | UINT64 Msr;\r | |
| 4563 | \r | |
| 4564 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS);\r | |
| 4565 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr);\r | |
| 4566 | @endcode\r | |
| a73ab083 | 4567 | @note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 4568 | **/\r |
| 2f88bd3a | 4569 | #define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7\r |
| c67b579c MK |
4570 | \r |
| 4571 | /**\r | |
| 4572 | Package. Uncore C-box 10 perfmon counter 0.\r | |
| 4573 | \r | |
| 4574 | @param ECX MSR_HASWELL_E_C10_PMON_CTR0 (0x00000EA8)\r | |
| 4575 | @param EAX Lower 32-bits of MSR value.\r | |
| 4576 | @param EDX Upper 32-bits of MSR value.\r | |
| 4577 | \r | |
| 4578 | <b>Example usage</b>\r | |
| 4579 | @code\r | |
| 4580 | UINT64 Msr;\r | |
| 4581 | \r | |
| 4582 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0);\r | |
| 4583 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr);\r | |
| 4584 | @endcode\r | |
| a73ab083 | 4585 | @note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.\r |
| c67b579c | 4586 | **/\r |
| 2f88bd3a | 4587 | #define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8\r |
| c67b579c MK |
4588 | \r |
| 4589 | /**\r | |
| 4590 | Package. Uncore C-box 10 perfmon counter 1.\r | |
| 4591 | \r | |
| 4592 | @param ECX MSR_HASWELL_E_C10_PMON_CTR1 (0x00000EA9)\r | |
| 4593 | @param EAX Lower 32-bits of MSR value.\r | |
| 4594 | @param EDX Upper 32-bits of MSR value.\r | |
| 4595 | \r | |
| 4596 | <b>Example usage</b>\r | |
| 4597 | @code\r | |
| 4598 | UINT64 Msr;\r | |
| 4599 | \r | |
| 4600 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1);\r | |
| 4601 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr);\r | |
| 4602 | @endcode\r | |
| a73ab083 | 4603 | @note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.\r |
| c67b579c | 4604 | **/\r |
| 2f88bd3a | 4605 | #define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9\r |
| c67b579c MK |
4606 | \r |
| 4607 | /**\r | |
| 4608 | Package. Uncore C-box 10 perfmon counter 2.\r | |
| 4609 | \r | |
| 4610 | @param ECX MSR_HASWELL_E_C10_PMON_CTR2 (0x00000EAA)\r | |
| 4611 | @param EAX Lower 32-bits of MSR value.\r | |
| 4612 | @param EDX Upper 32-bits of MSR value.\r | |
| 4613 | \r | |
| 4614 | <b>Example usage</b>\r | |
| 4615 | @code\r | |
| 4616 | UINT64 Msr;\r | |
| 4617 | \r | |
| 4618 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2);\r | |
| 4619 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr);\r | |
| 4620 | @endcode\r | |
| a73ab083 | 4621 | @note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.\r |
| c67b579c | 4622 | **/\r |
| 2f88bd3a | 4623 | #define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA\r |
| c67b579c MK |
4624 | \r |
| 4625 | /**\r | |
| 4626 | Package. Uncore C-box 10 perfmon counter 3.\r | |
| 4627 | \r | |
| 4628 | @param ECX MSR_HASWELL_E_C10_PMON_CTR3 (0x00000EAB)\r | |
| 4629 | @param EAX Lower 32-bits of MSR value.\r | |
| 4630 | @param EDX Upper 32-bits of MSR value.\r | |
| 4631 | \r | |
| 4632 | <b>Example usage</b>\r | |
| 4633 | @code\r | |
| 4634 | UINT64 Msr;\r | |
| 4635 | \r | |
| 4636 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3);\r | |
| 4637 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr);\r | |
| 4638 | @endcode\r | |
| a73ab083 | 4639 | @note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.\r |
| c67b579c | 4640 | **/\r |
| 2f88bd3a | 4641 | #define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB\r |
| c67b579c MK |
4642 | \r |
| 4643 | /**\r | |
| 4644 | Package. Uncore C-box 11 perfmon local box wide control.\r | |
| 4645 | \r | |
| 4646 | @param ECX MSR_HASWELL_E_C11_PMON_BOX_CTL (0x00000EB0)\r | |
| 4647 | @param EAX Lower 32-bits of MSR value.\r | |
| 4648 | @param EDX Upper 32-bits of MSR value.\r | |
| 4649 | \r | |
| 4650 | <b>Example usage</b>\r | |
| 4651 | @code\r | |
| 4652 | UINT64 Msr;\r | |
| 4653 | \r | |
| 4654 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL);\r | |
| 4655 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr);\r | |
| 4656 | @endcode\r | |
| a73ab083 | 4657 | @note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.\r |
| c67b579c | 4658 | **/\r |
| 2f88bd3a | 4659 | #define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0\r |
| c67b579c MK |
4660 | \r |
| 4661 | /**\r | |
| 4662 | Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.\r | |
| 4663 | \r | |
| 4664 | @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL0 (0x00000EB1)\r | |
| 4665 | @param EAX Lower 32-bits of MSR value.\r | |
| 4666 | @param EDX Upper 32-bits of MSR value.\r | |
| 4667 | \r | |
| 4668 | <b>Example usage</b>\r | |
| 4669 | @code\r | |
| 4670 | UINT64 Msr;\r | |
| 4671 | \r | |
| 4672 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0);\r | |
| 4673 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr);\r | |
| 4674 | @endcode\r | |
| a73ab083 | 4675 | @note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 4676 | **/\r |
| 2f88bd3a | 4677 | #define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1\r |
| c67b579c MK |
4678 | \r |
| 4679 | /**\r | |
| 4680 | Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.\r | |
| 4681 | \r | |
| 4682 | @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL1 (0x00000EB2)\r | |
| 4683 | @param EAX Lower 32-bits of MSR value.\r | |
| 4684 | @param EDX Upper 32-bits of MSR value.\r | |
| 4685 | \r | |
| 4686 | <b>Example usage</b>\r | |
| 4687 | @code\r | |
| 4688 | UINT64 Msr;\r | |
| 4689 | \r | |
| 4690 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1);\r | |
| 4691 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr);\r | |
| 4692 | @endcode\r | |
| a73ab083 | 4693 | @note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 4694 | **/\r |
| 2f88bd3a | 4695 | #define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2\r |
| c67b579c MK |
4696 | \r |
| 4697 | /**\r | |
| 4698 | Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.\r | |
| 4699 | \r | |
| 4700 | @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL2 (0x00000EB3)\r | |
| 4701 | @param EAX Lower 32-bits of MSR value.\r | |
| 4702 | @param EDX Upper 32-bits of MSR value.\r | |
| 4703 | \r | |
| 4704 | <b>Example usage</b>\r | |
| 4705 | @code\r | |
| 4706 | UINT64 Msr;\r | |
| 4707 | \r | |
| 4708 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2);\r | |
| 4709 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr);\r | |
| 4710 | @endcode\r | |
| a73ab083 | 4711 | @note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 4712 | **/\r |
| 2f88bd3a | 4713 | #define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3\r |
| c67b579c MK |
4714 | \r |
| 4715 | /**\r | |
| 4716 | Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.\r | |
| 4717 | \r | |
| 4718 | @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL3 (0x00000EB4)\r | |
| 4719 | @param EAX Lower 32-bits of MSR value.\r | |
| 4720 | @param EDX Upper 32-bits of MSR value.\r | |
| 4721 | \r | |
| 4722 | <b>Example usage</b>\r | |
| 4723 | @code\r | |
| 4724 | UINT64 Msr;\r | |
| 4725 | \r | |
| 4726 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3);\r | |
| 4727 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr);\r | |
| 4728 | @endcode\r | |
| a73ab083 | 4729 | @note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 4730 | **/\r |
| 2f88bd3a | 4731 | #define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4\r |
| c67b579c MK |
4732 | \r |
| 4733 | /**\r | |
| 4734 | Package. Uncore C-box 11 perfmon box wide filter0.\r | |
| 4735 | \r | |
| 4736 | @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER0 (0x00000EB5)\r | |
| 4737 | @param EAX Lower 32-bits of MSR value.\r | |
| 4738 | @param EDX Upper 32-bits of MSR value.\r | |
| 4739 | \r | |
| 4740 | <b>Example usage</b>\r | |
| 4741 | @code\r | |
| 4742 | UINT64 Msr;\r | |
| 4743 | \r | |
| 4744 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0);\r | |
| 4745 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr);\r | |
| 4746 | @endcode\r | |
| a73ab083 | 4747 | @note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c | 4748 | **/\r |
| 2f88bd3a | 4749 | #define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5\r |
| c67b579c MK |
4750 | \r |
| 4751 | /**\r | |
| 4752 | Package. Uncore C-box 11 perfmon box wide filter1.\r | |
| 4753 | \r | |
| 4754 | @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER1 (0x00000EB6)\r | |
| 4755 | @param EAX Lower 32-bits of MSR value.\r | |
| 4756 | @param EDX Upper 32-bits of MSR value.\r | |
| 4757 | \r | |
| 4758 | <b>Example usage</b>\r | |
| 4759 | @code\r | |
| 4760 | UINT64 Msr;\r | |
| 4761 | \r | |
| 4762 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1);\r | |
| 4763 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr);\r | |
| 4764 | @endcode\r | |
| a73ab083 | 4765 | @note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c | 4766 | **/\r |
| 2f88bd3a | 4767 | #define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6\r |
| c67b579c MK |
4768 | \r |
| 4769 | /**\r | |
| 4770 | Package. Uncore C-box 11 perfmon box wide status.\r | |
| 4771 | \r | |
| 4772 | @param ECX MSR_HASWELL_E_C11_PMON_BOX_STATUS (0x00000EB7)\r | |
| 4773 | @param EAX Lower 32-bits of MSR value.\r | |
| 4774 | @param EDX Upper 32-bits of MSR value.\r | |
| 4775 | \r | |
| 4776 | <b>Example usage</b>\r | |
| 4777 | @code\r | |
| 4778 | UINT64 Msr;\r | |
| 4779 | \r | |
| 4780 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS);\r | |
| 4781 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr);\r | |
| 4782 | @endcode\r | |
| a73ab083 | 4783 | @note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 4784 | **/\r |
| 2f88bd3a | 4785 | #define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7\r |
| c67b579c MK |
4786 | \r |
| 4787 | /**\r | |
| 4788 | Package. Uncore C-box 11 perfmon counter 0.\r | |
| 4789 | \r | |
| 4790 | @param ECX MSR_HASWELL_E_C11_PMON_CTR0 (0x00000EB8)\r | |
| 4791 | @param EAX Lower 32-bits of MSR value.\r | |
| 4792 | @param EDX Upper 32-bits of MSR value.\r | |
| 4793 | \r | |
| 4794 | <b>Example usage</b>\r | |
| 4795 | @code\r | |
| 4796 | UINT64 Msr;\r | |
| 4797 | \r | |
| 4798 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0);\r | |
| 4799 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr);\r | |
| 4800 | @endcode\r | |
| a73ab083 | 4801 | @note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.\r |
| c67b579c | 4802 | **/\r |
| 2f88bd3a | 4803 | #define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8\r |
| c67b579c MK |
4804 | \r |
| 4805 | /**\r | |
| 4806 | Package. Uncore C-box 11 perfmon counter 1.\r | |
| 4807 | \r | |
| 4808 | @param ECX MSR_HASWELL_E_C11_PMON_CTR1 (0x00000EB9)\r | |
| 4809 | @param EAX Lower 32-bits of MSR value.\r | |
| 4810 | @param EDX Upper 32-bits of MSR value.\r | |
| 4811 | \r | |
| 4812 | <b>Example usage</b>\r | |
| 4813 | @code\r | |
| 4814 | UINT64 Msr;\r | |
| 4815 | \r | |
| 4816 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1);\r | |
| 4817 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr);\r | |
| 4818 | @endcode\r | |
| a73ab083 | 4819 | @note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.\r |
| c67b579c | 4820 | **/\r |
| 2f88bd3a | 4821 | #define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9\r |
| c67b579c MK |
4822 | \r |
| 4823 | /**\r | |
| 4824 | Package. Uncore C-box 11 perfmon counter 2.\r | |
| 4825 | \r | |
| 4826 | @param ECX MSR_HASWELL_E_C11_PMON_CTR2 (0x00000EBA)\r | |
| 4827 | @param EAX Lower 32-bits of MSR value.\r | |
| 4828 | @param EDX Upper 32-bits of MSR value.\r | |
| 4829 | \r | |
| 4830 | <b>Example usage</b>\r | |
| 4831 | @code\r | |
| 4832 | UINT64 Msr;\r | |
| 4833 | \r | |
| 4834 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2);\r | |
| 4835 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr);\r | |
| 4836 | @endcode\r | |
| a73ab083 | 4837 | @note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.\r |
| c67b579c | 4838 | **/\r |
| 2f88bd3a | 4839 | #define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA\r |
| c67b579c MK |
4840 | \r |
| 4841 | /**\r | |
| 4842 | Package. Uncore C-box 11 perfmon counter 3.\r | |
| 4843 | \r | |
| 4844 | @param ECX MSR_HASWELL_E_C11_PMON_CTR3 (0x00000EBB)\r | |
| 4845 | @param EAX Lower 32-bits of MSR value.\r | |
| 4846 | @param EDX Upper 32-bits of MSR value.\r | |
| 4847 | \r | |
| 4848 | <b>Example usage</b>\r | |
| 4849 | @code\r | |
| 4850 | UINT64 Msr;\r | |
| 4851 | \r | |
| 4852 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3);\r | |
| 4853 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr);\r | |
| 4854 | @endcode\r | |
| a73ab083 | 4855 | @note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.\r |
| c67b579c | 4856 | **/\r |
| 2f88bd3a | 4857 | #define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB\r |
| c67b579c MK |
4858 | \r |
| 4859 | /**\r | |
| 4860 | Package. Uncore C-box 12 perfmon local box wide control.\r | |
| 4861 | \r | |
| 4862 | @param ECX MSR_HASWELL_E_C12_PMON_BOX_CTL (0x00000EC0)\r | |
| 4863 | @param EAX Lower 32-bits of MSR value.\r | |
| 4864 | @param EDX Upper 32-bits of MSR value.\r | |
| 4865 | \r | |
| 4866 | <b>Example usage</b>\r | |
| 4867 | @code\r | |
| 4868 | UINT64 Msr;\r | |
| 4869 | \r | |
| 4870 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL);\r | |
| 4871 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr);\r | |
| 4872 | @endcode\r | |
| a73ab083 | 4873 | @note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.\r |
| c67b579c | 4874 | **/\r |
| 2f88bd3a | 4875 | #define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0\r |
| c67b579c MK |
4876 | \r |
| 4877 | /**\r | |
| 4878 | Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.\r | |
| 4879 | \r | |
| 4880 | @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL0 (0x00000EC1)\r | |
| 4881 | @param EAX Lower 32-bits of MSR value.\r | |
| 4882 | @param EDX Upper 32-bits of MSR value.\r | |
| 4883 | \r | |
| 4884 | <b>Example usage</b>\r | |
| 4885 | @code\r | |
| 4886 | UINT64 Msr;\r | |
| 4887 | \r | |
| 4888 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0);\r | |
| 4889 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr);\r | |
| 4890 | @endcode\r | |
| a73ab083 | 4891 | @note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 4892 | **/\r |
| 2f88bd3a | 4893 | #define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1\r |
| c67b579c MK |
4894 | \r |
| 4895 | /**\r | |
| 4896 | Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.\r | |
| 4897 | \r | |
| 4898 | @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL1 (0x00000EC2)\r | |
| 4899 | @param EAX Lower 32-bits of MSR value.\r | |
| 4900 | @param EDX Upper 32-bits of MSR value.\r | |
| 4901 | \r | |
| 4902 | <b>Example usage</b>\r | |
| 4903 | @code\r | |
| 4904 | UINT64 Msr;\r | |
| 4905 | \r | |
| 4906 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1);\r | |
| 4907 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr);\r | |
| 4908 | @endcode\r | |
| a73ab083 | 4909 | @note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 4910 | **/\r |
| 2f88bd3a | 4911 | #define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2\r |
| c67b579c MK |
4912 | \r |
| 4913 | /**\r | |
| 4914 | Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.\r | |
| 4915 | \r | |
| 4916 | @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL2 (0x00000EC3)\r | |
| 4917 | @param EAX Lower 32-bits of MSR value.\r | |
| 4918 | @param EDX Upper 32-bits of MSR value.\r | |
| 4919 | \r | |
| 4920 | <b>Example usage</b>\r | |
| 4921 | @code\r | |
| 4922 | UINT64 Msr;\r | |
| 4923 | \r | |
| 4924 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2);\r | |
| 4925 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr);\r | |
| 4926 | @endcode\r | |
| a73ab083 | 4927 | @note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 4928 | **/\r |
| 2f88bd3a | 4929 | #define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3\r |
| c67b579c MK |
4930 | \r |
| 4931 | /**\r | |
| 4932 | Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.\r | |
| 4933 | \r | |
| 4934 | @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL3 (0x00000EC4)\r | |
| 4935 | @param EAX Lower 32-bits of MSR value.\r | |
| 4936 | @param EDX Upper 32-bits of MSR value.\r | |
| 4937 | \r | |
| 4938 | <b>Example usage</b>\r | |
| 4939 | @code\r | |
| 4940 | UINT64 Msr;\r | |
| 4941 | \r | |
| 4942 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3);\r | |
| 4943 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr);\r | |
| 4944 | @endcode\r | |
| a73ab083 | 4945 | @note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 4946 | **/\r |
| 2f88bd3a | 4947 | #define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4\r |
| c67b579c MK |
4948 | \r |
| 4949 | /**\r | |
| 4950 | Package. Uncore C-box 12 perfmon box wide filter0.\r | |
| 4951 | \r | |
| 4952 | @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER0 (0x00000EC5)\r | |
| 4953 | @param EAX Lower 32-bits of MSR value.\r | |
| 4954 | @param EDX Upper 32-bits of MSR value.\r | |
| 4955 | \r | |
| 4956 | <b>Example usage</b>\r | |
| 4957 | @code\r | |
| 4958 | UINT64 Msr;\r | |
| 4959 | \r | |
| 4960 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0);\r | |
| 4961 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr);\r | |
| 4962 | @endcode\r | |
| a73ab083 | 4963 | @note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c | 4964 | **/\r |
| 2f88bd3a | 4965 | #define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5\r |
| c67b579c MK |
4966 | \r |
| 4967 | /**\r | |
| 4968 | Package. Uncore C-box 12 perfmon box wide filter1.\r | |
| 4969 | \r | |
| 4970 | @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER1 (0x00000EC6)\r | |
| 4971 | @param EAX Lower 32-bits of MSR value.\r | |
| 4972 | @param EDX Upper 32-bits of MSR value.\r | |
| 4973 | \r | |
| 4974 | <b>Example usage</b>\r | |
| 4975 | @code\r | |
| 4976 | UINT64 Msr;\r | |
| 4977 | \r | |
| 4978 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1);\r | |
| 4979 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr);\r | |
| 4980 | @endcode\r | |
| a73ab083 | 4981 | @note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c | 4982 | **/\r |
| 2f88bd3a | 4983 | #define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6\r |
| c67b579c MK |
4984 | \r |
| 4985 | /**\r | |
| 4986 | Package. Uncore C-box 12 perfmon box wide status.\r | |
| 4987 | \r | |
| 4988 | @param ECX MSR_HASWELL_E_C12_PMON_BOX_STATUS (0x00000EC7)\r | |
| 4989 | @param EAX Lower 32-bits of MSR value.\r | |
| 4990 | @param EDX Upper 32-bits of MSR value.\r | |
| 4991 | \r | |
| 4992 | <b>Example usage</b>\r | |
| 4993 | @code\r | |
| 4994 | UINT64 Msr;\r | |
| 4995 | \r | |
| 4996 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS);\r | |
| 4997 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr);\r | |
| 4998 | @endcode\r | |
| a73ab083 | 4999 | @note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 5000 | **/\r |
| 2f88bd3a | 5001 | #define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7\r |
| c67b579c MK |
5002 | \r |
| 5003 | /**\r | |
| 5004 | Package. Uncore C-box 12 perfmon counter 0.\r | |
| 5005 | \r | |
| 5006 | @param ECX MSR_HASWELL_E_C12_PMON_CTR0 (0x00000EC8)\r | |
| 5007 | @param EAX Lower 32-bits of MSR value.\r | |
| 5008 | @param EDX Upper 32-bits of MSR value.\r | |
| 5009 | \r | |
| 5010 | <b>Example usage</b>\r | |
| 5011 | @code\r | |
| 5012 | UINT64 Msr;\r | |
| 5013 | \r | |
| 5014 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0);\r | |
| 5015 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr);\r | |
| 5016 | @endcode\r | |
| a73ab083 | 5017 | @note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.\r |
| c67b579c | 5018 | **/\r |
| 2f88bd3a | 5019 | #define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8\r |
| c67b579c MK |
5020 | \r |
| 5021 | /**\r | |
| 5022 | Package. Uncore C-box 12 perfmon counter 1.\r | |
| 5023 | \r | |
| 5024 | @param ECX MSR_HASWELL_E_C12_PMON_CTR1 (0x00000EC9)\r | |
| 5025 | @param EAX Lower 32-bits of MSR value.\r | |
| 5026 | @param EDX Upper 32-bits of MSR value.\r | |
| 5027 | \r | |
| 5028 | <b>Example usage</b>\r | |
| 5029 | @code\r | |
| 5030 | UINT64 Msr;\r | |
| 5031 | \r | |
| 5032 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1);\r | |
| 5033 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr);\r | |
| 5034 | @endcode\r | |
| a73ab083 | 5035 | @note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.\r |
| c67b579c | 5036 | **/\r |
| 2f88bd3a | 5037 | #define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9\r |
| c67b579c MK |
5038 | \r |
| 5039 | /**\r | |
| 5040 | Package. Uncore C-box 12 perfmon counter 2.\r | |
| 5041 | \r | |
| 5042 | @param ECX MSR_HASWELL_E_C12_PMON_CTR2 (0x00000ECA)\r | |
| 5043 | @param EAX Lower 32-bits of MSR value.\r | |
| 5044 | @param EDX Upper 32-bits of MSR value.\r | |
| 5045 | \r | |
| 5046 | <b>Example usage</b>\r | |
| 5047 | @code\r | |
| 5048 | UINT64 Msr;\r | |
| 5049 | \r | |
| 5050 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2);\r | |
| 5051 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr);\r | |
| 5052 | @endcode\r | |
| a73ab083 | 5053 | @note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.\r |
| c67b579c | 5054 | **/\r |
| 2f88bd3a | 5055 | #define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA\r |
| c67b579c MK |
5056 | \r |
| 5057 | /**\r | |
| 5058 | Package. Uncore C-box 12 perfmon counter 3.\r | |
| 5059 | \r | |
| 5060 | @param ECX MSR_HASWELL_E_C12_PMON_CTR3 (0x00000ECB)\r | |
| 5061 | @param EAX Lower 32-bits of MSR value.\r | |
| 5062 | @param EDX Upper 32-bits of MSR value.\r | |
| 5063 | \r | |
| 5064 | <b>Example usage</b>\r | |
| 5065 | @code\r | |
| 5066 | UINT64 Msr;\r | |
| 5067 | \r | |
| 5068 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3);\r | |
| 5069 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr);\r | |
| 5070 | @endcode\r | |
| a73ab083 | 5071 | @note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.\r |
| c67b579c | 5072 | **/\r |
| 2f88bd3a | 5073 | #define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB\r |
| c67b579c MK |
5074 | \r |
| 5075 | /**\r | |
| 5076 | Package. Uncore C-box 13 perfmon local box wide control.\r | |
| 5077 | \r | |
| 5078 | @param ECX MSR_HASWELL_E_C13_PMON_BOX_CTL (0x00000ED0)\r | |
| 5079 | @param EAX Lower 32-bits of MSR value.\r | |
| 5080 | @param EDX Upper 32-bits of MSR value.\r | |
| 5081 | \r | |
| 5082 | <b>Example usage</b>\r | |
| 5083 | @code\r | |
| 5084 | UINT64 Msr;\r | |
| 5085 | \r | |
| 5086 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL);\r | |
| 5087 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr);\r | |
| 5088 | @endcode\r | |
| a73ab083 | 5089 | @note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.\r |
| c67b579c | 5090 | **/\r |
| 2f88bd3a | 5091 | #define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0\r |
| c67b579c MK |
5092 | \r |
| 5093 | /**\r | |
| 5094 | Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.\r | |
| 5095 | \r | |
| 5096 | @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL0 (0x00000ED1)\r | |
| 5097 | @param EAX Lower 32-bits of MSR value.\r | |
| 5098 | @param EDX Upper 32-bits of MSR value.\r | |
| 5099 | \r | |
| 5100 | <b>Example usage</b>\r | |
| 5101 | @code\r | |
| 5102 | UINT64 Msr;\r | |
| 5103 | \r | |
| 5104 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0);\r | |
| 5105 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr);\r | |
| 5106 | @endcode\r | |
| a73ab083 | 5107 | @note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 5108 | **/\r |
| 2f88bd3a | 5109 | #define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1\r |
| c67b579c MK |
5110 | \r |
| 5111 | /**\r | |
| 5112 | Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.\r | |
| 5113 | \r | |
| 5114 | @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL1 (0x00000ED2)\r | |
| 5115 | @param EAX Lower 32-bits of MSR value.\r | |
| 5116 | @param EDX Upper 32-bits of MSR value.\r | |
| 5117 | \r | |
| 5118 | <b>Example usage</b>\r | |
| 5119 | @code\r | |
| 5120 | UINT64 Msr;\r | |
| 5121 | \r | |
| 5122 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1);\r | |
| 5123 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr);\r | |
| 5124 | @endcode\r | |
| a73ab083 | 5125 | @note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 5126 | **/\r |
| 2f88bd3a | 5127 | #define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2\r |
| c67b579c MK |
5128 | \r |
| 5129 | /**\r | |
| 5130 | Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.\r | |
| 5131 | \r | |
| 5132 | @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL2 (0x00000ED3)\r | |
| 5133 | @param EAX Lower 32-bits of MSR value.\r | |
| 5134 | @param EDX Upper 32-bits of MSR value.\r | |
| 5135 | \r | |
| 5136 | <b>Example usage</b>\r | |
| 5137 | @code\r | |
| 5138 | UINT64 Msr;\r | |
| 5139 | \r | |
| 5140 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2);\r | |
| 5141 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr);\r | |
| 5142 | @endcode\r | |
| a73ab083 | 5143 | @note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 5144 | **/\r |
| 2f88bd3a | 5145 | #define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3\r |
| c67b579c MK |
5146 | \r |
| 5147 | /**\r | |
| 5148 | Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.\r | |
| 5149 | \r | |
| 5150 | @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL3 (0x00000ED4)\r | |
| 5151 | @param EAX Lower 32-bits of MSR value.\r | |
| 5152 | @param EDX Upper 32-bits of MSR value.\r | |
| 5153 | \r | |
| 5154 | <b>Example usage</b>\r | |
| 5155 | @code\r | |
| 5156 | UINT64 Msr;\r | |
| 5157 | \r | |
| 5158 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3);\r | |
| 5159 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr);\r | |
| 5160 | @endcode\r | |
| a73ab083 | 5161 | @note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 5162 | **/\r |
| 2f88bd3a | 5163 | #define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4\r |
| c67b579c MK |
5164 | \r |
| 5165 | /**\r | |
| 5166 | Package. Uncore C-box 13 perfmon box wide filter0.\r | |
| 5167 | \r | |
| 5168 | @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER0 (0x00000ED5)\r | |
| 5169 | @param EAX Lower 32-bits of MSR value.\r | |
| 5170 | @param EDX Upper 32-bits of MSR value.\r | |
| 5171 | \r | |
| 5172 | <b>Example usage</b>\r | |
| 5173 | @code\r | |
| 5174 | UINT64 Msr;\r | |
| 5175 | \r | |
| 5176 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0);\r | |
| 5177 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr);\r | |
| 5178 | @endcode\r | |
| a73ab083 | 5179 | @note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c | 5180 | **/\r |
| 2f88bd3a | 5181 | #define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5\r |
| c67b579c MK |
5182 | \r |
| 5183 | /**\r | |
| 5184 | Package. Uncore C-box 13 perfmon box wide filter1.\r | |
| 5185 | \r | |
| 5186 | @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER1 (0x00000ED6)\r | |
| 5187 | @param EAX Lower 32-bits of MSR value.\r | |
| 5188 | @param EDX Upper 32-bits of MSR value.\r | |
| 5189 | \r | |
| 5190 | <b>Example usage</b>\r | |
| 5191 | @code\r | |
| 5192 | UINT64 Msr;\r | |
| 5193 | \r | |
| 5194 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1);\r | |
| 5195 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr);\r | |
| 5196 | @endcode\r | |
| a73ab083 | 5197 | @note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c | 5198 | **/\r |
| 2f88bd3a | 5199 | #define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6\r |
| c67b579c MK |
5200 | \r |
| 5201 | /**\r | |
| 5202 | Package. Uncore C-box 13 perfmon box wide status.\r | |
| 5203 | \r | |
| 5204 | @param ECX MSR_HASWELL_E_C13_PMON_BOX_STATUS (0x00000ED7)\r | |
| 5205 | @param EAX Lower 32-bits of MSR value.\r | |
| 5206 | @param EDX Upper 32-bits of MSR value.\r | |
| 5207 | \r | |
| 5208 | <b>Example usage</b>\r | |
| 5209 | @code\r | |
| 5210 | UINT64 Msr;\r | |
| 5211 | \r | |
| 5212 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS);\r | |
| 5213 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr);\r | |
| 5214 | @endcode\r | |
| a73ab083 | 5215 | @note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 5216 | **/\r |
| 2f88bd3a | 5217 | #define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7\r |
| c67b579c MK |
5218 | \r |
| 5219 | /**\r | |
| 5220 | Package. Uncore C-box 13 perfmon counter 0.\r | |
| 5221 | \r | |
| 5222 | @param ECX MSR_HASWELL_E_C13_PMON_CTR0 (0x00000ED8)\r | |
| 5223 | @param EAX Lower 32-bits of MSR value.\r | |
| 5224 | @param EDX Upper 32-bits of MSR value.\r | |
| 5225 | \r | |
| 5226 | <b>Example usage</b>\r | |
| 5227 | @code\r | |
| 5228 | UINT64 Msr;\r | |
| 5229 | \r | |
| 5230 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0);\r | |
| 5231 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr);\r | |
| 5232 | @endcode\r | |
| a73ab083 | 5233 | @note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.\r |
| c67b579c | 5234 | **/\r |
| 2f88bd3a | 5235 | #define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8\r |
| c67b579c MK |
5236 | \r |
| 5237 | /**\r | |
| 5238 | Package. Uncore C-box 13 perfmon counter 1.\r | |
| 5239 | \r | |
| 5240 | @param ECX MSR_HASWELL_E_C13_PMON_CTR1 (0x00000ED9)\r | |
| 5241 | @param EAX Lower 32-bits of MSR value.\r | |
| 5242 | @param EDX Upper 32-bits of MSR value.\r | |
| 5243 | \r | |
| 5244 | <b>Example usage</b>\r | |
| 5245 | @code\r | |
| 5246 | UINT64 Msr;\r | |
| 5247 | \r | |
| 5248 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1);\r | |
| 5249 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr);\r | |
| 5250 | @endcode\r | |
| a73ab083 | 5251 | @note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.\r |
| c67b579c | 5252 | **/\r |
| 2f88bd3a | 5253 | #define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9\r |
| c67b579c MK |
5254 | \r |
| 5255 | /**\r | |
| 5256 | Package. Uncore C-box 13 perfmon counter 2.\r | |
| 5257 | \r | |
| 5258 | @param ECX MSR_HASWELL_E_C13_PMON_CTR2 (0x00000EDA)\r | |
| 5259 | @param EAX Lower 32-bits of MSR value.\r | |
| 5260 | @param EDX Upper 32-bits of MSR value.\r | |
| 5261 | \r | |
| 5262 | <b>Example usage</b>\r | |
| 5263 | @code\r | |
| 5264 | UINT64 Msr;\r | |
| 5265 | \r | |
| 5266 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2);\r | |
| 5267 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr);\r | |
| 5268 | @endcode\r | |
| a73ab083 | 5269 | @note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.\r |
| c67b579c | 5270 | **/\r |
| 2f88bd3a | 5271 | #define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA\r |
| c67b579c MK |
5272 | \r |
| 5273 | /**\r | |
| 5274 | Package. Uncore C-box 13 perfmon counter 3.\r | |
| 5275 | \r | |
| 5276 | @param ECX MSR_HASWELL_E_C13_PMON_CTR3 (0x00000EDB)\r | |
| 5277 | @param EAX Lower 32-bits of MSR value.\r | |
| 5278 | @param EDX Upper 32-bits of MSR value.\r | |
| 5279 | \r | |
| 5280 | <b>Example usage</b>\r | |
| 5281 | @code\r | |
| 5282 | UINT64 Msr;\r | |
| 5283 | \r | |
| 5284 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3);\r | |
| 5285 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr);\r | |
| 5286 | @endcode\r | |
| a73ab083 | 5287 | @note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.\r |
| c67b579c | 5288 | **/\r |
| 2f88bd3a | 5289 | #define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB\r |
| c67b579c MK |
5290 | \r |
| 5291 | /**\r | |
| 5292 | Package. Uncore C-box 14 perfmon local box wide control.\r | |
| 5293 | \r | |
| 5294 | @param ECX MSR_HASWELL_E_C14_PMON_BOX_CTL (0x00000EE0)\r | |
| 5295 | @param EAX Lower 32-bits of MSR value.\r | |
| 5296 | @param EDX Upper 32-bits of MSR value.\r | |
| 5297 | \r | |
| 5298 | <b>Example usage</b>\r | |
| 5299 | @code\r | |
| 5300 | UINT64 Msr;\r | |
| 5301 | \r | |
| 5302 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL);\r | |
| 5303 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr);\r | |
| 5304 | @endcode\r | |
| a73ab083 | 5305 | @note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.\r |
| c67b579c | 5306 | **/\r |
| 2f88bd3a | 5307 | #define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0\r |
| c67b579c MK |
5308 | \r |
| 5309 | /**\r | |
| 5310 | Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.\r | |
| 5311 | \r | |
| 5312 | @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL0 (0x00000EE1)\r | |
| 5313 | @param EAX Lower 32-bits of MSR value.\r | |
| 5314 | @param EDX Upper 32-bits of MSR value.\r | |
| 5315 | \r | |
| 5316 | <b>Example usage</b>\r | |
| 5317 | @code\r | |
| 5318 | UINT64 Msr;\r | |
| 5319 | \r | |
| 5320 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0);\r | |
| 5321 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr);\r | |
| 5322 | @endcode\r | |
| a73ab083 | 5323 | @note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 5324 | **/\r |
| 2f88bd3a | 5325 | #define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1\r |
| c67b579c MK |
5326 | \r |
| 5327 | /**\r | |
| 5328 | Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.\r | |
| 5329 | \r | |
| 5330 | @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL1 (0x00000EE2)\r | |
| 5331 | @param EAX Lower 32-bits of MSR value.\r | |
| 5332 | @param EDX Upper 32-bits of MSR value.\r | |
| 5333 | \r | |
| 5334 | <b>Example usage</b>\r | |
| 5335 | @code\r | |
| 5336 | UINT64 Msr;\r | |
| 5337 | \r | |
| 5338 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1);\r | |
| 5339 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr);\r | |
| 5340 | @endcode\r | |
| a73ab083 | 5341 | @note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 5342 | **/\r |
| 2f88bd3a | 5343 | #define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2\r |
| c67b579c MK |
5344 | \r |
| 5345 | /**\r | |
| 5346 | Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.\r | |
| 5347 | \r | |
| 5348 | @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL2 (0x00000EE3)\r | |
| 5349 | @param EAX Lower 32-bits of MSR value.\r | |
| 5350 | @param EDX Upper 32-bits of MSR value.\r | |
| 5351 | \r | |
| 5352 | <b>Example usage</b>\r | |
| 5353 | @code\r | |
| 5354 | UINT64 Msr;\r | |
| 5355 | \r | |
| 5356 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2);\r | |
| 5357 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr);\r | |
| 5358 | @endcode\r | |
| a73ab083 | 5359 | @note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 5360 | **/\r |
| 2f88bd3a | 5361 | #define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3\r |
| c67b579c MK |
5362 | \r |
| 5363 | /**\r | |
| 5364 | Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.\r | |
| 5365 | \r | |
| 5366 | @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL3 (0x00000EE4)\r | |
| 5367 | @param EAX Lower 32-bits of MSR value.\r | |
| 5368 | @param EDX Upper 32-bits of MSR value.\r | |
| 5369 | \r | |
| 5370 | <b>Example usage</b>\r | |
| 5371 | @code\r | |
| 5372 | UINT64 Msr;\r | |
| 5373 | \r | |
| 5374 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3);\r | |
| 5375 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr);\r | |
| 5376 | @endcode\r | |
| a73ab083 | 5377 | @note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 5378 | **/\r |
| 2f88bd3a | 5379 | #define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4\r |
| c67b579c MK |
5380 | \r |
| 5381 | /**\r | |
| 5382 | Package. Uncore C-box 14 perfmon box wide filter0.\r | |
| 5383 | \r | |
| 5384 | @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER (0x00000EE5)\r | |
| 5385 | @param EAX Lower 32-bits of MSR value.\r | |
| 5386 | @param EDX Upper 32-bits of MSR value.\r | |
| 5387 | \r | |
| 5388 | <b>Example usage</b>\r | |
| 5389 | @code\r | |
| 5390 | UINT64 Msr;\r | |
| 5391 | \r | |
| 5392 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER);\r | |
| 5393 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr);\r | |
| 5394 | @endcode\r | |
| a73ab083 | 5395 | @note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.\r |
| c67b579c | 5396 | **/\r |
| 2f88bd3a | 5397 | #define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5\r |
| c67b579c MK |
5398 | \r |
| 5399 | /**\r | |
| 5400 | Package. Uncore C-box 14 perfmon box wide filter1.\r | |
| 5401 | \r | |
| 5402 | @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER1 (0x00000EE6)\r | |
| 5403 | @param EAX Lower 32-bits of MSR value.\r | |
| 5404 | @param EDX Upper 32-bits of MSR value.\r | |
| 5405 | \r | |
| 5406 | <b>Example usage</b>\r | |
| 5407 | @code\r | |
| 5408 | UINT64 Msr;\r | |
| 5409 | \r | |
| 5410 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1);\r | |
| 5411 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr);\r | |
| 5412 | @endcode\r | |
| a73ab083 | 5413 | @note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c | 5414 | **/\r |
| 2f88bd3a | 5415 | #define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6\r |
| c67b579c MK |
5416 | \r |
| 5417 | /**\r | |
| 5418 | Package. Uncore C-box 14 perfmon box wide status.\r | |
| 5419 | \r | |
| 5420 | @param ECX MSR_HASWELL_E_C14_PMON_BOX_STATUS (0x00000EE7)\r | |
| 5421 | @param EAX Lower 32-bits of MSR value.\r | |
| 5422 | @param EDX Upper 32-bits of MSR value.\r | |
| 5423 | \r | |
| 5424 | <b>Example usage</b>\r | |
| 5425 | @code\r | |
| 5426 | UINT64 Msr;\r | |
| 5427 | \r | |
| 5428 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS);\r | |
| 5429 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr);\r | |
| 5430 | @endcode\r | |
| a73ab083 | 5431 | @note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 5432 | **/\r |
| 2f88bd3a | 5433 | #define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7\r |
| c67b579c MK |
5434 | \r |
| 5435 | /**\r | |
| 5436 | Package. Uncore C-box 14 perfmon counter 0.\r | |
| 5437 | \r | |
| 5438 | @param ECX MSR_HASWELL_E_C14_PMON_CTR0 (0x00000EE8)\r | |
| 5439 | @param EAX Lower 32-bits of MSR value.\r | |
| 5440 | @param EDX Upper 32-bits of MSR value.\r | |
| 5441 | \r | |
| 5442 | <b>Example usage</b>\r | |
| 5443 | @code\r | |
| 5444 | UINT64 Msr;\r | |
| 5445 | \r | |
| 5446 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0);\r | |
| 5447 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr);\r | |
| 5448 | @endcode\r | |
| a73ab083 | 5449 | @note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.\r |
| c67b579c | 5450 | **/\r |
| 2f88bd3a | 5451 | #define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8\r |
| c67b579c MK |
5452 | \r |
| 5453 | /**\r | |
| 5454 | Package. Uncore C-box 14 perfmon counter 1.\r | |
| 5455 | \r | |
| 5456 | @param ECX MSR_HASWELL_E_C14_PMON_CTR1 (0x00000EE9)\r | |
| 5457 | @param EAX Lower 32-bits of MSR value.\r | |
| 5458 | @param EDX Upper 32-bits of MSR value.\r | |
| 5459 | \r | |
| 5460 | <b>Example usage</b>\r | |
| 5461 | @code\r | |
| 5462 | UINT64 Msr;\r | |
| 5463 | \r | |
| 5464 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1);\r | |
| 5465 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr);\r | |
| 5466 | @endcode\r | |
| a73ab083 | 5467 | @note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.\r |
| c67b579c | 5468 | **/\r |
| 2f88bd3a | 5469 | #define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9\r |
| c67b579c MK |
5470 | \r |
| 5471 | /**\r | |
| 5472 | Package. Uncore C-box 14 perfmon counter 2.\r | |
| 5473 | \r | |
| 5474 | @param ECX MSR_HASWELL_E_C14_PMON_CTR2 (0x00000EEA)\r | |
| 5475 | @param EAX Lower 32-bits of MSR value.\r | |
| 5476 | @param EDX Upper 32-bits of MSR value.\r | |
| 5477 | \r | |
| 5478 | <b>Example usage</b>\r | |
| 5479 | @code\r | |
| 5480 | UINT64 Msr;\r | |
| 5481 | \r | |
| 5482 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2);\r | |
| 5483 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr);\r | |
| 5484 | @endcode\r | |
| a73ab083 | 5485 | @note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.\r |
| c67b579c | 5486 | **/\r |
| 2f88bd3a | 5487 | #define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA\r |
| c67b579c MK |
5488 | \r |
| 5489 | /**\r | |
| 5490 | Package. Uncore C-box 14 perfmon counter 3.\r | |
| 5491 | \r | |
| 5492 | @param ECX MSR_HASWELL_E_C14_PMON_CTR3 (0x00000EEB)\r | |
| 5493 | @param EAX Lower 32-bits of MSR value.\r | |
| 5494 | @param EDX Upper 32-bits of MSR value.\r | |
| 5495 | \r | |
| 5496 | <b>Example usage</b>\r | |
| 5497 | @code\r | |
| 5498 | UINT64 Msr;\r | |
| 5499 | \r | |
| 5500 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3);\r | |
| 5501 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr);\r | |
| 5502 | @endcode\r | |
| a73ab083 | 5503 | @note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.\r |
| c67b579c | 5504 | **/\r |
| 2f88bd3a | 5505 | #define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB\r |
| c67b579c MK |
5506 | \r |
| 5507 | /**\r | |
| 5508 | Package. Uncore C-box 15 perfmon local box wide control.\r | |
| 5509 | \r | |
| 5510 | @param ECX MSR_HASWELL_E_C15_PMON_BOX_CTL (0x00000EF0)\r | |
| 5511 | @param EAX Lower 32-bits of MSR value.\r | |
| 5512 | @param EDX Upper 32-bits of MSR value.\r | |
| 5513 | \r | |
| 5514 | <b>Example usage</b>\r | |
| 5515 | @code\r | |
| 5516 | UINT64 Msr;\r | |
| 5517 | \r | |
| 5518 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL);\r | |
| 5519 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr);\r | |
| 5520 | @endcode\r | |
| a73ab083 | 5521 | @note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.\r |
| c67b579c | 5522 | **/\r |
| 2f88bd3a | 5523 | #define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0\r |
| c67b579c MK |
5524 | \r |
| 5525 | /**\r | |
| 5526 | Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.\r | |
| 5527 | \r | |
| 5528 | @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL0 (0x00000EF1)\r | |
| 5529 | @param EAX Lower 32-bits of MSR value.\r | |
| 5530 | @param EDX Upper 32-bits of MSR value.\r | |
| 5531 | \r | |
| 5532 | <b>Example usage</b>\r | |
| 5533 | @code\r | |
| 5534 | UINT64 Msr;\r | |
| 5535 | \r | |
| 5536 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0);\r | |
| 5537 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr);\r | |
| 5538 | @endcode\r | |
| a73ab083 | 5539 | @note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 5540 | **/\r |
| 2f88bd3a | 5541 | #define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1\r |
| c67b579c MK |
5542 | \r |
| 5543 | /**\r | |
| 5544 | Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.\r | |
| 5545 | \r | |
| 5546 | @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL1 (0x00000EF2)\r | |
| 5547 | @param EAX Lower 32-bits of MSR value.\r | |
| 5548 | @param EDX Upper 32-bits of MSR value.\r | |
| 5549 | \r | |
| 5550 | <b>Example usage</b>\r | |
| 5551 | @code\r | |
| 5552 | UINT64 Msr;\r | |
| 5553 | \r | |
| 5554 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1);\r | |
| 5555 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr);\r | |
| 5556 | @endcode\r | |
| a73ab083 | 5557 | @note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 5558 | **/\r |
| 2f88bd3a | 5559 | #define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2\r |
| c67b579c MK |
5560 | \r |
| 5561 | /**\r | |
| 5562 | Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.\r | |
| 5563 | \r | |
| 5564 | @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL2 (0x00000EF3)\r | |
| 5565 | @param EAX Lower 32-bits of MSR value.\r | |
| 5566 | @param EDX Upper 32-bits of MSR value.\r | |
| 5567 | \r | |
| 5568 | <b>Example usage</b>\r | |
| 5569 | @code\r | |
| 5570 | UINT64 Msr;\r | |
| 5571 | \r | |
| 5572 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2);\r | |
| 5573 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr);\r | |
| 5574 | @endcode\r | |
| a73ab083 | 5575 | @note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 5576 | **/\r |
| 2f88bd3a | 5577 | #define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3\r |
| c67b579c MK |
5578 | \r |
| 5579 | /**\r | |
| 5580 | Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.\r | |
| 5581 | \r | |
| 5582 | @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL3 (0x00000EF4)\r | |
| 5583 | @param EAX Lower 32-bits of MSR value.\r | |
| 5584 | @param EDX Upper 32-bits of MSR value.\r | |
| 5585 | \r | |
| 5586 | <b>Example usage</b>\r | |
| 5587 | @code\r | |
| 5588 | UINT64 Msr;\r | |
| 5589 | \r | |
| 5590 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3);\r | |
| 5591 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr);\r | |
| 5592 | @endcode\r | |
| a73ab083 | 5593 | @note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 5594 | **/\r |
| 2f88bd3a | 5595 | #define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4\r |
| c67b579c MK |
5596 | \r |
| 5597 | /**\r | |
| 5598 | Package. Uncore C-box 15 perfmon box wide filter0.\r | |
| 5599 | \r | |
| 5600 | @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER0 (0x00000EF5)\r | |
| 5601 | @param EAX Lower 32-bits of MSR value.\r | |
| 5602 | @param EDX Upper 32-bits of MSR value.\r | |
| 5603 | \r | |
| 5604 | <b>Example usage</b>\r | |
| 5605 | @code\r | |
| 5606 | UINT64 Msr;\r | |
| 5607 | \r | |
| 5608 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0);\r | |
| 5609 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr);\r | |
| 5610 | @endcode\r | |
| a73ab083 | 5611 | @note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c | 5612 | **/\r |
| 2f88bd3a | 5613 | #define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5\r |
| c67b579c MK |
5614 | \r |
| 5615 | /**\r | |
| 5616 | Package. Uncore C-box 15 perfmon box wide filter1.\r | |
| 5617 | \r | |
| 5618 | @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER1 (0x00000EF6)\r | |
| 5619 | @param EAX Lower 32-bits of MSR value.\r | |
| 5620 | @param EDX Upper 32-bits of MSR value.\r | |
| 5621 | \r | |
| 5622 | <b>Example usage</b>\r | |
| 5623 | @code\r | |
| 5624 | UINT64 Msr;\r | |
| 5625 | \r | |
| 5626 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1);\r | |
| 5627 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr);\r | |
| 5628 | @endcode\r | |
| a73ab083 | 5629 | @note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c | 5630 | **/\r |
| 2f88bd3a | 5631 | #define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6\r |
| c67b579c MK |
5632 | \r |
| 5633 | /**\r | |
| 5634 | Package. Uncore C-box 15 perfmon box wide status.\r | |
| 5635 | \r | |
| 5636 | @param ECX MSR_HASWELL_E_C15_PMON_BOX_STATUS (0x00000EF7)\r | |
| 5637 | @param EAX Lower 32-bits of MSR value.\r | |
| 5638 | @param EDX Upper 32-bits of MSR value.\r | |
| 5639 | \r | |
| 5640 | <b>Example usage</b>\r | |
| 5641 | @code\r | |
| 5642 | UINT64 Msr;\r | |
| 5643 | \r | |
| 5644 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS);\r | |
| 5645 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr);\r | |
| 5646 | @endcode\r | |
| a73ab083 | 5647 | @note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 5648 | **/\r |
| 2f88bd3a | 5649 | #define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7\r |
| c67b579c MK |
5650 | \r |
| 5651 | /**\r | |
| 5652 | Package. Uncore C-box 15 perfmon counter 0.\r | |
| 5653 | \r | |
| 5654 | @param ECX MSR_HASWELL_E_C15_PMON_CTR0 (0x00000EF8)\r | |
| 5655 | @param EAX Lower 32-bits of MSR value.\r | |
| 5656 | @param EDX Upper 32-bits of MSR value.\r | |
| 5657 | \r | |
| 5658 | <b>Example usage</b>\r | |
| 5659 | @code\r | |
| 5660 | UINT64 Msr;\r | |
| 5661 | \r | |
| 5662 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0);\r | |
| 5663 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr);\r | |
| 5664 | @endcode\r | |
| a73ab083 | 5665 | @note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.\r |
| c67b579c | 5666 | **/\r |
| 2f88bd3a | 5667 | #define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8\r |
| c67b579c MK |
5668 | \r |
| 5669 | /**\r | |
| 5670 | Package. Uncore C-box 15 perfmon counter 1.\r | |
| 5671 | \r | |
| 5672 | @param ECX MSR_HASWELL_E_C15_PMON_CTR1 (0x00000EF9)\r | |
| 5673 | @param EAX Lower 32-bits of MSR value.\r | |
| 5674 | @param EDX Upper 32-bits of MSR value.\r | |
| 5675 | \r | |
| 5676 | <b>Example usage</b>\r | |
| 5677 | @code\r | |
| 5678 | UINT64 Msr;\r | |
| 5679 | \r | |
| 5680 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1);\r | |
| 5681 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr);\r | |
| 5682 | @endcode\r | |
| a73ab083 | 5683 | @note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.\r |
| c67b579c | 5684 | **/\r |
| 2f88bd3a | 5685 | #define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9\r |
| c67b579c MK |
5686 | \r |
| 5687 | /**\r | |
| 5688 | Package. Uncore C-box 15 perfmon counter 2.\r | |
| 5689 | \r | |
| 5690 | @param ECX MSR_HASWELL_E_C15_PMON_CTR2 (0x00000EFA)\r | |
| 5691 | @param EAX Lower 32-bits of MSR value.\r | |
| 5692 | @param EDX Upper 32-bits of MSR value.\r | |
| 5693 | \r | |
| 5694 | <b>Example usage</b>\r | |
| 5695 | @code\r | |
| 5696 | UINT64 Msr;\r | |
| 5697 | \r | |
| 5698 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2);\r | |
| 5699 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr);\r | |
| 5700 | @endcode\r | |
| a73ab083 | 5701 | @note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.\r |
| c67b579c | 5702 | **/\r |
| 2f88bd3a | 5703 | #define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA\r |
| c67b579c MK |
5704 | \r |
| 5705 | /**\r | |
| 5706 | Package. Uncore C-box 15 perfmon counter 3.\r | |
| 5707 | \r | |
| 5708 | @param ECX MSR_HASWELL_E_C15_PMON_CTR3 (0x00000EFB)\r | |
| 5709 | @param EAX Lower 32-bits of MSR value.\r | |
| 5710 | @param EDX Upper 32-bits of MSR value.\r | |
| 5711 | \r | |
| 5712 | <b>Example usage</b>\r | |
| 5713 | @code\r | |
| 5714 | UINT64 Msr;\r | |
| 5715 | \r | |
| 5716 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3);\r | |
| 5717 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr);\r | |
| 5718 | @endcode\r | |
| a73ab083 | 5719 | @note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.\r |
| c67b579c | 5720 | **/\r |
| 2f88bd3a | 5721 | #define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB\r |
| c67b579c MK |
5722 | \r |
| 5723 | /**\r | |
| 5724 | Package. Uncore C-box 16 perfmon for box-wide control.\r | |
| 5725 | \r | |
| 5726 | @param ECX MSR_HASWELL_E_C16_PMON_BOX_CTL (0x00000F00)\r | |
| 5727 | @param EAX Lower 32-bits of MSR value.\r | |
| 5728 | @param EDX Upper 32-bits of MSR value.\r | |
| 5729 | \r | |
| 5730 | <b>Example usage</b>\r | |
| 5731 | @code\r | |
| 5732 | UINT64 Msr;\r | |
| 5733 | \r | |
| 5734 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL);\r | |
| 5735 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr);\r | |
| 5736 | @endcode\r | |
| a73ab083 | 5737 | @note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.\r |
| c67b579c | 5738 | **/\r |
| 2f88bd3a | 5739 | #define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00\r |
| c67b579c MK |
5740 | \r |
| 5741 | /**\r | |
| 5742 | Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.\r | |
| 5743 | \r | |
| 5744 | @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL0 (0x00000F01)\r | |
| 5745 | @param EAX Lower 32-bits of MSR value.\r | |
| 5746 | @param EDX Upper 32-bits of MSR value.\r | |
| 5747 | \r | |
| 5748 | <b>Example usage</b>\r | |
| 5749 | @code\r | |
| 5750 | UINT64 Msr;\r | |
| 5751 | \r | |
| 5752 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0);\r | |
| 5753 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr);\r | |
| 5754 | @endcode\r | |
| a73ab083 | 5755 | @note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 5756 | **/\r |
| 2f88bd3a | 5757 | #define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01\r |
| c67b579c MK |
5758 | \r |
| 5759 | /**\r | |
| 5760 | Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.\r | |
| 5761 | \r | |
| 5762 | @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL1 (0x00000F02)\r | |
| 5763 | @param EAX Lower 32-bits of MSR value.\r | |
| 5764 | @param EDX Upper 32-bits of MSR value.\r | |
| 5765 | \r | |
| 5766 | <b>Example usage</b>\r | |
| 5767 | @code\r | |
| 5768 | UINT64 Msr;\r | |
| 5769 | \r | |
| 5770 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1);\r | |
| 5771 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr);\r | |
| 5772 | @endcode\r | |
| a73ab083 | 5773 | @note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 5774 | **/\r |
| 2f88bd3a | 5775 | #define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02\r |
| c67b579c MK |
5776 | \r |
| 5777 | /**\r | |
| 5778 | Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.\r | |
| 5779 | \r | |
| 5780 | @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL2 (0x00000F03)\r | |
| 5781 | @param EAX Lower 32-bits of MSR value.\r | |
| 5782 | @param EDX Upper 32-bits of MSR value.\r | |
| 5783 | \r | |
| 5784 | <b>Example usage</b>\r | |
| 5785 | @code\r | |
| 5786 | UINT64 Msr;\r | |
| 5787 | \r | |
| 5788 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2);\r | |
| 5789 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr);\r | |
| 5790 | @endcode\r | |
| a73ab083 | 5791 | @note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 5792 | **/\r |
| 2f88bd3a | 5793 | #define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03\r |
| c67b579c MK |
5794 | \r |
| 5795 | /**\r | |
| 5796 | Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.\r | |
| 5797 | \r | |
| 5798 | @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL3 (0x00000F04)\r | |
| 5799 | @param EAX Lower 32-bits of MSR value.\r | |
| 5800 | @param EDX Upper 32-bits of MSR value.\r | |
| 5801 | \r | |
| 5802 | <b>Example usage</b>\r | |
| 5803 | @code\r | |
| 5804 | UINT64 Msr;\r | |
| 5805 | \r | |
| 5806 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3);\r | |
| 5807 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr);\r | |
| 5808 | @endcode\r | |
| a73ab083 | 5809 | @note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 5810 | **/\r |
| 2f88bd3a | 5811 | #define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04\r |
| c67b579c MK |
5812 | \r |
| 5813 | /**\r | |
| 5814 | Package. Uncore C-box 16 perfmon box wide filter 0.\r | |
| 5815 | \r | |
| 5816 | @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER0 (0x00000F05)\r | |
| 5817 | @param EAX Lower 32-bits of MSR value.\r | |
| 5818 | @param EDX Upper 32-bits of MSR value.\r | |
| 5819 | \r | |
| 5820 | <b>Example usage</b>\r | |
| 5821 | @code\r | |
| 5822 | UINT64 Msr;\r | |
| 5823 | \r | |
| 5824 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0);\r | |
| 5825 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr);\r | |
| 5826 | @endcode\r | |
| a73ab083 | 5827 | @note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c | 5828 | **/\r |
| 2f88bd3a | 5829 | #define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05\r |
| c67b579c MK |
5830 | \r |
| 5831 | /**\r | |
| 5832 | Package. Uncore C-box 16 perfmon box wide filter 1.\r | |
| 5833 | \r | |
| 5834 | @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER1 (0x00000F06)\r | |
| 5835 | @param EAX Lower 32-bits of MSR value.\r | |
| 5836 | @param EDX Upper 32-bits of MSR value.\r | |
| 5837 | \r | |
| 5838 | <b>Example usage</b>\r | |
| 5839 | @code\r | |
| 5840 | UINT64 Msr;\r | |
| 5841 | \r | |
| 5842 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1);\r | |
| 5843 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr);\r | |
| 5844 | @endcode\r | |
| a73ab083 | 5845 | @note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c | 5846 | **/\r |
| 2f88bd3a | 5847 | #define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06\r |
| c67b579c MK |
5848 | \r |
| 5849 | /**\r | |
| 5850 | Package. Uncore C-box 16 perfmon box wide status.\r | |
| 5851 | \r | |
| 5852 | @param ECX MSR_HASWELL_E_C16_PMON_BOX_STATUS (0x00000F07)\r | |
| 5853 | @param EAX Lower 32-bits of MSR value.\r | |
| 5854 | @param EDX Upper 32-bits of MSR value.\r | |
| 5855 | \r | |
| 5856 | <b>Example usage</b>\r | |
| 5857 | @code\r | |
| 5858 | UINT64 Msr;\r | |
| 5859 | \r | |
| 5860 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS);\r | |
| 5861 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr);\r | |
| 5862 | @endcode\r | |
| a73ab083 | 5863 | @note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 5864 | **/\r |
| 2f88bd3a | 5865 | #define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07\r |
| c67b579c MK |
5866 | \r |
| 5867 | /**\r | |
| 5868 | Package. Uncore C-box 16 perfmon counter 0.\r | |
| 5869 | \r | |
| 5870 | @param ECX MSR_HASWELL_E_C16_PMON_CTR0 (0x00000F08)\r | |
| 5871 | @param EAX Lower 32-bits of MSR value.\r | |
| 5872 | @param EDX Upper 32-bits of MSR value.\r | |
| 5873 | \r | |
| 5874 | <b>Example usage</b>\r | |
| 5875 | @code\r | |
| 5876 | UINT64 Msr;\r | |
| 5877 | \r | |
| 5878 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0);\r | |
| 5879 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr);\r | |
| 5880 | @endcode\r | |
| a73ab083 | 5881 | @note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.\r |
| c67b579c | 5882 | **/\r |
| 2f88bd3a | 5883 | #define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08\r |
| c67b579c MK |
5884 | \r |
| 5885 | /**\r | |
| 5886 | Package. Uncore C-box 16 perfmon counter 1.\r | |
| 5887 | \r | |
| 5888 | @param ECX MSR_HASWELL_E_C16_PMON_CTR1 (0x00000F09)\r | |
| 5889 | @param EAX Lower 32-bits of MSR value.\r | |
| 5890 | @param EDX Upper 32-bits of MSR value.\r | |
| 5891 | \r | |
| 5892 | <b>Example usage</b>\r | |
| 5893 | @code\r | |
| 5894 | UINT64 Msr;\r | |
| 5895 | \r | |
| 5896 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1);\r | |
| 5897 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr);\r | |
| 5898 | @endcode\r | |
| a73ab083 | 5899 | @note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.\r |
| c67b579c | 5900 | **/\r |
| 2f88bd3a | 5901 | #define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09\r |
| c67b579c MK |
5902 | \r |
| 5903 | /**\r | |
| 5904 | Package. Uncore C-box 16 perfmon counter 2.\r | |
| 5905 | \r | |
| 5906 | @param ECX MSR_HASWELL_E_C16_PMON_CTR2 (0x00000F0A)\r | |
| 5907 | @param EAX Lower 32-bits of MSR value.\r | |
| 5908 | @param EDX Upper 32-bits of MSR value.\r | |
| 5909 | \r | |
| 5910 | <b>Example usage</b>\r | |
| 5911 | @code\r | |
| 5912 | UINT64 Msr;\r | |
| 5913 | \r | |
| 5914 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2);\r | |
| 5915 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr);\r | |
| 5916 | @endcode\r | |
| a73ab083 | 5917 | @note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.\r |
| c67b579c | 5918 | **/\r |
| 2f88bd3a | 5919 | #define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A\r |
| c67b579c MK |
5920 | \r |
| 5921 | /**\r | |
| 5922 | Package. Uncore C-box 16 perfmon counter 3.\r | |
| 5923 | \r | |
| 5924 | @param ECX MSR_HASWELL_E_C16_PMON_CTR3 (0x00000E0B)\r | |
| 5925 | @param EAX Lower 32-bits of MSR value.\r | |
| 5926 | @param EDX Upper 32-bits of MSR value.\r | |
| 5927 | \r | |
| 5928 | <b>Example usage</b>\r | |
| 5929 | @code\r | |
| 5930 | UINT64 Msr;\r | |
| 5931 | \r | |
| 5932 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3);\r | |
| 5933 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr);\r | |
| 5934 | @endcode\r | |
| a73ab083 | 5935 | @note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.\r |
| c67b579c | 5936 | **/\r |
| 2f88bd3a | 5937 | #define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B\r |
| c67b579c MK |
5938 | \r |
| 5939 | /**\r | |
| 5940 | Package. Uncore C-box 17 perfmon for box-wide control.\r | |
| 5941 | \r | |
| 5942 | @param ECX MSR_HASWELL_E_C17_PMON_BOX_CTL (0x00000F10)\r | |
| 5943 | @param EAX Lower 32-bits of MSR value.\r | |
| 5944 | @param EDX Upper 32-bits of MSR value.\r | |
| 5945 | \r | |
| 5946 | <b>Example usage</b>\r | |
| 5947 | @code\r | |
| 5948 | UINT64 Msr;\r | |
| 5949 | \r | |
| 5950 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL);\r | |
| 5951 | AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr);\r | |
| 5952 | @endcode\r | |
| a73ab083 | 5953 | @note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.\r |
| c67b579c | 5954 | **/\r |
| 2f88bd3a | 5955 | #define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10\r |
| c67b579c MK |
5956 | \r |
| 5957 | /**\r | |
| 5958 | Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.\r | |
| 5959 | \r | |
| 5960 | @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL0 (0x00000F11)\r | |
| 5961 | @param EAX Lower 32-bits of MSR value.\r | |
| 5962 | @param EDX Upper 32-bits of MSR value.\r | |
| 5963 | \r | |
| 5964 | <b>Example usage</b>\r | |
| 5965 | @code\r | |
| 5966 | UINT64 Msr;\r | |
| 5967 | \r | |
| 5968 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0);\r | |
| 5969 | AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr);\r | |
| 5970 | @endcode\r | |
| a73ab083 | 5971 | @note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.\r |
| c67b579c | 5972 | **/\r |
| 2f88bd3a | 5973 | #define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11\r |
| c67b579c MK |
5974 | \r |
| 5975 | /**\r | |
| 5976 | Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.\r | |
| 5977 | \r | |
| 5978 | @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL1 (0x00000F12)\r | |
| 5979 | @param EAX Lower 32-bits of MSR value.\r | |
| 5980 | @param EDX Upper 32-bits of MSR value.\r | |
| 5981 | \r | |
| 5982 | <b>Example usage</b>\r | |
| 5983 | @code\r | |
| 5984 | UINT64 Msr;\r | |
| 5985 | \r | |
| 5986 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1);\r | |
| 5987 | AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr);\r | |
| 5988 | @endcode\r | |
| a73ab083 | 5989 | @note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.\r |
| c67b579c | 5990 | **/\r |
| 2f88bd3a | 5991 | #define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12\r |
| c67b579c MK |
5992 | \r |
| 5993 | /**\r | |
| 5994 | Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.\r | |
| 5995 | \r | |
| 5996 | @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL2 (0x00000F13)\r | |
| 5997 | @param EAX Lower 32-bits of MSR value.\r | |
| 5998 | @param EDX Upper 32-bits of MSR value.\r | |
| 5999 | \r | |
| 6000 | <b>Example usage</b>\r | |
| 6001 | @code\r | |
| 6002 | UINT64 Msr;\r | |
| 6003 | \r | |
| 6004 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2);\r | |
| 6005 | AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr);\r | |
| 6006 | @endcode\r | |
| a73ab083 | 6007 | @note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.\r |
| c67b579c | 6008 | **/\r |
| 2f88bd3a | 6009 | #define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13\r |
| c67b579c MK |
6010 | \r |
| 6011 | /**\r | |
| 6012 | Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.\r | |
| 6013 | \r | |
| 6014 | @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL3 (0x00000F14)\r | |
| 6015 | @param EAX Lower 32-bits of MSR value.\r | |
| 6016 | @param EDX Upper 32-bits of MSR value.\r | |
| 6017 | \r | |
| 6018 | <b>Example usage</b>\r | |
| 6019 | @code\r | |
| 6020 | UINT64 Msr;\r | |
| 6021 | \r | |
| 6022 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3);\r | |
| 6023 | AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr);\r | |
| 6024 | @endcode\r | |
| a73ab083 | 6025 | @note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.\r |
| c67b579c | 6026 | **/\r |
| 2f88bd3a | 6027 | #define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14\r |
| c67b579c MK |
6028 | \r |
| 6029 | /**\r | |
| 6030 | Package. Uncore C-box 17 perfmon box wide filter 0.\r | |
| 6031 | \r | |
| 6032 | @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER0 (0x00000F15)\r | |
| 6033 | @param EAX Lower 32-bits of MSR value.\r | |
| 6034 | @param EDX Upper 32-bits of MSR value.\r | |
| 6035 | \r | |
| 6036 | <b>Example usage</b>\r | |
| 6037 | @code\r | |
| 6038 | UINT64 Msr;\r | |
| 6039 | \r | |
| 6040 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0);\r | |
| 6041 | AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr);\r | |
| 6042 | @endcode\r | |
| a73ab083 | 6043 | @note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c | 6044 | **/\r |
| 2f88bd3a | 6045 | #define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15\r |
| c67b579c MK |
6046 | \r |
| 6047 | /**\r | |
| 6048 | Package. Uncore C-box 17 perfmon box wide filter1.\r | |
| 6049 | \r | |
| 6050 | @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER1 (0x00000F16)\r | |
| 6051 | @param EAX Lower 32-bits of MSR value.\r | |
| 6052 | @param EDX Upper 32-bits of MSR value.\r | |
| 6053 | \r | |
| 6054 | <b>Example usage</b>\r | |
| 6055 | @code\r | |
| 6056 | UINT64 Msr;\r | |
| 6057 | \r | |
| 6058 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1);\r | |
| 6059 | AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr);\r | |
| 6060 | @endcode\r | |
| a73ab083 | 6061 | @note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c | 6062 | **/\r |
| 2f88bd3a | 6063 | #define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16\r |
| c67b579c MK |
6064 | \r |
| 6065 | /**\r | |
| 6066 | Package. Uncore C-box 17 perfmon box wide status.\r | |
| 6067 | \r | |
| 6068 | @param ECX MSR_HASWELL_E_C17_PMON_BOX_STATUS (0x00000F17)\r | |
| 6069 | @param EAX Lower 32-bits of MSR value.\r | |
| 6070 | @param EDX Upper 32-bits of MSR value.\r | |
| 6071 | \r | |
| 6072 | <b>Example usage</b>\r | |
| 6073 | @code\r | |
| 6074 | UINT64 Msr;\r | |
| 6075 | \r | |
| 6076 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS);\r | |
| 6077 | AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr);\r | |
| 6078 | @endcode\r | |
| a73ab083 | 6079 | @note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.\r |
| c67b579c | 6080 | **/\r |
| 2f88bd3a | 6081 | #define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17\r |
| c67b579c MK |
6082 | \r |
| 6083 | /**\r | |
| 6084 | Package. Uncore C-box 17 perfmon counter n.\r | |
| 6085 | \r | |
| 6086 | @param ECX MSR_HASWELL_E_C17_PMON_CTRn\r | |
| 6087 | @param EAX Lower 32-bits of MSR value.\r | |
| 6088 | @param EDX Upper 32-bits of MSR value.\r | |
| 6089 | \r | |
| 6090 | <b>Example usage</b>\r | |
| 6091 | @code\r | |
| 6092 | UINT64 Msr;\r | |
| 6093 | \r | |
| 6094 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);\r | |
| 6095 | AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);\r | |
| 6096 | @endcode\r | |
| a73ab083 JF |
6097 | @note MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM.\r |
| 6098 | MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM.\r | |
| 6099 | MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM.\r | |
| 6100 | MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.\r | |
| c67b579c MK |
6101 | @{\r |
| 6102 | **/\r | |
| 2f88bd3a MK |
6103 | #define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18\r |
| 6104 | #define MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19\r | |
| 6105 | #define MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A\r | |
| 6106 | #define MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B\r | |
| c67b579c MK |
6107 | /// @}\r |
| 6108 | \r | |
| 6109 | #endif\r |