projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 6b55a245 | 1 | /** @file\r |
| 788421d5 | 2 | MSR Definitions for Intel processors based on the Skylake/Kabylake/Coffeelake/Cannonlake microarchitecture.\r |
| 6b55a245 MK |
3 | \r |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
| 7 | provided for that MSR.\r | |
| 8 | \r | |
| e057908f | 9 | Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r |
| 0acd8697 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 6b55a245 MK |
11 | \r |
| 12 | @par Specification Reference:\r | |
| ba1a2d11 ED |
13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r |
| 14 | May 2018, Volume 4: Model-Specific-Registers (MSR)\r | |
| 6b55a245 MK |
15 | \r |
| 16 | **/\r | |
| 17 | \r | |
| 18 | #ifndef __SKYLAKE_MSR_H__\r | |
| 19 | #define __SKYLAKE_MSR_H__\r | |
| 20 | \r | |
| e057908f | 21 | #include <Register/Intel/ArchitecturalMsr.h>\r |
| 6b55a245 | 22 | \r |
| f4c982bf JF |
23 | /**\r |
| 24 | Is Intel processors based on the Skylake microarchitecture?\r | |
| 25 | \r | |
| 26 | @param DisplayFamily Display Family ID\r | |
| 27 | @param DisplayModel Display Model ID\r | |
| 28 | \r | |
| 29 | @retval TRUE Yes, it is.\r | |
| 30 | @retval FALSE No, it isn't.\r | |
| 31 | **/\r | |
| 32 | #define IS_SKYLAKE_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
| 33 | (DisplayFamily == 0x06 && \\r | |
| 34 | ( \\r | |
| 35 | DisplayModel == 0x4E || \\r | |
| 3add0205 ED |
36 | DisplayModel == 0x5E || \\r |
| 37 | DisplayModel == 0x55 || \\r | |
| 38 | DisplayModel == 0x8E || \\r | |
| 39 | DisplayModel == 0x9E || \\r | |
| 40 | DisplayModel == 0x66 \\r | |
| f4c982bf JF |
41 | ) \\r |
| 42 | )\r | |
| 43 | \r | |
| 6b55a245 MK |
44 | /**\r |
| 45 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r | |
| 46 | RW if MSR_PLATFORM_INFO.[28] = 1.\r | |
| 47 | \r | |
| 48 | @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x000001AD)\r | |
| 49 | @param EAX Lower 32-bits of MSR value.\r | |
| 50 | Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.\r | |
| 51 | @param EDX Upper 32-bits of MSR value.\r | |
| 52 | Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.\r | |
| 53 | \r | |
| 54 | <b>Example usage</b>\r | |
| 55 | @code\r | |
| 56 | MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER Msr;\r | |
| 57 | \r | |
| 58 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT);\r | |
| 59 | @endcode\r | |
| 04e7a465 | 60 | @note MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r |
| 6b55a245 | 61 | **/\r |
| 2f88bd3a | 62 | #define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD\r |
| 6b55a245 MK |
63 | \r |
| 64 | /**\r | |
| 65 | MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT\r | |
| 66 | **/\r | |
| 67 | typedef union {\r | |
| 68 | ///\r | |
| 69 | /// Individual bit fields\r | |
| 70 | ///\r | |
| 71 | struct {\r | |
| 72 | ///\r | |
| 73 | /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r | |
| 74 | /// limit of 1 core active.\r | |
| 75 | ///\r | |
| 2f88bd3a | 76 | UINT32 Maximum1C : 8;\r |
| 6b55a245 MK |
77 | ///\r |
| 78 | /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r | |
| 79 | /// limit of 2 core active.\r | |
| 80 | ///\r | |
| 2f88bd3a | 81 | UINT32 Maximum2C : 8;\r |
| 6b55a245 MK |
82 | ///\r |
| 83 | /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r | |
| 84 | /// limit of 3 core active.\r | |
| 85 | ///\r | |
| 2f88bd3a | 86 | UINT32 Maximum3C : 8;\r |
| 6b55a245 MK |
87 | ///\r |
| 88 | /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r | |
| 89 | /// limit of 4 core active.\r | |
| 90 | ///\r | |
| 2f88bd3a MK |
91 | UINT32 Maximum4C : 8;\r |
| 92 | UINT32 Reserved : 32;\r | |
| 6b55a245 MK |
93 | } Bits;\r |
| 94 | ///\r | |
| 95 | /// All bit fields as a 32-bit value\r | |
| 96 | ///\r | |
| 2f88bd3a | 97 | UINT32 Uint32;\r |
| 6b55a245 MK |
98 | ///\r |
| 99 | /// All bit fields as a 64-bit value\r | |
| 100 | ///\r | |
| 2f88bd3a | 101 | UINT64 Uint64;\r |
| 6b55a245 MK |
102 | } MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER;\r |
| 103 | \r | |
| 6b55a245 MK |
104 | /**\r |
| 105 | Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4)\r | |
| 106 | that points to the MSR containing the most recent branch record.\r | |
| 107 | \r | |
| 108 | @param ECX MSR_SKYLAKE_LASTBRANCH_TOS (0x000001C9)\r | |
| 109 | @param EAX Lower 32-bits of MSR value.\r | |
| 110 | @param EDX Upper 32-bits of MSR value.\r | |
| 111 | \r | |
| 112 | <b>Example usage</b>\r | |
| 113 | @code\r | |
| 114 | UINT64 Msr;\r | |
| 115 | \r | |
| 116 | Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS);\r | |
| 117 | AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr);\r | |
| 118 | @endcode\r | |
| 04e7a465 | 119 | @note MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r |
| 6b55a245 | 120 | **/\r |
| 2f88bd3a | 121 | #define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9\r |
| 6b55a245 | 122 | \r |
| 3add0205 ED |
123 | /**\r |
| 124 | Core. Power Control Register See http://biosbits.org.\r | |
| 125 | \r | |
| 126 | @param ECX MSR_SKYLAKE_POWER_CTL (0x000001FC)\r | |
| 127 | @param EAX Lower 32-bits of MSR value.\r | |
| 128 | Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.\r | |
| 129 | @param EDX Upper 32-bits of MSR value.\r | |
| 130 | Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.\r | |
| 131 | \r | |
| 132 | <b>Example usage</b>\r | |
| 133 | @code\r | |
| 134 | MSR_SKYLAKE_POWER_CTL_REGISTER Msr;\r | |
| 135 | \r | |
| 136 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_POWER_CTL);\r | |
| 137 | AsmWriteMsr64 (MSR_SKYLAKE_POWER_CTL, Msr.Uint64);\r | |
| 138 | @endcode\r | |
| 139 | **/\r | |
| 2f88bd3a | 140 | #define MSR_SKYLAKE_POWER_CTL 0x000001FC\r |
| 3add0205 ED |
141 | \r |
| 142 | /**\r | |
| 143 | MSR information returned for MSR index #MSR_SKYLAKE_POWER_CTL\r | |
| 144 | **/\r | |
| 145 | typedef union {\r | |
| 146 | ///\r | |
| 147 | /// Individual bit fields\r | |
| 148 | ///\r | |
| 149 | struct {\r | |
| 2f88bd3a | 150 | UINT32 Reserved1 : 1;\r |
| 3add0205 ED |
151 | ///\r |
| 152 | /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU\r | |
| 153 | /// to switch to the Minimum Enhanced Intel SpeedStep Technology operating\r | |
| 154 | /// point when all execution cores enter MWAIT (C1).\r | |
| 155 | ///\r | |
| 2f88bd3a MK |
156 | UINT32 C1EEnable : 1;\r |
| 157 | UINT32 Reserved2 : 17;\r | |
| 3add0205 ED |
158 | ///\r |
| 159 | /// [Bit 19] Disable Race to Halt Optimization (R/W) Setting this bit\r | |
| 160 | /// disables the Race to Halt optimization and avoids this optimization\r | |
| 161 | /// limitation to execute below the most efficient frequency ratio.\r | |
| 162 | /// Default value is 0 for processors that support Race to Halt\r | |
| 163 | /// optimization. Default value is 1 for processors that do not support\r | |
| 164 | /// Race to Halt optimization.\r | |
| 165 | ///\r | |
| 2f88bd3a | 166 | UINT32 Fix_Me_1 : 1;\r |
| 3add0205 ED |
167 | ///\r |
| 168 | /// [Bit 20] Disable Energy Efficiency Optimization (R/W) Setting this bit\r | |
| 169 | /// disables the P-States energy efficiency optimization. Default value is\r | |
| 170 | /// 0. Disable/enable the energy efficiency optimization in P-State legacy\r | |
| 171 | /// mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the\r | |
| 172 | /// turbo range or into PERF_MIN_CTL value if it is not zero set. In HWP\r | |
| 173 | /// mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS\r | |
| 174 | /// desired or OS maximize to the OS minimize performance setting.\r | |
| 175 | ///\r | |
| 2f88bd3a MK |
176 | UINT32 DisableEnergyEfficiencyOptimization : 1;\r |
| 177 | UINT32 Reserved3 : 11;\r | |
| 178 | UINT32 Reserved4 : 32;\r | |
| 3add0205 ED |
179 | } Bits;\r |
| 180 | ///\r | |
| 181 | /// All bit fields as a 32-bit value\r | |
| 182 | ///\r | |
| 2f88bd3a | 183 | UINT32 Uint32;\r |
| 3add0205 ED |
184 | ///\r |
| 185 | /// All bit fields as a 64-bit value\r | |
| 186 | ///\r | |
| 2f88bd3a | 187 | UINT64 Uint64;\r |
| 3add0205 ED |
188 | } MSR_SKYLAKE_POWER_CTL_REGISTER;\r |
| 189 | \r | |
| 6b55a245 | 190 | /**\r |
| 8b344785 ED |
191 | Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update\r |
| 192 | CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in\r | |
| 193 | the package. Lower 64 bits of an 128-bit external entropy value for key\r | |
| 194 | derivation of an enclave.\r | |
| 6b55a245 | 195 | \r |
| 8b344785 | 196 | @param ECX MSR_SKYLAKE_SGXOWNEREPOCH0 (0x00000300)\r |
| 6b55a245 MK |
197 | @param EAX Lower 32-bits of MSR value.\r |
| 198 | @param EDX Upper 32-bits of MSR value.\r | |
| 199 | \r | |
| 200 | <b>Example usage</b>\r | |
| 201 | @code\r | |
| 202 | UINT64 Msr;\r | |
| 203 | \r | |
| 8b344785 ED |
204 | Msr = 0;\r |
| 205 | AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH0, Msr);\r | |
| 6b55a245 | 206 | @endcode\r |
| 8b344785 | 207 | @note MSR_SKYLAKE_SGXOWNEREPOCH0 is defined as MSR_SGXOWNER0 in SDM.\r |
| 6b55a245 | 208 | **/\r |
| 2f88bd3a | 209 | #define MSR_SKYLAKE_SGXOWNEREPOCH0 0x00000300\r |
| 6b55a245 | 210 | \r |
| 8b344785 ED |
211 | //\r |
| 212 | // Define MSR_SKYLAKE_SGXOWNER0 for compatibility due to name change in the SDM.\r | |
| 213 | //\r | |
| 2f88bd3a MK |
214 | #define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0\r |
| 215 | \r | |
| 6b55a245 | 216 | /**\r |
| 8b344785 ED |
217 | Package. Upper 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update\r |
| 218 | CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in\r | |
| 219 | the package. Upper 64 bits of an 128-bit external entropy value for key\r | |
| 220 | derivation of an enclave.\r | |
| 6b55a245 | 221 | \r |
| 8b344785 | 222 | @param ECX MSR_SKYLAKE_SGXOWNEREPOCH1 (0x00000301)\r |
| 6b55a245 MK |
223 | @param EAX Lower 32-bits of MSR value.\r |
| 224 | @param EDX Upper 32-bits of MSR value.\r | |
| 225 | \r | |
| 226 | <b>Example usage</b>\r | |
| 227 | @code\r | |
| 228 | UINT64 Msr;\r | |
| 229 | \r | |
| 8b344785 ED |
230 | Msr = 0;\r |
| 231 | AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH1, Msr);\r | |
| 6b55a245 | 232 | @endcode\r |
| 8b344785 | 233 | @note MSR_SKYLAKE_SGXOWNEREPOCH1 is defined as MSR_SGXOWNER1 in SDM.\r |
| 6b55a245 | 234 | **/\r |
| 2f88bd3a | 235 | #define MSR_SKYLAKE_SGXOWNEREPOCH1 0x00000301\r |
| 8b344785 ED |
236 | \r |
| 237 | //\r | |
| 238 | // Define MSR_SKYLAKE_SGXOWNER1 for compatibility due to name change in the SDM.\r | |
| 239 | //\r | |
| 2f88bd3a | 240 | #define MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1\r |
| 6b55a245 MK |
241 | \r |
| 242 | /**\r | |
| ba1a2d11 | 243 | See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring\r |
| 37cea63f | 244 | Version 4.".\r |
| 6b55a245 | 245 | \r |
| 37cea63f | 246 | @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r |
| 6b55a245 | 247 | @param EAX Lower 32-bits of MSR value.\r |
| 37cea63f | 248 | Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r |
| 6b55a245 | 249 | @param EDX Upper 32-bits of MSR value.\r |
| 37cea63f | 250 | Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r |
| 6b55a245 MK |
251 | \r |
| 252 | <b>Example usage</b>\r | |
| 253 | @code\r | |
| 37cea63f | 254 | MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r |
| 6b55a245 | 255 | \r |
| 37cea63f HW |
256 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS);\r |
| 257 | AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r | |
| 6b55a245 | 258 | @endcode\r |
| 37cea63f | 259 | @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r |
| 6b55a245 | 260 | **/\r |
| 2f88bd3a | 261 | #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E\r |
| 6b55a245 MK |
262 | \r |
| 263 | /**\r | |
| 37cea63f | 264 | MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS\r |
| 6b55a245 MK |
265 | **/\r |
| 266 | typedef union {\r | |
| 267 | ///\r | |
| 268 | /// Individual bit fields\r | |
| 269 | ///\r | |
| 270 | struct {\r | |
| 271 | ///\r | |
| 272 | /// [Bit 0] Thread. Ovf_PMC0.\r | |
| 273 | ///\r | |
| 2f88bd3a | 274 | UINT32 Ovf_PMC0 : 1;\r |
| 6b55a245 MK |
275 | ///\r |
| 276 | /// [Bit 1] Thread. Ovf_PMC1.\r | |
| 277 | ///\r | |
| 2f88bd3a | 278 | UINT32 Ovf_PMC1 : 1;\r |
| 6b55a245 MK |
279 | ///\r |
| 280 | /// [Bit 2] Thread. Ovf_PMC2.\r | |
| 281 | ///\r | |
| 2f88bd3a | 282 | UINT32 Ovf_PMC2 : 1;\r |
| 6b55a245 MK |
283 | ///\r |
| 284 | /// [Bit 3] Thread. Ovf_PMC3.\r | |
| 285 | ///\r | |
| 2f88bd3a | 286 | UINT32 Ovf_PMC3 : 1;\r |
| 6b55a245 MK |
287 | ///\r |
| 288 | /// [Bit 4] Thread. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r | |
| 289 | ///\r | |
| 2f88bd3a | 290 | UINT32 Ovf_PMC4 : 1;\r |
| 6b55a245 MK |
291 | ///\r |
| 292 | /// [Bit 5] Thread. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r | |
| 293 | ///\r | |
| 2f88bd3a | 294 | UINT32 Ovf_PMC5 : 1;\r |
| 6b55a245 MK |
295 | ///\r |
| 296 | /// [Bit 6] Thread. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r | |
| 297 | ///\r | |
| 2f88bd3a | 298 | UINT32 Ovf_PMC6 : 1;\r |
| 6b55a245 MK |
299 | ///\r |
| 300 | /// [Bit 7] Thread. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r | |
| 301 | ///\r | |
| 2f88bd3a MK |
302 | UINT32 Ovf_PMC7 : 1;\r |
| 303 | UINT32 Reserved1 : 24;\r | |
| 6b55a245 MK |
304 | ///\r |
| 305 | /// [Bit 32] Thread. Ovf_FixedCtr0.\r | |
| 306 | ///\r | |
| 2f88bd3a | 307 | UINT32 Ovf_FixedCtr0 : 1;\r |
| 6b55a245 MK |
308 | ///\r |
| 309 | /// [Bit 33] Thread. Ovf_FixedCtr1.\r | |
| 310 | ///\r | |
| 2f88bd3a | 311 | UINT32 Ovf_FixedCtr1 : 1;\r |
| 6b55a245 MK |
312 | ///\r |
| 313 | /// [Bit 34] Thread. Ovf_FixedCtr2.\r | |
| 314 | ///\r | |
| 2f88bd3a MK |
315 | UINT32 Ovf_FixedCtr2 : 1;\r |
| 316 | UINT32 Reserved2 : 20;\r | |
| 6b55a245 MK |
317 | ///\r |
| 318 | /// [Bit 55] Thread. Trace_ToPA_PMI.\r | |
| 319 | ///\r | |
| 2f88bd3a MK |
320 | UINT32 Trace_ToPA_PMI : 1;\r |
| 321 | UINT32 Reserved3 : 2;\r | |
| 6b55a245 MK |
322 | ///\r |
| 323 | /// [Bit 58] Thread. LBR_Frz.\r | |
| 324 | ///\r | |
| 2f88bd3a | 325 | UINT32 LBR_Frz : 1;\r |
| 6b55a245 MK |
326 | ///\r |
| 327 | /// [Bit 59] Thread. CTR_Frz.\r | |
| 328 | ///\r | |
| 2f88bd3a | 329 | UINT32 CTR_Frz : 1;\r |
| 6b55a245 MK |
330 | ///\r |
| 331 | /// [Bit 60] Thread. ASCI.\r | |
| 332 | ///\r | |
| 2f88bd3a | 333 | UINT32 ASCI : 1;\r |
| 6b55a245 MK |
334 | ///\r |
| 335 | /// [Bit 61] Thread. Ovf_Uncore.\r | |
| 336 | ///\r | |
| 2f88bd3a | 337 | UINT32 Ovf_Uncore : 1;\r |
| 6b55a245 MK |
338 | ///\r |
| 339 | /// [Bit 62] Thread. Ovf_BufDSSAVE.\r | |
| 340 | ///\r | |
| 2f88bd3a | 341 | UINT32 Ovf_BufDSSAVE : 1;\r |
| 6b55a245 MK |
342 | ///\r |
| 343 | /// [Bit 63] Thread. CondChgd.\r | |
| 344 | ///\r | |
| 2f88bd3a | 345 | UINT32 CondChgd : 1;\r |
| 6b55a245 MK |
346 | } Bits;\r |
| 347 | ///\r | |
| 348 | /// All bit fields as a 64-bit value\r | |
| 349 | ///\r | |
| 2f88bd3a | 350 | UINT64 Uint64;\r |
| 37cea63f | 351 | } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER;\r |
| 6b55a245 | 352 | \r |
| 6b55a245 | 353 | /**\r |
| ba1a2d11 | 354 | See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring\r |
| 37cea63f | 355 | Version 4.".\r |
| 6b55a245 MK |
356 | \r |
| 357 | @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r | |
| 358 | @param EAX Lower 32-bits of MSR value.\r | |
| 359 | Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r | |
| 360 | @param EDX Upper 32-bits of MSR value.\r | |
| 361 | Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r | |
| 362 | \r | |
| 363 | <b>Example usage</b>\r | |
| 364 | @code\r | |
| 365 | MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;\r | |
| 366 | \r | |
| 367 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET);\r | |
| 368 | AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r | |
| 369 | @endcode\r | |
| 04e7a465 | 370 | @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r |
| 6b55a245 | 371 | **/\r |
| 2f88bd3a | 372 | #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r |
| 6b55a245 MK |
373 | \r |
| 374 | /**\r | |
| 375 | MSR information returned for MSR index\r | |
| 376 | #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET\r | |
| 377 | **/\r | |
| 378 | typedef union {\r | |
| 379 | ///\r | |
| 380 | /// Individual bit fields\r | |
| 381 | ///\r | |
| 382 | struct {\r | |
| 383 | ///\r | |
| 384 | /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.\r | |
| 385 | ///\r | |
| 2f88bd3a | 386 | UINT32 Ovf_PMC0 : 1;\r |
| 6b55a245 MK |
387 | ///\r |
| 388 | /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.\r | |
| 389 | ///\r | |
| 2f88bd3a | 390 | UINT32 Ovf_PMC1 : 1;\r |
| 6b55a245 MK |
391 | ///\r |
| 392 | /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.\r | |
| 393 | ///\r | |
| 2f88bd3a | 394 | UINT32 Ovf_PMC2 : 1;\r |
| 6b55a245 MK |
395 | ///\r |
| 396 | /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.\r | |
| 397 | ///\r | |
| 2f88bd3a | 398 | UINT32 Ovf_PMC3 : 1;\r |
| 6b55a245 MK |
399 | ///\r |
| 400 | /// [Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r | |
| 401 | ///\r | |
| 2f88bd3a | 402 | UINT32 Ovf_PMC4 : 1;\r |
| 6b55a245 MK |
403 | ///\r |
| 404 | /// [Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r | |
| 405 | ///\r | |
| 2f88bd3a | 406 | UINT32 Ovf_PMC5 : 1;\r |
| 6b55a245 MK |
407 | ///\r |
| 408 | /// [Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r | |
| 409 | ///\r | |
| 2f88bd3a | 410 | UINT32 Ovf_PMC6 : 1;\r |
| 6b55a245 MK |
411 | ///\r |
| 412 | /// [Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r | |
| 413 | ///\r | |
| 2f88bd3a MK |
414 | UINT32 Ovf_PMC7 : 1;\r |
| 415 | UINT32 Reserved1 : 24;\r | |
| 6b55a245 MK |
416 | ///\r |
| 417 | /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.\r | |
| 418 | ///\r | |
| 2f88bd3a | 419 | UINT32 Ovf_FixedCtr0 : 1;\r |
| 6b55a245 MK |
420 | ///\r |
| 421 | /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.\r | |
| 422 | ///\r | |
| 2f88bd3a | 423 | UINT32 Ovf_FixedCtr1 : 1;\r |
| 6b55a245 MK |
424 | ///\r |
| 425 | /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.\r | |
| 426 | ///\r | |
| 2f88bd3a MK |
427 | UINT32 Ovf_FixedCtr2 : 1;\r |
| 428 | UINT32 Reserved2 : 20;\r | |
| 6b55a245 MK |
429 | ///\r |
| 430 | /// [Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI.\r | |
| 431 | ///\r | |
| 2f88bd3a MK |
432 | UINT32 Trace_ToPA_PMI : 1;\r |
| 433 | UINT32 Reserved3 : 2;\r | |
| 6b55a245 MK |
434 | ///\r |
| 435 | /// [Bit 58] Thread. Set 1 to clear LBR_Frz.\r | |
| 436 | ///\r | |
| 2f88bd3a | 437 | UINT32 LBR_Frz : 1;\r |
| 6b55a245 MK |
438 | ///\r |
| 439 | /// [Bit 59] Thread. Set 1 to clear CTR_Frz.\r | |
| 440 | ///\r | |
| 2f88bd3a | 441 | UINT32 CTR_Frz : 1;\r |
| 6b55a245 MK |
442 | ///\r |
| 443 | /// [Bit 60] Thread. Set 1 to clear ASCI.\r | |
| 444 | ///\r | |
| 2f88bd3a | 445 | UINT32 ASCI : 1;\r |
| 6b55a245 MK |
446 | ///\r |
| 447 | /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.\r | |
| 448 | ///\r | |
| 2f88bd3a | 449 | UINT32 Ovf_Uncore : 1;\r |
| 6b55a245 MK |
450 | ///\r |
| 451 | /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.\r | |
| 452 | ///\r | |
| 2f88bd3a | 453 | UINT32 Ovf_BufDSSAVE : 1;\r |
| 6b55a245 MK |
454 | ///\r |
| 455 | /// [Bit 63] Thread. Set 1 to clear CondChgd.\r | |
| 456 | ///\r | |
| 2f88bd3a | 457 | UINT32 CondChgd : 1;\r |
| 6b55a245 MK |
458 | } Bits;\r |
| 459 | ///\r | |
| 460 | /// All bit fields as a 64-bit value\r | |
| 461 | ///\r | |
| 2f88bd3a | 462 | UINT64 Uint64;\r |
| 6b55a245 MK |
463 | } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r |
| 464 | \r | |
| 6b55a245 | 465 | /**\r |
| ba1a2d11 | 466 | See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring\r |
| 37cea63f | 467 | Version 4.".\r |
| 6b55a245 MK |
468 | \r |
| 469 | @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r | |
| 470 | @param EAX Lower 32-bits of MSR value.\r | |
| 471 | Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r | |
| 472 | @param EDX Upper 32-bits of MSR value.\r | |
| 473 | Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r | |
| 474 | \r | |
| 475 | <b>Example usage</b>\r | |
| 476 | @code\r | |
| 477 | MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;\r | |
| 478 | \r | |
| 479 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET);\r | |
| 480 | AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r | |
| 481 | @endcode\r | |
| 04e7a465 | 482 | @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r |
| 6b55a245 MK |
483 | **/\r |
| 484 | #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r | |
| 485 | \r | |
| 486 | /**\r | |
| 487 | MSR information returned for MSR index\r | |
| 488 | #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET\r | |
| 489 | **/\r | |
| 490 | typedef union {\r | |
| 491 | ///\r | |
| 492 | /// Individual bit fields\r | |
| 493 | ///\r | |
| 494 | struct {\r | |
| 495 | ///\r | |
| 496 | /// [Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1.\r | |
| 497 | ///\r | |
| 2f88bd3a | 498 | UINT32 Ovf_PMC0 : 1;\r |
| 6b55a245 MK |
499 | ///\r |
| 500 | /// [Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1.\r | |
| 501 | ///\r | |
| 2f88bd3a | 502 | UINT32 Ovf_PMC1 : 1;\r |
| 6b55a245 MK |
503 | ///\r |
| 504 | /// [Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1.\r | |
| 505 | ///\r | |
| 2f88bd3a | 506 | UINT32 Ovf_PMC2 : 1;\r |
| 6b55a245 MK |
507 | ///\r |
| 508 | /// [Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1.\r | |
| 509 | ///\r | |
| 2f88bd3a | 510 | UINT32 Ovf_PMC3 : 1;\r |
| 6b55a245 MK |
511 | ///\r |
| 512 | /// [Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4).\r | |
| 513 | ///\r | |
| 2f88bd3a | 514 | UINT32 Ovf_PMC4 : 1;\r |
| 6b55a245 MK |
515 | ///\r |
| 516 | /// [Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5).\r | |
| 517 | ///\r | |
| 2f88bd3a | 518 | UINT32 Ovf_PMC5 : 1;\r |
| 6b55a245 MK |
519 | ///\r |
| 520 | /// [Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6).\r | |
| 521 | ///\r | |
| 2f88bd3a | 522 | UINT32 Ovf_PMC6 : 1;\r |
| 6b55a245 MK |
523 | ///\r |
| 524 | /// [Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7).\r | |
| 525 | ///\r | |
| 2f88bd3a MK |
526 | UINT32 Ovf_PMC7 : 1;\r |
| 527 | UINT32 Reserved1 : 24;\r | |
| 6b55a245 MK |
528 | ///\r |
| 529 | /// [Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1.\r | |
| 530 | ///\r | |
| 2f88bd3a | 531 | UINT32 Ovf_FixedCtr0 : 1;\r |
| 6b55a245 MK |
532 | ///\r |
| 533 | /// [Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1.\r | |
| 534 | ///\r | |
| 2f88bd3a | 535 | UINT32 Ovf_FixedCtr1 : 1;\r |
| 6b55a245 MK |
536 | ///\r |
| 537 | /// [Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1.\r | |
| 538 | ///\r | |
| 2f88bd3a MK |
539 | UINT32 Ovf_FixedCtr2 : 1;\r |
| 540 | UINT32 Reserved2 : 20;\r | |
| 6b55a245 MK |
541 | ///\r |
| 542 | /// [Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1.\r | |
| 543 | ///\r | |
| 2f88bd3a MK |
544 | UINT32 Trace_ToPA_PMI : 1;\r |
| 545 | UINT32 Reserved3 : 2;\r | |
| 6b55a245 MK |
546 | ///\r |
| 547 | /// [Bit 58] Thread. Set 1 to cause LBR_Frz = 1.\r | |
| 548 | ///\r | |
| 2f88bd3a | 549 | UINT32 LBR_Frz : 1;\r |
| 6b55a245 MK |
550 | ///\r |
| 551 | /// [Bit 59] Thread. Set 1 to cause CTR_Frz = 1.\r | |
| 552 | ///\r | |
| 2f88bd3a | 553 | UINT32 CTR_Frz : 1;\r |
| 6b55a245 MK |
554 | ///\r |
| 555 | /// [Bit 60] Thread. Set 1 to cause ASCI = 1.\r | |
| 556 | ///\r | |
| 2f88bd3a | 557 | UINT32 ASCI : 1;\r |
| 6b55a245 MK |
558 | ///\r |
| 559 | /// [Bit 61] Thread. Set 1 to cause Ovf_Uncore.\r | |
| 560 | ///\r | |
| 2f88bd3a | 561 | UINT32 Ovf_Uncore : 1;\r |
| 6b55a245 MK |
562 | ///\r |
| 563 | /// [Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE.\r | |
| 564 | ///\r | |
| 2f88bd3a MK |
565 | UINT32 Ovf_BufDSSAVE : 1;\r |
| 566 | UINT32 Reserved4 : 1;\r | |
| 6b55a245 MK |
567 | } Bits;\r |
| 568 | ///\r | |
| 569 | /// All bit fields as a 64-bit value\r | |
| 570 | ///\r | |
| 2f88bd3a | 571 | UINT64 Uint64;\r |
| 6b55a245 MK |
572 | } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r |
| 573 | \r | |
| 6b55a245 MK |
574 | /**\r |
| 575 | Thread. FrontEnd Precise Event Condition Select (R/W).\r | |
| 576 | \r | |
| 577 | @param ECX MSR_SKYLAKE_PEBS_FRONTEND (0x000003F7)\r | |
| 578 | @param EAX Lower 32-bits of MSR value.\r | |
| 579 | Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.\r | |
| 580 | @param EDX Upper 32-bits of MSR value.\r | |
| 581 | Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.\r | |
| 582 | \r | |
| 583 | <b>Example usage</b>\r | |
| 584 | @code\r | |
| 585 | MSR_SKYLAKE_PEBS_FRONTEND_REGISTER Msr;\r | |
| 586 | \r | |
| 587 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND);\r | |
| 588 | AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64);\r | |
| 589 | @endcode\r | |
| 04e7a465 | 590 | @note MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM.\r |
| 6b55a245 | 591 | **/\r |
| 2f88bd3a | 592 | #define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7\r |
| 6b55a245 MK |
593 | \r |
| 594 | /**\r | |
| 595 | MSR information returned for MSR index #MSR_SKYLAKE_PEBS_FRONTEND\r | |
| 596 | **/\r | |
| 597 | typedef union {\r | |
| 598 | ///\r | |
| 599 | /// Individual bit fields\r | |
| 600 | ///\r | |
| 601 | struct {\r | |
| 602 | ///\r | |
| 603 | /// [Bits 2:0] Event Code Select.\r | |
| 604 | ///\r | |
| 2f88bd3a MK |
605 | UINT32 EventCodeSelect : 3;\r |
| 606 | UINT32 Reserved1 : 1;\r | |
| 6b55a245 MK |
607 | ///\r |
| 608 | /// [Bit 4] Event Code Select High.\r | |
| 609 | ///\r | |
| 2f88bd3a MK |
610 | UINT32 EventCodeSelectHigh : 1;\r |
| 611 | UINT32 Reserved2 : 3;\r | |
| 6b55a245 MK |
612 | ///\r |
| 613 | /// [Bits 19:8] IDQ_Bubble_Length Specifier.\r | |
| 614 | ///\r | |
| 2f88bd3a | 615 | UINT32 IDQ_Bubble_Length : 12;\r |
| 6b55a245 MK |
616 | ///\r |
| 617 | /// [Bits 22:20] IDQ_Bubble_Width Specifier.\r | |
| 618 | ///\r | |
| 2f88bd3a MK |
619 | UINT32 IDQ_Bubble_Width : 3;\r |
| 620 | UINT32 Reserved3 : 9;\r | |
| 621 | UINT32 Reserved4 : 32;\r | |
| 6b55a245 MK |
622 | } Bits;\r |
| 623 | ///\r | |
| 624 | /// All bit fields as a 32-bit value\r | |
| 625 | ///\r | |
| 2f88bd3a | 626 | UINT32 Uint32;\r |
| 6b55a245 MK |
627 | ///\r |
| 628 | /// All bit fields as a 64-bit value\r | |
| 629 | ///\r | |
| 2f88bd3a | 630 | UINT64 Uint64;\r |
| 6b55a245 MK |
631 | } MSR_SKYLAKE_PEBS_FRONTEND_REGISTER;\r |
| 632 | \r | |
| 37cea63f HW |
633 | /**\r |
| 634 | Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r | |
| 635 | Domains.".\r | |
| 636 | \r | |
| 637 | @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)\r | |
| 638 | @param EAX Lower 32-bits of MSR value.\r | |
| 639 | @param EDX Upper 32-bits of MSR value.\r | |
| 640 | \r | |
| 641 | <b>Example usage</b>\r | |
| 642 | @code\r | |
| 643 | UINT64 Msr;\r | |
| 644 | \r | |
| 645 | Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);\r | |
| 646 | @endcode\r | |
| 647 | @note MSR_SKYLAKE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r | |
| 648 | **/\r | |
| 2f88bd3a | 649 | #define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639\r |
| 37cea63f | 650 | \r |
| 6b55a245 MK |
651 | /**\r |
| 652 | Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both\r | |
| 653 | platform vendor hardware implementation and BIOS enablement support it. This\r | |
| 654 | MSR will read 0 if not valid.\r | |
| 655 | \r | |
| 656 | @param ECX MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER (0x0000064D)\r | |
| 657 | @param EAX Lower 32-bits of MSR value.\r | |
| 658 | Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.\r | |
| 659 | @param EDX Upper 32-bits of MSR value.\r | |
| 660 | Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.\r | |
| 661 | \r | |
| 662 | <b>Example usage</b>\r | |
| 663 | @code\r | |
| 664 | MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER Msr;\r | |
| 665 | \r | |
| 666 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER);\r | |
| 667 | @endcode\r | |
| 04e7a465 | 668 | @note MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as MSR_PLATFORM_ENERGY_COUNTER in SDM.\r |
| 6b55a245 | 669 | **/\r |
| 2f88bd3a | 670 | #define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D\r |
| 6b55a245 MK |
671 | \r |
| 672 | /**\r | |
| 673 | MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER\r | |
| 674 | **/\r | |
| 675 | typedef union {\r | |
| 676 | ///\r | |
| 677 | /// Individual bit fields\r | |
| 678 | ///\r | |
| 679 | struct {\r | |
| 680 | ///\r | |
| 681 | /// [Bits 31:0] Total energy consumed by all devices in the platform that\r | |
| 682 | /// receive power from integrated power delivery mechanism, Included\r | |
| 683 | /// platform devices are processor cores, SOC, memory, add-on or\r | |
| 684 | /// peripheral devices that get powered directly from the platform power\r | |
| 685 | /// delivery means. The energy units are specified in the\r | |
| 686 | /// MSR_RAPL_POWER_UNIT.Enery_Status_Unit.\r | |
| 687 | ///\r | |
| 2f88bd3a MK |
688 | UINT32 TotalEnergy : 32;\r |
| 689 | UINT32 Reserved : 32;\r | |
| 6b55a245 MK |
690 | } Bits;\r |
| 691 | ///\r | |
| 692 | /// All bit fields as a 32-bit value\r | |
| 693 | ///\r | |
| 2f88bd3a | 694 | UINT32 Uint32;\r |
| 6b55a245 MK |
695 | ///\r |
| 696 | /// All bit fields as a 64-bit value\r | |
| 697 | ///\r | |
| 2f88bd3a | 698 | UINT64 Uint64;\r |
| 6b55a245 MK |
699 | } MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER;\r |
| 700 | \r | |
| 6b55a245 MK |
701 | /**\r |
| 702 | Thread. Productive Performance Count. (R/O). Hardware's view of workload\r | |
| 703 | scalability. See Section 14.4.5.1.\r | |
| 704 | \r | |
| 705 | @param ECX MSR_SKYLAKE_PPERF (0x0000064E)\r | |
| 706 | @param EAX Lower 32-bits of MSR value.\r | |
| 707 | @param EDX Upper 32-bits of MSR value.\r | |
| 708 | \r | |
| 709 | <b>Example usage</b>\r | |
| 710 | @code\r | |
| 711 | UINT64 Msr;\r | |
| 712 | \r | |
| 713 | Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF);\r | |
| 714 | @endcode\r | |
| 04e7a465 | 715 | @note MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM.\r |
| 6b55a245 | 716 | **/\r |
| 2f88bd3a | 717 | #define MSR_SKYLAKE_PPERF 0x0000064E\r |
| 6b55a245 | 718 | \r |
| 37cea63f HW |
719 | /**\r |
| 720 | Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r | |
| 721 | refers to processor core frequency).\r | |
| 722 | \r | |
| 723 | @param ECX MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS (0x0000064F)\r | |
| 724 | @param EAX Lower 32-bits of MSR value.\r | |
| 725 | Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
| 726 | @param EDX Upper 32-bits of MSR value.\r | |
| 727 | Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
| 728 | \r | |
| 729 | <b>Example usage</b>\r | |
| 730 | @code\r | |
| 731 | MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r | |
| 732 | \r | |
| 733 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS);\r | |
| 734 | AsmWriteMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r | |
| 735 | @endcode\r | |
| 736 | @note MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r | |
| 737 | **/\r | |
| 2f88bd3a | 738 | #define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F\r |
| 37cea63f HW |
739 | \r |
| 740 | /**\r | |
| 741 | MSR information returned for MSR index #MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS\r | |
| 742 | **/\r | |
| 743 | typedef union {\r | |
| 744 | ///\r | |
| 745 | /// Individual bit fields\r | |
| 746 | ///\r | |
| 747 | struct {\r | |
| 748 | ///\r | |
| 749 | /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r | |
| 750 | /// operating system request due to assertion of external PROCHOT.\r | |
| 751 | ///\r | |
| 2f88bd3a | 752 | UINT32 PROCHOT_Status : 1;\r |
| 37cea63f HW |
753 | ///\r |
| 754 | /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r | |
| 755 | /// operating system request due to a thermal event.\r | |
| 756 | ///\r | |
| 2f88bd3a MK |
757 | UINT32 ThermalStatus : 1;\r |
| 758 | UINT32 Reserved1 : 2;\r | |
| 37cea63f HW |
759 | ///\r |
| 760 | /// [Bit 4] Residency State Regulation Status (R0) When set, frequency is\r | |
| 761 | /// reduced below the operating system request due to residency state\r | |
| 762 | /// regulation limit.\r | |
| 763 | ///\r | |
| 2f88bd3a | 764 | UINT32 ResidencyStateRegulationStatus : 1;\r |
| 37cea63f HW |
765 | ///\r |
| 766 | /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r | |
| 767 | /// is reduced below the operating system request due to Running Average\r | |
| 768 | /// Thermal Limit (RATL).\r | |
| 769 | ///\r | |
| 2f88bd3a | 770 | UINT32 RunningAverageThermalLimitStatus : 1;\r |
| 37cea63f HW |
771 | ///\r |
| 772 | /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r | |
| 773 | /// below the operating system request due to a thermal alert from a\r | |
| 774 | /// processor Voltage Regulator (VR).\r | |
| 775 | ///\r | |
| 2f88bd3a | 776 | UINT32 VRThermAlertStatus : 1;\r |
| 37cea63f HW |
777 | ///\r |
| 778 | /// [Bit 7] VR Therm Design Current Status (R0) When set, frequency is\r | |
| 779 | /// reduced below the operating system request due to VR thermal design\r | |
| 780 | /// current limit.\r | |
| 781 | ///\r | |
| 2f88bd3a | 782 | UINT32 VRThermDesignCurrentStatus : 1;\r |
| 37cea63f HW |
783 | ///\r |
| 784 | /// [Bit 8] Other Status (R0) When set, frequency is reduced below the\r | |
| 785 | /// operating system request due to electrical or other constraints.\r | |
| 786 | ///\r | |
| 2f88bd3a MK |
787 | UINT32 OtherStatus : 1;\r |
| 788 | UINT32 Reserved2 : 1;\r | |
| 37cea63f HW |
789 | ///\r |
| 790 | /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r | |
| 791 | /// set, frequency is reduced below the operating system request due to\r | |
| 792 | /// package/platform-level power limiting PL1.\r | |
| 793 | ///\r | |
| 2f88bd3a | 794 | UINT32 PL1Status : 1;\r |
| 37cea63f HW |
795 | ///\r |
| 796 | /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r | |
| 797 | /// set, frequency is reduced below the operating system request due to\r | |
| 798 | /// package/platform-level power limiting PL2/PL3.\r | |
| 799 | ///\r | |
| 2f88bd3a | 800 | UINT32 PL2Status : 1;\r |
| 37cea63f HW |
801 | ///\r |
| 802 | /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced\r | |
| 803 | /// below the operating system request due to multi-core turbo limits.\r | |
| 804 | ///\r | |
| 2f88bd3a | 805 | UINT32 MaxTurboLimitStatus : 1;\r |
| 37cea63f HW |
806 | ///\r |
| 807 | /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r | |
| 808 | /// is reduced below the operating system request due to Turbo transition\r | |
| 809 | /// attenuation. This prevents performance degradation due to frequent\r | |
| 810 | /// operating ratio changes.\r | |
| 811 | ///\r | |
| 2f88bd3a MK |
812 | UINT32 TurboTransitionAttenuationStatus : 1;\r |
| 813 | UINT32 Reserved3 : 2;\r | |
| 37cea63f HW |
814 | ///\r |
| 815 | /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r | |
| 816 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 817 | /// remain set until cleared by software writing 0.\r | |
| 818 | ///\r | |
| 2f88bd3a | 819 | UINT32 PROCHOT_Log : 1;\r |
| 37cea63f HW |
820 | ///\r |
| 821 | /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r | |
| 822 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 823 | /// remain set until cleared by software writing 0.\r | |
| 824 | ///\r | |
| 2f88bd3a MK |
825 | UINT32 ThermalLog : 1;\r |
| 826 | UINT32 Reserved4 : 2;\r | |
| 37cea63f HW |
827 | ///\r |
| 828 | /// [Bit 20] Residency State Regulation Log When set, indicates that the\r | |
| 829 | /// Residency State Regulation Status bit has asserted since the log bit\r | |
| 830 | /// was last cleared. This log bit will remain set until cleared by\r | |
| 831 | /// software writing 0.\r | |
| 832 | ///\r | |
| 2f88bd3a | 833 | UINT32 ResidencyStateRegulationLog : 1;\r |
| 37cea63f HW |
834 | ///\r |
| 835 | /// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r | |
| 836 | /// the RATL Status bit has asserted since the log bit was last cleared.\r | |
| 837 | /// This log bit will remain set until cleared by software writing 0.\r | |
| 838 | ///\r | |
| 2f88bd3a | 839 | UINT32 RunningAverageThermalLimitLog : 1;\r |
| 37cea63f HW |
840 | ///\r |
| 841 | /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r | |
| 842 | /// Alert Status bit has asserted since the log bit was last cleared. This\r | |
| 843 | /// log bit will remain set until cleared by software writing 0.\r | |
| 844 | ///\r | |
| 2f88bd3a | 845 | UINT32 VRThermAlertLog : 1;\r |
| 37cea63f HW |
846 | ///\r |
| 847 | /// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r | |
| 848 | /// VR TDC Status bit has asserted since the log bit was last cleared.\r | |
| 849 | /// This log bit will remain set until cleared by software writing 0.\r | |
| 850 | ///\r | |
| 2f88bd3a | 851 | UINT32 VRThermalDesignCurrentLog : 1;\r |
| 37cea63f HW |
852 | ///\r |
| 853 | /// [Bit 24] Other Log When set, indicates that the Other Status bit has\r | |
| 854 | /// asserted since the log bit was last cleared. This log bit will remain\r | |
| 855 | /// set until cleared by software writing 0.\r | |
| 856 | ///\r | |
| 2f88bd3a MK |
857 | UINT32 OtherLog : 1;\r |
| 858 | UINT32 Reserved5 : 1;\r | |
| 37cea63f HW |
859 | ///\r |
| 860 | /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r | |
| 861 | /// indicates that the Package or Platform Level PL1 Power Limiting Status\r | |
| 862 | /// bit has asserted since the log bit was last cleared. This log bit will\r | |
| 863 | /// remain set until cleared by software writing 0.\r | |
| 864 | ///\r | |
| 2f88bd3a | 865 | UINT32 PL1Log : 1;\r |
| 37cea63f HW |
866 | ///\r |
| 867 | /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r | |
| 868 | /// indicates that the Package or Platform Level PL2/PL3 Power Limiting\r | |
| 869 | /// Status bit has asserted since the log bit was last cleared. This log\r | |
| 870 | /// bit will remain set until cleared by software writing 0.\r | |
| 871 | ///\r | |
| 2f88bd3a | 872 | UINT32 PL2Log : 1;\r |
| 37cea63f HW |
873 | ///\r |
| 874 | /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r | |
| 875 | /// Limit Status bit has asserted since the log bit was last cleared. This\r | |
| 876 | /// log bit will remain set until cleared by software writing 0.\r | |
| 877 | ///\r | |
| 2f88bd3a | 878 | UINT32 MaxTurboLimitLog : 1;\r |
| 37cea63f HW |
879 | ///\r |
| 880 | /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r | |
| 881 | /// Turbo Transition Attenuation Status bit has asserted since the log bit\r | |
| 882 | /// was last cleared. This log bit will remain set until cleared by\r | |
| 883 | /// software writing 0.\r | |
| 884 | ///\r | |
| 2f88bd3a MK |
885 | UINT32 TurboTransitionAttenuationLog : 1;\r |
| 886 | UINT32 Reserved6 : 2;\r | |
| 887 | UINT32 Reserved7 : 32;\r | |
| 37cea63f HW |
888 | } Bits;\r |
| 889 | ///\r | |
| 890 | /// All bit fields as a 32-bit value\r | |
| 891 | ///\r | |
| 2f88bd3a | 892 | UINT32 Uint32;\r |
| 37cea63f HW |
893 | ///\r |
| 894 | /// All bit fields as a 64-bit value\r | |
| 895 | ///\r | |
| 2f88bd3a | 896 | UINT64 Uint64;\r |
| 37cea63f HW |
897 | } MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER;\r |
| 898 | \r | |
| 6b55a245 MK |
899 | /**\r |
| 900 | Package. HDC Configuration (R/W)..\r | |
| 901 | \r | |
| 902 | @param ECX MSR_SKYLAKE_PKG_HDC_CONFIG (0x00000652)\r | |
| 903 | @param EAX Lower 32-bits of MSR value.\r | |
| 904 | Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.\r | |
| 905 | @param EDX Upper 32-bits of MSR value.\r | |
| 906 | Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.\r | |
| 907 | \r | |
| 908 | <b>Example usage</b>\r | |
| 909 | @code\r | |
| 910 | MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER Msr;\r | |
| 911 | \r | |
| 912 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG);\r | |
| 913 | AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64);\r | |
| 914 | @endcode\r | |
| 04e7a465 | 915 | @note MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM.\r |
| 6b55a245 | 916 | **/\r |
| 2f88bd3a | 917 | #define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652\r |
| 6b55a245 MK |
918 | \r |
| 919 | /**\r | |
| 920 | MSR information returned for MSR index #MSR_SKYLAKE_PKG_HDC_CONFIG\r | |
| 921 | **/\r | |
| 922 | typedef union {\r | |
| 923 | ///\r | |
| 924 | /// Individual bit fields\r | |
| 925 | ///\r | |
| 926 | struct {\r | |
| 927 | ///\r | |
| 928 | /// [Bits 2:0] PKG_Cx_Monitor. Configures Package Cx state threshold for\r | |
| 929 | /// MSR_PKG_HDC_DEEP_RESIDENCY.\r | |
| 930 | ///\r | |
| 2f88bd3a MK |
931 | UINT32 PKG_Cx_Monitor : 3;\r |
| 932 | UINT32 Reserved1 : 29;\r | |
| 933 | UINT32 Reserved2 : 32;\r | |
| 6b55a245 MK |
934 | } Bits;\r |
| 935 | ///\r | |
| 936 | /// All bit fields as a 32-bit value\r | |
| 937 | ///\r | |
| 2f88bd3a | 938 | UINT32 Uint32;\r |
| 6b55a245 MK |
939 | ///\r |
| 940 | /// All bit fields as a 64-bit value\r | |
| 941 | ///\r | |
| 2f88bd3a | 942 | UINT64 Uint64;\r |
| 6b55a245 MK |
943 | } MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER;\r |
| 944 | \r | |
| 6b55a245 MK |
945 | /**\r |
| 946 | Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt.\r | |
| 947 | \r | |
| 948 | @param ECX MSR_SKYLAKE_CORE_HDC_RESIDENCY (0x00000653)\r | |
| 949 | @param EAX Lower 32-bits of MSR value.\r | |
| 950 | @param EDX Upper 32-bits of MSR value.\r | |
| 951 | \r | |
| 952 | <b>Example usage</b>\r | |
| 953 | @code\r | |
| 954 | UINT64 Msr;\r | |
| 955 | \r | |
| 956 | Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY);\r | |
| 957 | @endcode\r | |
| 04e7a465 | 958 | @note MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in SDM.\r |
| 6b55a245 | 959 | **/\r |
| 2f88bd3a | 960 | #define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653\r |
| 6b55a245 MK |
961 | \r |
| 962 | /**\r | |
| 963 | Package. Accumulate the cycles the package was in C2 state and at least one\r | |
| 964 | logical processor was in forced idle. (R/O). Pkg_C2_Duty_Cycle_Cnt.\r | |
| 965 | \r | |
| 966 | @param ECX MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY (0x00000655)\r | |
| 967 | @param EAX Lower 32-bits of MSR value.\r | |
| 968 | @param EDX Upper 32-bits of MSR value.\r | |
| 969 | \r | |
| 970 | <b>Example usage</b>\r | |
| 971 | @code\r | |
| 972 | UINT64 Msr;\r | |
| 973 | \r | |
| 974 | Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY);\r | |
| 975 | @endcode\r | |
| 04e7a465 | 976 | @note MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM.\r |
| 6b55a245 | 977 | **/\r |
| 2f88bd3a | 978 | #define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655\r |
| 6b55a245 MK |
979 | \r |
| 980 | /**\r | |
| 981 | Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt.\r | |
| 982 | \r | |
| 983 | @param ECX MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY (0x00000656)\r | |
| 984 | @param EAX Lower 32-bits of MSR value.\r | |
| 985 | @param EDX Upper 32-bits of MSR value.\r | |
| 986 | \r | |
| 987 | <b>Example usage</b>\r | |
| 988 | @code\r | |
| 989 | UINT64 Msr;\r | |
| 990 | \r | |
| 991 | Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY);\r | |
| 992 | @endcode\r | |
| 04e7a465 | 993 | @note MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as MSR_PKG_HDC_DEEP_RESIDENCY in SDM.\r |
| 6b55a245 | 994 | **/\r |
| 2f88bd3a | 995 | #define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656\r |
| 6b55a245 MK |
996 | \r |
| 997 | /**\r | |
| 998 | Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate\r | |
| 999 | as the TSC. The increment each cycle is weighted by the number of processor\r | |
| 1000 | cores in the package that reside in C0. If N cores are simultaneously in C0,\r | |
| 1001 | then each cycle the counter increments by N.\r | |
| 1002 | \r | |
| 1003 | @param ECX MSR_SKYLAKE_WEIGHTED_CORE_C0 (0x00000658)\r | |
| 1004 | @param EAX Lower 32-bits of MSR value.\r | |
| 1005 | @param EDX Upper 32-bits of MSR value.\r | |
| 1006 | \r | |
| 1007 | <b>Example usage</b>\r | |
| 1008 | @code\r | |
| 1009 | UINT64 Msr;\r | |
| 1010 | \r | |
| 1011 | Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0);\r | |
| 1012 | @endcode\r | |
| 04e7a465 | 1013 | @note MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM.\r |
| 6b55a245 | 1014 | **/\r |
| 2f88bd3a | 1015 | #define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658\r |
| 6b55a245 MK |
1016 | \r |
| 1017 | /**\r | |
| 1018 | Package. Any Core C0 Residency. (R/O). Increment at the same rate as the\r | |
| 1019 | TSC. The increment each cycle is one if any processor core in the package is\r | |
| 1020 | in C0.\r | |
| 1021 | \r | |
| 1022 | @param ECX MSR_SKYLAKE_ANY_CORE_C0 (0x00000659)\r | |
| 1023 | @param EAX Lower 32-bits of MSR value.\r | |
| 1024 | @param EDX Upper 32-bits of MSR value.\r | |
| 1025 | \r | |
| 1026 | <b>Example usage</b>\r | |
| 1027 | @code\r | |
| 1028 | UINT64 Msr;\r | |
| 1029 | \r | |
| 1030 | Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0);\r | |
| 1031 | @endcode\r | |
| 04e7a465 | 1032 | @note MSR_SKYLAKE_ANY_CORE_C0 is defined as MSR_ANY_CORE_C0 in SDM.\r |
| 6b55a245 | 1033 | **/\r |
| 2f88bd3a | 1034 | #define MSR_SKYLAKE_ANY_CORE_C0 0x00000659\r |
| 6b55a245 MK |
1035 | \r |
| 1036 | /**\r | |
| 1037 | Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate\r | |
| 1038 | as the TSC. The increment each cycle is one if any processor graphic\r | |
| 1039 | device's compute engines are in C0.\r | |
| 1040 | \r | |
| 1041 | @param ECX MSR_SKYLAKE_ANY_GFXE_C0 (0x0000065A)\r | |
| 1042 | @param EAX Lower 32-bits of MSR value.\r | |
| 1043 | @param EDX Upper 32-bits of MSR value.\r | |
| 1044 | \r | |
| 1045 | <b>Example usage</b>\r | |
| 1046 | @code\r | |
| 1047 | UINT64 Msr;\r | |
| 1048 | \r | |
| 1049 | Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_GFXE_C0);\r | |
| 1050 | @endcode\r | |
| 04e7a465 | 1051 | @note MSR_SKYLAKE_ANY_GFXE_C0 is defined as MSR_ANY_GFXE_C0 in SDM.\r |
| 6b55a245 | 1052 | **/\r |
| 2f88bd3a | 1053 | #define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A\r |
| 6b55a245 MK |
1054 | \r |
| 1055 | /**\r | |
| 1056 | Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment\r | |
| 1057 | at the same rate as the TSC. The increment each cycle is one if at least one\r | |
| 1058 | compute engine of the processor graphics is in C0 and at least one processor\r | |
| 1059 | core in the package is also in C0.\r | |
| 1060 | \r | |
| 1061 | @param ECX MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 (0x0000065B)\r | |
| 1062 | @param EAX Lower 32-bits of MSR value.\r | |
| 1063 | @param EDX Upper 32-bits of MSR value.\r | |
| 1064 | \r | |
| 1065 | <b>Example usage</b>\r | |
| 1066 | @code\r | |
| 1067 | UINT64 Msr;\r | |
| 1068 | \r | |
| 1069 | Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0);\r | |
| 1070 | @endcode\r | |
| 04e7a465 | 1071 | @note MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 is defined as MSR_CORE_GFXE_OVERLAP_C0 in SDM.\r |
| 6b55a245 | 1072 | **/\r |
| 2f88bd3a | 1073 | #define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B\r |
| 6b55a245 MK |
1074 | \r |
| 1075 | /**\r | |
| 1076 | Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to\r | |
| 1077 | limit power consumption of the platform devices to the specified values. The\r | |
| 1078 | Long Duration power consumption is specified via Platform_Power_Limit_1 and\r | |
| 1079 | Platform_Power_Limit_1_Time. The Short Duration power consumption limit is\r | |
| 1080 | specified via the Platform_Power_Limit_2 with duration chosen by the\r | |
| 1081 | processor. The processor implements an exponential-weighted algorithm in the\r | |
| 1082 | placement of the time windows.\r | |
| 1083 | \r | |
| 1084 | @param ECX MSR_SKYLAKE_PLATFORM_POWER_LIMIT (0x0000065C)\r | |
| 1085 | @param EAX Lower 32-bits of MSR value.\r | |
| 1086 | Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.\r | |
| 1087 | @param EDX Upper 32-bits of MSR value.\r | |
| 1088 | Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.\r | |
| 1089 | \r | |
| 1090 | <b>Example usage</b>\r | |
| 1091 | @code\r | |
| 1092 | MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER Msr;\r | |
| 1093 | \r | |
| 1094 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT);\r | |
| 1095 | AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT, Msr.Uint64);\r | |
| 1096 | @endcode\r | |
| 04e7a465 | 1097 | @note MSR_SKYLAKE_PLATFORM_POWER_LIMIT is defined as MSR_PLATFORM_POWER_LIMIT in SDM.\r |
| 6b55a245 | 1098 | **/\r |
| 2f88bd3a | 1099 | #define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C\r |
| 6b55a245 MK |
1100 | \r |
| 1101 | /**\r | |
| 1102 | MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_POWER_LIMIT\r | |
| 1103 | **/\r | |
| 1104 | typedef union {\r | |
| 1105 | ///\r | |
| 1106 | /// Individual bit fields\r | |
| 1107 | ///\r | |
| 1108 | struct {\r | |
| 1109 | ///\r | |
| 1110 | /// [Bits 14:0] Platform Power Limit #1. Average Power limit value which\r | |
| 1111 | /// the platform must not exceed over a time window as specified by\r | |
| 1112 | /// Power_Limit_1_TIME field. The default value is the Thermal Design\r | |
| 1113 | /// Power (TDP) and varies with product skus. The unit is specified in\r | |
| 1114 | /// MSR_RAPLPOWER_UNIT.\r | |
| 1115 | ///\r | |
| 2f88bd3a | 1116 | UINT32 PlatformPowerLimit1 : 15;\r |
| 6b55a245 MK |
1117 | ///\r |
| 1118 | /// [Bit 15] Enable Platform Power Limit #1. When set, enables the\r | |
| 1119 | /// processor to apply control policy such that the platform power does\r | |
| 1120 | /// not exceed Platform Power limit #1 over the time window specified by\r | |
| 1121 | /// Power Limit #1 Time Window.\r | |
| 1122 | ///\r | |
| 2f88bd3a | 1123 | UINT32 EnablePlatformPowerLimit1 : 1;\r |
| 6b55a245 MK |
1124 | ///\r |
| 1125 | /// [Bit 16] Platform Clamping Limitation #1. When set, allows the\r | |
| 1126 | /// processor to go below the OS requested P states in order to maintain\r | |
| 1127 | /// the power below specified Platform Power Limit #1 value. This bit is\r | |
| 1128 | /// writeable only when CPUID (EAX=6):EAX[4] is set.\r | |
| 1129 | ///\r | |
| 2f88bd3a | 1130 | UINT32 PlatformClampingLimitation1 : 1;\r |
| 6b55a245 MK |
1131 | ///\r |
| 1132 | /// [Bits 23:17] Time Window for Platform Power Limit #1. Specifies the\r | |
| 1133 | /// duration of the time window over which Platform Power Limit 1 value\r | |
| 1134 | /// should be maintained for sustained long duration. This field is made\r | |
| 1135 | /// up of two numbers from the following equation: Time Window = (float)\r | |
| 1136 | /// ((1+(X/4))*(2^Y)), where: X. = POWER_LIMIT_1_TIME[23:22] Y. =\r | |
| 1137 | /// POWER_LIMIT_1_TIME[21:17]. The maximum allowed value in this field is\r | |
| 1138 | /// defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH,\r | |
| 1139 | /// The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit].\r | |
| 1140 | ///\r | |
| 2f88bd3a MK |
1141 | UINT32 Time : 7;\r |
| 1142 | UINT32 Reserved1 : 8;\r | |
| 6b55a245 MK |
1143 | ///\r |
| 1144 | /// [Bits 46:32] Platform Power Limit #2. Average Power limit value which\r | |
| 1145 | /// the platform must not exceed over the Short Duration time window\r | |
| 1146 | /// chosen by the processor. The recommended default value is 1.25 times\r | |
| 1147 | /// the Long Duration Power Limit (i.e. Platform Power Limit # 1).\r | |
| 1148 | ///\r | |
| 2f88bd3a | 1149 | UINT32 PlatformPowerLimit2 : 15;\r |
| 6b55a245 MK |
1150 | ///\r |
| 1151 | /// [Bit 47] Enable Platform Power Limit #2. When set, enables the\r | |
| 1152 | /// processor to apply control policy such that the platform power does\r | |
| 1153 | /// not exceed Platform Power limit #2 over the Short Duration time window.\r | |
| 1154 | ///\r | |
| 2f88bd3a | 1155 | UINT32 EnablePlatformPowerLimit2 : 1;\r |
| 6b55a245 MK |
1156 | ///\r |
| 1157 | /// [Bit 48] Platform Clamping Limitation #2. When set, allows the\r | |
| 1158 | /// processor to go below the OS requested P states in order to maintain\r | |
| 1159 | /// the power below specified Platform Power Limit #2 value.\r | |
| 1160 | ///\r | |
| 2f88bd3a MK |
1161 | UINT32 PlatformClampingLimitation2 : 1;\r |
| 1162 | UINT32 Reserved2 : 14;\r | |
| 6b55a245 MK |
1163 | ///\r |
| 1164 | /// [Bit 63] Lock. Setting this bit will lock all other bits of this MSR\r | |
| 1165 | /// until system RESET.\r | |
| 1166 | ///\r | |
| 2f88bd3a | 1167 | UINT32 Lock : 1;\r |
| 6b55a245 MK |
1168 | } Bits;\r |
| 1169 | ///\r | |
| 1170 | /// All bit fields as a 64-bit value\r | |
| 1171 | ///\r | |
| 2f88bd3a | 1172 | UINT64 Uint64;\r |
| 6b55a245 MK |
1173 | } MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER;\r |
| 1174 | \r | |
| 6b55a245 MK |
1175 | /**\r |
| 1176 | Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last\r | |
| 1177 | branch record registers on the last branch record stack. This part of the\r | |
| 1178 | stack contains pointers to the source instruction. See also: - Last Branch\r | |
| 37cea63f | 1179 | Record Stack TOS at 1C9H - Section 17.10.\r |
| 6b55a245 MK |
1180 | \r |
| 1181 | @param ECX MSR_SKYLAKE_LASTBRANCH_n_FROM_IP\r | |
| 1182 | @param EAX Lower 32-bits of MSR value.\r | |
| 1183 | @param EDX Upper 32-bits of MSR value.\r | |
| 1184 | \r | |
| 1185 | <b>Example usage</b>\r | |
| 1186 | @code\r | |
| 1187 | UINT64 Msr;\r | |
| 1188 | \r | |
| 1189 | Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP);\r | |
| 1190 | AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP, Msr);\r | |
| 1191 | @endcode\r | |
| 04e7a465 JF |
1192 | @note MSR_SKYLAKE_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.\r |
| 1193 | MSR_SKYLAKE_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.\r | |
| 1194 | MSR_SKYLAKE_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.\r | |
| 1195 | MSR_SKYLAKE_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.\r | |
| 1196 | MSR_SKYLAKE_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.\r | |
| 1197 | MSR_SKYLAKE_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.\r | |
| 1198 | MSR_SKYLAKE_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.\r | |
| 1199 | MSR_SKYLAKE_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.\r | |
| 1200 | MSR_SKYLAKE_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.\r | |
| 1201 | MSR_SKYLAKE_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.\r | |
| 1202 | MSR_SKYLAKE_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.\r | |
| 1203 | MSR_SKYLAKE_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.\r | |
| 1204 | MSR_SKYLAKE_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.\r | |
| 1205 | MSR_SKYLAKE_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.\r | |
| 1206 | MSR_SKYLAKE_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.\r | |
| 1207 | MSR_SKYLAKE_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.\r | |
| 6b55a245 MK |
1208 | @{\r |
| 1209 | **/\r | |
| 2f88bd3a MK |
1210 | #define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690\r |
| 1211 | #define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691\r | |
| 1212 | #define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692\r | |
| 1213 | #define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693\r | |
| 1214 | #define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694\r | |
| 1215 | #define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695\r | |
| 1216 | #define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696\r | |
| 1217 | #define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697\r | |
| 1218 | #define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698\r | |
| 1219 | #define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699\r | |
| 1220 | #define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A\r | |
| 1221 | #define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B\r | |
| 1222 | #define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C\r | |
| 1223 | #define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D\r | |
| 1224 | #define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E\r | |
| 1225 | #define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F\r | |
| 6b55a245 MK |
1226 | /// @}\r |
| 1227 | \r | |
| 37cea63f HW |
1228 | /**\r |
| 1229 | Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)\r | |
| 1230 | (frequency refers to processor graphics frequency).\r | |
| 1231 | \r | |
| 1232 | @param ECX MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)\r | |
| 1233 | @param EAX Lower 32-bits of MSR value.\r | |
| 1234 | Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r | |
| 1235 | @param EDX Upper 32-bits of MSR value.\r | |
| 1236 | Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r | |
| 1237 | \r | |
| 1238 | <b>Example usage</b>\r | |
| 1239 | @code\r | |
| 1240 | MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr;\r | |
| 1241 | \r | |
| 1242 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS);\r | |
| 1243 | AsmWriteMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);\r | |
| 1244 | @endcode\r | |
| 1245 | @note MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.\r | |
| 1246 | **/\r | |
| 1247 | #define MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0\r | |
| 1248 | \r | |
| 1249 | /**\r | |
| 1250 | MSR information returned for MSR index\r | |
| 1251 | #MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS\r | |
| 1252 | **/\r | |
| 1253 | typedef union {\r | |
| 1254 | ///\r | |
| 1255 | /// Individual bit fields\r | |
| 1256 | ///\r | |
| 1257 | struct {\r | |
| 1258 | ///\r | |
| 1259 | /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to\r | |
| 1260 | /// assertion of external PROCHOT.\r | |
| 1261 | ///\r | |
| 2f88bd3a | 1262 | UINT32 PROCHOT_Status : 1;\r |
| 37cea63f HW |
1263 | ///\r |
| 1264 | /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a\r | |
| 1265 | /// thermal event.\r | |
| 1266 | ///\r | |
| 2f88bd3a MK |
1267 | UINT32 ThermalStatus : 1;\r |
| 1268 | UINT32 Reserved1 : 3;\r | |
| 37cea63f HW |
1269 | ///\r |
| 1270 | /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r | |
| 1271 | /// is reduced due to running average thermal limit.\r | |
| 1272 | ///\r | |
| 2f88bd3a | 1273 | UINT32 RunningAverageThermalLimitStatus : 1;\r |
| 37cea63f HW |
1274 | ///\r |
| 1275 | /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due\r | |
| 1276 | /// to a thermal alert from a processor Voltage Regulator.\r | |
| 1277 | ///\r | |
| 2f88bd3a | 1278 | UINT32 VRThermAlertStatus : 1;\r |
| 37cea63f HW |
1279 | ///\r |
| 1280 | /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is\r | |
| 1281 | /// reduced due to VR TDC limit.\r | |
| 1282 | ///\r | |
| 2f88bd3a | 1283 | UINT32 VRThermalDesignCurrentStatus : 1;\r |
| 37cea63f HW |
1284 | ///\r |
| 1285 | /// [Bit 8] Other Status (R0) When set, frequency is reduced due to\r | |
| 1286 | /// electrical or other constraints.\r | |
| 1287 | ///\r | |
| 2f88bd3a MK |
1288 | UINT32 OtherStatus : 1;\r |
| 1289 | UINT32 Reserved2 : 1;\r | |
| 37cea63f HW |
1290 | ///\r |
| 1291 | /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r | |
| 1292 | /// set, frequency is reduced due to package/platform-level power limiting\r | |
| 1293 | /// PL1.\r | |
| 1294 | ///\r | |
| 2f88bd3a | 1295 | UINT32 PL1Status : 1;\r |
| 37cea63f HW |
1296 | ///\r |
| 1297 | /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r | |
| 1298 | /// set, frequency is reduced due to package/platform-level power limiting\r | |
| 1299 | /// PL2/PL3.\r | |
| 1300 | ///\r | |
| 2f88bd3a | 1301 | UINT32 PL2Status : 1;\r |
| 37cea63f HW |
1302 | ///\r |
| 1303 | /// [Bit 12] Inefficient Operation Status (R0) When set, processor\r | |
| 1304 | /// graphics frequency is operating below target frequency.\r | |
| 1305 | ///\r | |
| 2f88bd3a MK |
1306 | UINT32 InefficientOperationStatus : 1;\r |
| 1307 | UINT32 Reserved3 : 3;\r | |
| 37cea63f HW |
1308 | ///\r |
| 1309 | /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r | |
| 1310 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 1311 | /// remain set until cleared by software writing 0.\r | |
| 1312 | ///\r | |
| 2f88bd3a | 1313 | UINT32 PROCHOT_Log : 1;\r |
| 37cea63f HW |
1314 | ///\r |
| 1315 | /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r | |
| 1316 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 1317 | /// remain set until cleared by software writing 0.\r | |
| 1318 | ///\r | |
| 2f88bd3a MK |
1319 | UINT32 ThermalLog : 1;\r |
| 1320 | UINT32 Reserved4 : 3;\r | |
| 37cea63f HW |
1321 | ///\r |
| 1322 | /// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r | |
| 1323 | /// the RATL Status bit has asserted since the log bit was last cleared.\r | |
| 1324 | /// This log bit will remain set until cleared by software writing 0.\r | |
| 1325 | ///\r | |
| 2f88bd3a | 1326 | UINT32 RunningAverageThermalLimitLog : 1;\r |
| 37cea63f HW |
1327 | ///\r |
| 1328 | /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r | |
| 1329 | /// Alert Status bit has asserted since the log bit was last cleared. This\r | |
| 1330 | /// log bit will remain set until cleared by software writing 0.\r | |
| 1331 | ///\r | |
| 2f88bd3a | 1332 | UINT32 VRThermAlertLog : 1;\r |
| 37cea63f HW |
1333 | ///\r |
| 1334 | /// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r | |
| 1335 | /// VR Therm Alert Status bit has asserted since the log bit was last\r | |
| 1336 | /// cleared. This log bit will remain set until cleared by software\r | |
| 1337 | /// writing 0.\r | |
| 1338 | ///\r | |
| 2f88bd3a | 1339 | UINT32 VRThermalDesignCurrentLog : 1;\r |
| 37cea63f HW |
1340 | ///\r |
| 1341 | /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has\r | |
| 1342 | /// asserted since the log bit was last cleared. This log bit will remain\r | |
| 1343 | /// set until cleared by software writing 0.\r | |
| 1344 | ///\r | |
| 2f88bd3a MK |
1345 | UINT32 OtherLog : 1;\r |
| 1346 | UINT32 Reserved5 : 1;\r | |
| 37cea63f HW |
1347 | ///\r |
| 1348 | /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r | |
| 1349 | /// indicates that the Package/Platform Level PL1 Power Limiting Status\r | |
| 1350 | /// bit has asserted since the log bit was last cleared. This log bit will\r | |
| 1351 | /// remain set until cleared by software writing 0.\r | |
| 1352 | ///\r | |
| 2f88bd3a | 1353 | UINT32 PL1Log : 1;\r |
| 37cea63f HW |
1354 | ///\r |
| 1355 | /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r | |
| 1356 | /// indicates that the Package/Platform Level PL2 Power Limiting Status\r | |
| 1357 | /// bit has asserted since the log bit was last cleared. This log bit will\r | |
| 1358 | /// remain set until cleared by software writing 0.\r | |
| 1359 | ///\r | |
| 2f88bd3a | 1360 | UINT32 PL2Log : 1;\r |
| 37cea63f HW |
1361 | ///\r |
| 1362 | /// [Bit 28] Inefficient Operation Log When set, indicates that the\r | |
| 1363 | /// Inefficient Operation Status bit has asserted since the log bit was\r | |
| 1364 | /// last cleared. This log bit will remain set until cleared by software\r | |
| 1365 | /// writing 0.\r | |
| 1366 | ///\r | |
| 2f88bd3a MK |
1367 | UINT32 InefficientOperationLog : 1;\r |
| 1368 | UINT32 Reserved6 : 3;\r | |
| 1369 | UINT32 Reserved7 : 32;\r | |
| 37cea63f HW |
1370 | } Bits;\r |
| 1371 | ///\r | |
| 1372 | /// All bit fields as a 32-bit value\r | |
| 1373 | ///\r | |
| 2f88bd3a | 1374 | UINT32 Uint32;\r |
| 37cea63f HW |
1375 | ///\r |
| 1376 | /// All bit fields as a 64-bit value\r | |
| 1377 | ///\r | |
| 2f88bd3a | 1378 | UINT64 Uint64;\r |
| 37cea63f HW |
1379 | } MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;\r |
| 1380 | \r | |
| 37cea63f HW |
1381 | /**\r |
| 1382 | Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)\r | |
| 1383 | (frequency refers to ring interconnect in the uncore).\r | |
| 1384 | \r | |
| 1385 | @param ECX MSR_SKYLAKE_RING_PERF_LIMIT_REASONS (0x000006B1)\r | |
| 1386 | @param EAX Lower 32-bits of MSR value.\r | |
| 1387 | Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.\r | |
| 1388 | @param EDX Upper 32-bits of MSR value.\r | |
| 1389 | Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.\r | |
| 1390 | \r | |
| 1391 | <b>Example usage</b>\r | |
| 1392 | @code\r | |
| 1393 | MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER Msr;\r | |
| 1394 | \r | |
| 1395 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS);\r | |
| 1396 | AsmWriteMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS, Msr.Uint64);\r | |
| 1397 | @endcode\r | |
| 1398 | @note MSR_SKYLAKE_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.\r | |
| 1399 | **/\r | |
| 2f88bd3a | 1400 | #define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1\r |
| 37cea63f HW |
1401 | \r |
| 1402 | /**\r | |
| 1403 | MSR information returned for MSR index #MSR_SKYLAKE_RING_PERF_LIMIT_REASONS\r | |
| 1404 | **/\r | |
| 1405 | typedef union {\r | |
| 1406 | ///\r | |
| 1407 | /// Individual bit fields\r | |
| 1408 | ///\r | |
| 1409 | struct {\r | |
| 1410 | ///\r | |
| 1411 | /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to\r | |
| 1412 | /// assertion of external PROCHOT.\r | |
| 1413 | ///\r | |
| 2f88bd3a | 1414 | UINT32 PROCHOT_Status : 1;\r |
| 37cea63f HW |
1415 | ///\r |
| 1416 | /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a\r | |
| 1417 | /// thermal event.\r | |
| 1418 | ///\r | |
| 2f88bd3a MK |
1419 | UINT32 ThermalStatus : 1;\r |
| 1420 | UINT32 Reserved1 : 3;\r | |
| 37cea63f HW |
1421 | ///\r |
| 1422 | /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r | |
| 1423 | /// is reduced due to running average thermal limit.\r | |
| 1424 | ///\r | |
| 2f88bd3a | 1425 | UINT32 RunningAverageThermalLimitStatus : 1;\r |
| 37cea63f HW |
1426 | ///\r |
| 1427 | /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due\r | |
| 1428 | /// to a thermal alert from a processor Voltage Regulator.\r | |
| 1429 | ///\r | |
| 2f88bd3a | 1430 | UINT32 VRThermAlertStatus : 1;\r |
| 37cea63f HW |
1431 | ///\r |
| 1432 | /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is\r | |
| 1433 | /// reduced due to VR TDC limit.\r | |
| 1434 | ///\r | |
| 2f88bd3a | 1435 | UINT32 VRThermalDesignCurrentStatus : 1;\r |
| 37cea63f HW |
1436 | ///\r |
| 1437 | /// [Bit 8] Other Status (R0) When set, frequency is reduced due to\r | |
| 1438 | /// electrical or other constraints.\r | |
| 1439 | ///\r | |
| 2f88bd3a MK |
1440 | UINT32 OtherStatus : 1;\r |
| 1441 | UINT32 Reserved2 : 1;\r | |
| 37cea63f HW |
1442 | ///\r |
| 1443 | /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r | |
| 1444 | /// set, frequency is reduced due to package/Platform-level power limiting\r | |
| 1445 | /// PL1.\r | |
| 1446 | ///\r | |
| 2f88bd3a | 1447 | UINT32 PL1Status : 1;\r |
| 37cea63f HW |
1448 | ///\r |
| 1449 | /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r | |
| 1450 | /// set, frequency is reduced due to package/Platform-level power limiting\r | |
| 1451 | /// PL2/PL3.\r | |
| 1452 | ///\r | |
| 2f88bd3a MK |
1453 | UINT32 PL2Status : 1;\r |
| 1454 | UINT32 Reserved3 : 4;\r | |
| 37cea63f HW |
1455 | ///\r |
| 1456 | /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r | |
| 1457 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 1458 | /// remain set until cleared by software writing 0.\r | |
| 1459 | ///\r | |
| 2f88bd3a | 1460 | UINT32 PROCHOT_Log : 1;\r |
| 37cea63f HW |
1461 | ///\r |
| 1462 | /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r | |
| 1463 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 1464 | /// remain set until cleared by software writing 0.\r | |
| 1465 | ///\r | |
| 2f88bd3a MK |
1466 | UINT32 ThermalLog : 1;\r |
| 1467 | UINT32 Reserved4 : 3;\r | |
| 37cea63f HW |
1468 | ///\r |
| 1469 | /// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r | |
| 1470 | /// the RATL Status bit has asserted since the log bit was last cleared.\r | |
| 1471 | /// This log bit will remain set until cleared by software writing 0.\r | |
| 1472 | ///\r | |
| 2f88bd3a | 1473 | UINT32 RunningAverageThermalLimitLog : 1;\r |
| 37cea63f HW |
1474 | ///\r |
| 1475 | /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r | |
| 1476 | /// Alert Status bit has asserted since the log bit was last cleared. This\r | |
| 1477 | /// log bit will remain set until cleared by software writing 0.\r | |
| 1478 | ///\r | |
| 2f88bd3a | 1479 | UINT32 VRThermAlertLog : 1;\r |
| 37cea63f HW |
1480 | ///\r |
| 1481 | /// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r | |
| 1482 | /// VR Therm Alert Status bit has asserted since the log bit was last\r | |
| 1483 | /// cleared. This log bit will remain set until cleared by software\r | |
| 1484 | /// writing 0.\r | |
| 1485 | ///\r | |
| 2f88bd3a | 1486 | UINT32 VRThermalDesignCurrentLog : 1;\r |
| 37cea63f HW |
1487 | ///\r |
| 1488 | /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has\r | |
| 1489 | /// asserted since the log bit was last cleared. This log bit will remain\r | |
| 1490 | /// set until cleared by software writing 0.\r | |
| 1491 | ///\r | |
| 2f88bd3a MK |
1492 | UINT32 OtherLog : 1;\r |
| 1493 | UINT32 Reserved5 : 1;\r | |
| 37cea63f HW |
1494 | ///\r |
| 1495 | /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r | |
| 1496 | /// indicates that the Package/Platform Level PL1 Power Limiting Status\r | |
| 1497 | /// bit has asserted since the log bit was last cleared. This log bit will\r | |
| 1498 | /// remain set until cleared by software writing 0.\r | |
| 1499 | ///\r | |
| 2f88bd3a | 1500 | UINT32 PL1Log : 1;\r |
| 37cea63f HW |
1501 | ///\r |
| 1502 | /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r | |
| 1503 | /// indicates that the Package/Platform Level PL2 Power Limiting Status\r | |
| 1504 | /// bit has asserted since the log bit was last cleared. This log bit will\r | |
| 1505 | /// remain set until cleared by software writing 0.\r | |
| 1506 | ///\r | |
| 2f88bd3a MK |
1507 | UINT32 PL2Log : 1;\r |
| 1508 | UINT32 Reserved6 : 4;\r | |
| 1509 | UINT32 Reserved7 : 32;\r | |
| 37cea63f HW |
1510 | } Bits;\r |
| 1511 | ///\r | |
| 1512 | /// All bit fields as a 32-bit value\r | |
| 1513 | ///\r | |
| 2f88bd3a | 1514 | UINT32 Uint32;\r |
| 37cea63f HW |
1515 | ///\r |
| 1516 | /// All bit fields as a 64-bit value\r | |
| 1517 | ///\r | |
| 2f88bd3a | 1518 | UINT64 Uint64;\r |
| 37cea63f HW |
1519 | } MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER;\r |
| 1520 | \r | |
| 6b55a245 MK |
1521 | /**\r |
| 1522 | Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch\r | |
| 1523 | record registers on the last branch record stack. This part of the stack\r | |
| 1524 | contains pointers to the destination instruction. See also: - Last Branch\r | |
| 37cea63f | 1525 | Record Stack TOS at 1C9H - Section 17.10.\r |
| 6b55a245 MK |
1526 | \r |
| 1527 | @param ECX MSR_SKYLAKE_LASTBRANCH_n_TO_IP\r | |
| 1528 | @param EAX Lower 32-bits of MSR value.\r | |
| 1529 | @param EDX Upper 32-bits of MSR value.\r | |
| 1530 | \r | |
| 1531 | <b>Example usage</b>\r | |
| 1532 | @code\r | |
| 1533 | UINT64 Msr;\r | |
| 1534 | \r | |
| 1535 | Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP);\r | |
| 1536 | AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP, Msr);\r | |
| 1537 | @endcode\r | |
| 04e7a465 JF |
1538 | @note MSR_SKYLAKE_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.\r |
| 1539 | MSR_SKYLAKE_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.\r | |
| 1540 | MSR_SKYLAKE_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.\r | |
| 1541 | MSR_SKYLAKE_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.\r | |
| 1542 | MSR_SKYLAKE_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.\r | |
| 1543 | MSR_SKYLAKE_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.\r | |
| 1544 | MSR_SKYLAKE_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.\r | |
| 1545 | MSR_SKYLAKE_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.\r | |
| 1546 | MSR_SKYLAKE_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.\r | |
| 1547 | MSR_SKYLAKE_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.\r | |
| 1548 | MSR_SKYLAKE_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.\r | |
| 1549 | MSR_SKYLAKE_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.\r | |
| 1550 | MSR_SKYLAKE_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.\r | |
| 1551 | MSR_SKYLAKE_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.\r | |
| 1552 | MSR_SKYLAKE_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.\r | |
| 1553 | MSR_SKYLAKE_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.\r | |
| 6b55a245 MK |
1554 | @{\r |
| 1555 | **/\r | |
| 2f88bd3a MK |
1556 | #define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0\r |
| 1557 | #define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1\r | |
| 1558 | #define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2\r | |
| 1559 | #define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3\r | |
| 1560 | #define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4\r | |
| 1561 | #define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5\r | |
| 1562 | #define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6\r | |
| 1563 | #define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7\r | |
| 1564 | #define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8\r | |
| 1565 | #define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9\r | |
| 1566 | #define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA\r | |
| 1567 | #define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB\r | |
| 1568 | #define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC\r | |
| 1569 | #define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD\r | |
| 1570 | #define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE\r | |
| 1571 | #define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF\r | |
| 6b55a245 MK |
1572 | /// @}\r |
| 1573 | \r | |
| 6b55a245 MK |
1574 | /**\r |
| 1575 | Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet\r | |
| 1576 | of last branch record registers on the last branch record stack. This part\r | |
| 1577 | of the stack contains flag, TSX-related and elapsed cycle information. See\r | |
| 37cea63f | 1578 | also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR\r |
| 6b55a245 MK |
1579 | Stack.".\r |
| 1580 | \r | |
| 1581 | @param ECX MSR_SKYLAKE_LBR_INFO_n\r | |
| 1582 | @param EAX Lower 32-bits of MSR value.\r | |
| 1583 | @param EDX Upper 32-bits of MSR value.\r | |
| 1584 | \r | |
| 1585 | <b>Example usage</b>\r | |
| 1586 | @code\r | |
| 1587 | UINT64 Msr;\r | |
| 1588 | \r | |
| 1589 | Msr = AsmReadMsr64 (MSR_SKYLAKE_LBR_INFO_0);\r | |
| 1590 | AsmWriteMsr64 (MSR_SKYLAKE_LBR_INFO_0, Msr);\r | |
| 1591 | @endcode\r | |
| 04e7a465 JF |
1592 | @note MSR_SKYLAKE_LBR_INFO_0 is defined as MSR_LBR_INFO_0 in SDM.\r |
| 1593 | MSR_SKYLAKE_LBR_INFO_1 is defined as MSR_LBR_INFO_1 in SDM.\r | |
| 1594 | MSR_SKYLAKE_LBR_INFO_2 is defined as MSR_LBR_INFO_2 in SDM.\r | |
| 1595 | MSR_SKYLAKE_LBR_INFO_3 is defined as MSR_LBR_INFO_3 in SDM.\r | |
| 1596 | MSR_SKYLAKE_LBR_INFO_4 is defined as MSR_LBR_INFO_4 in SDM.\r | |
| 1597 | MSR_SKYLAKE_LBR_INFO_5 is defined as MSR_LBR_INFO_5 in SDM.\r | |
| 1598 | MSR_SKYLAKE_LBR_INFO_6 is defined as MSR_LBR_INFO_6 in SDM.\r | |
| 1599 | MSR_SKYLAKE_LBR_INFO_7 is defined as MSR_LBR_INFO_7 in SDM.\r | |
| 1600 | MSR_SKYLAKE_LBR_INFO_8 is defined as MSR_LBR_INFO_8 in SDM.\r | |
| 1601 | MSR_SKYLAKE_LBR_INFO_9 is defined as MSR_LBR_INFO_9 in SDM.\r | |
| 1602 | MSR_SKYLAKE_LBR_INFO_10 is defined as MSR_LBR_INFO_10 in SDM.\r | |
| 1603 | MSR_SKYLAKE_LBR_INFO_11 is defined as MSR_LBR_INFO_11 in SDM.\r | |
| 1604 | MSR_SKYLAKE_LBR_INFO_12 is defined as MSR_LBR_INFO_12 in SDM.\r | |
| 1605 | MSR_SKYLAKE_LBR_INFO_13 is defined as MSR_LBR_INFO_13 in SDM.\r | |
| 1606 | MSR_SKYLAKE_LBR_INFO_14 is defined as MSR_LBR_INFO_14 in SDM.\r | |
| 1607 | MSR_SKYLAKE_LBR_INFO_15 is defined as MSR_LBR_INFO_15 in SDM.\r | |
| 1608 | MSR_SKYLAKE_LBR_INFO_16 is defined as MSR_LBR_INFO_16 in SDM.\r | |
| 1609 | MSR_SKYLAKE_LBR_INFO_17 is defined as MSR_LBR_INFO_17 in SDM.\r | |
| 1610 | MSR_SKYLAKE_LBR_INFO_18 is defined as MSR_LBR_INFO_18 in SDM.\r | |
| 1611 | MSR_SKYLAKE_LBR_INFO_19 is defined as MSR_LBR_INFO_19 in SDM.\r | |
| 1612 | MSR_SKYLAKE_LBR_INFO_20 is defined as MSR_LBR_INFO_20 in SDM.\r | |
| 1613 | MSR_SKYLAKE_LBR_INFO_21 is defined as MSR_LBR_INFO_21 in SDM.\r | |
| 1614 | MSR_SKYLAKE_LBR_INFO_22 is defined as MSR_LBR_INFO_22 in SDM.\r | |
| 1615 | MSR_SKYLAKE_LBR_INFO_23 is defined as MSR_LBR_INFO_23 in SDM.\r | |
| 1616 | MSR_SKYLAKE_LBR_INFO_24 is defined as MSR_LBR_INFO_24 in SDM.\r | |
| 1617 | MSR_SKYLAKE_LBR_INFO_25 is defined as MSR_LBR_INFO_25 in SDM.\r | |
| 1618 | MSR_SKYLAKE_LBR_INFO_26 is defined as MSR_LBR_INFO_26 in SDM.\r | |
| 1619 | MSR_SKYLAKE_LBR_INFO_27 is defined as MSR_LBR_INFO_27 in SDM.\r | |
| 1620 | MSR_SKYLAKE_LBR_INFO_28 is defined as MSR_LBR_INFO_28 in SDM.\r | |
| 1621 | MSR_SKYLAKE_LBR_INFO_29 is defined as MSR_LBR_INFO_29 in SDM.\r | |
| 1622 | MSR_SKYLAKE_LBR_INFO_30 is defined as MSR_LBR_INFO_30 in SDM.\r | |
| 1623 | MSR_SKYLAKE_LBR_INFO_31 is defined as MSR_LBR_INFO_31 in SDM.\r | |
| 6b55a245 MK |
1624 | @{\r |
| 1625 | **/\r | |
| 2f88bd3a MK |
1626 | #define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0\r |
| 1627 | #define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1\r | |
| 1628 | #define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2\r | |
| 1629 | #define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3\r | |
| 1630 | #define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4\r | |
| 1631 | #define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5\r | |
| 1632 | #define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6\r | |
| 1633 | #define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7\r | |
| 1634 | #define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8\r | |
| 1635 | #define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9\r | |
| 1636 | #define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA\r | |
| 1637 | #define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB\r | |
| 1638 | #define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC\r | |
| 1639 | #define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD\r | |
| 1640 | #define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE\r | |
| 1641 | #define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF\r | |
| 1642 | #define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0\r | |
| 1643 | #define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1\r | |
| 1644 | #define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2\r | |
| 1645 | #define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3\r | |
| 1646 | #define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4\r | |
| 1647 | #define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5\r | |
| 1648 | #define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6\r | |
| 1649 | #define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7\r | |
| 1650 | #define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8\r | |
| 1651 | #define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9\r | |
| 1652 | #define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA\r | |
| 1653 | #define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB\r | |
| 1654 | #define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC\r | |
| 1655 | #define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD\r | |
| 1656 | #define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE\r | |
| 1657 | #define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF\r | |
| 6b55a245 MK |
1658 | /// @}\r |
| 1659 | \r | |
| 37cea63f HW |
1660 | /**\r |
| 1661 | Package. Uncore fixed counter control (R/W).\r | |
| 1662 | \r | |
| 1663 | @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTRL (0x00000394)\r | |
| 1664 | @param EAX Lower 32-bits of MSR value.\r | |
| 1665 | Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.\r | |
| 1666 | @param EDX Upper 32-bits of MSR value.\r | |
| 1667 | Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.\r | |
| 1668 | \r | |
| 1669 | <b>Example usage</b>\r | |
| 1670 | @code\r | |
| 1671 | MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER Msr;\r | |
| 1672 | \r | |
| 1673 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL);\r | |
| 1674 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL, Msr.Uint64);\r | |
| 1675 | @endcode\r | |
| 1676 | @note MSR_SKYLAKE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r | |
| 1677 | **/\r | |
| 2f88bd3a | 1678 | #define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394\r |
| 37cea63f HW |
1679 | \r |
| 1680 | /**\r | |
| 1681 | MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTRL\r | |
| 1682 | **/\r | |
| 1683 | typedef union {\r | |
| 1684 | ///\r | |
| 1685 | /// Individual bit fields\r | |
| 1686 | ///\r | |
| 1687 | struct {\r | |
| 2f88bd3a | 1688 | UINT32 Reserved1 : 20;\r |
| 37cea63f HW |
1689 | ///\r |
| 1690 | /// [Bit 20] Enable overflow propagation.\r | |
| 1691 | ///\r | |
| 2f88bd3a MK |
1692 | UINT32 EnableOverflow : 1;\r |
| 1693 | UINT32 Reserved2 : 1;\r | |
| 37cea63f HW |
1694 | ///\r |
| 1695 | /// [Bit 22] Enable counting.\r | |
| 1696 | ///\r | |
| 2f88bd3a MK |
1697 | UINT32 EnableCounting : 1;\r |
| 1698 | UINT32 Reserved3 : 9;\r | |
| 1699 | UINT32 Reserved4 : 32;\r | |
| 37cea63f HW |
1700 | } Bits;\r |
| 1701 | ///\r | |
| 1702 | /// All bit fields as a 32-bit value\r | |
| 1703 | ///\r | |
| 2f88bd3a | 1704 | UINT32 Uint32;\r |
| 37cea63f HW |
1705 | ///\r |
| 1706 | /// All bit fields as a 64-bit value\r | |
| 1707 | ///\r | |
| 2f88bd3a | 1708 | UINT64 Uint64;\r |
| 37cea63f HW |
1709 | } MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER;\r |
| 1710 | \r | |
| 37cea63f HW |
1711 | /**\r |
| 1712 | Package. Uncore fixed counter.\r | |
| 1713 | \r | |
| 1714 | @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTR (0x00000395)\r | |
| 1715 | @param EAX Lower 32-bits of MSR value.\r | |
| 1716 | Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.\r | |
| 1717 | @param EDX Upper 32-bits of MSR value.\r | |
| 1718 | Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.\r | |
| 1719 | \r | |
| 1720 | <b>Example usage</b>\r | |
| 1721 | @code\r | |
| 1722 | MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER Msr;\r | |
| 1723 | \r | |
| 1724 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR);\r | |
| 1725 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR, Msr.Uint64);\r | |
| 1726 | @endcode\r | |
| 1727 | @note MSR_SKYLAKE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r | |
| 1728 | **/\r | |
| 2f88bd3a | 1729 | #define MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395\r |
| 37cea63f HW |
1730 | \r |
| 1731 | /**\r | |
| 1732 | MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTR\r | |
| 1733 | **/\r | |
| 1734 | typedef union {\r | |
| 1735 | ///\r | |
| 1736 | /// Individual bit fields\r | |
| 1737 | ///\r | |
| 1738 | struct {\r | |
| 1739 | ///\r | |
| 1740 | /// [Bits 31:0] Current count.\r | |
| 1741 | ///\r | |
| 2f88bd3a | 1742 | UINT32 CurrentCount : 32;\r |
| 37cea63f HW |
1743 | ///\r |
| 1744 | /// [Bits 43:32] Current count.\r | |
| 1745 | ///\r | |
| 2f88bd3a MK |
1746 | UINT32 CurrentCountHi : 12;\r |
| 1747 | UINT32 Reserved : 20;\r | |
| 37cea63f HW |
1748 | } Bits;\r |
| 1749 | ///\r | |
| 1750 | /// All bit fields as a 64-bit value\r | |
| 1751 | ///\r | |
| 2f88bd3a | 1752 | UINT64 Uint64;\r |
| 37cea63f HW |
1753 | } MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER;\r |
| 1754 | \r | |
| 37cea63f HW |
1755 | /**\r |
| 1756 | Package. Uncore C-Box configuration information (R/O).\r | |
| 1757 | \r | |
| 1758 | @param ECX MSR_SKYLAKE_UNC_CBO_CONFIG (0x00000396)\r | |
| 1759 | @param EAX Lower 32-bits of MSR value.\r | |
| 1760 | Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.\r | |
| 1761 | @param EDX Upper 32-bits of MSR value.\r | |
| 1762 | Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.\r | |
| 1763 | \r | |
| 1764 | <b>Example usage</b>\r | |
| 1765 | @code\r | |
| 1766 | MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER Msr;\r | |
| 1767 | \r | |
| 1768 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_CONFIG);\r | |
| 1769 | @endcode\r | |
| 1770 | @note MSR_SKYLAKE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r | |
| 1771 | **/\r | |
| 2f88bd3a | 1772 | #define MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396\r |
| 37cea63f HW |
1773 | \r |
| 1774 | /**\r | |
| 1775 | MSR information returned for MSR index #MSR_SKYLAKE_UNC_CBO_CONFIG\r | |
| 1776 | **/\r | |
| 1777 | typedef union {\r | |
| 1778 | ///\r | |
| 1779 | /// Individual bit fields\r | |
| 1780 | ///\r | |
| 1781 | struct {\r | |
| 1782 | ///\r | |
| 1783 | /// [Bits 3:0] Specifies the number of C-Box units with programmable\r | |
| 1784 | /// counters (including processor cores and processor graphics),.\r | |
| 1785 | ///\r | |
| 2f88bd3a MK |
1786 | UINT32 CBox : 4;\r |
| 1787 | UINT32 Reserved1 : 28;\r | |
| 1788 | UINT32 Reserved2 : 32;\r | |
| 37cea63f HW |
1789 | } Bits;\r |
| 1790 | ///\r | |
| 1791 | /// All bit fields as a 32-bit value\r | |
| 1792 | ///\r | |
| 2f88bd3a | 1793 | UINT32 Uint32;\r |
| 37cea63f HW |
1794 | ///\r |
| 1795 | /// All bit fields as a 64-bit value\r | |
| 1796 | ///\r | |
| 2f88bd3a | 1797 | UINT64 Uint64;\r |
| 37cea63f HW |
1798 | } MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER;\r |
| 1799 | \r | |
| 37cea63f HW |
1800 | /**\r |
| 1801 | Package. Uncore Arb unit, performance counter 0.\r | |
| 1802 | \r | |
| 1803 | @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR0 (0x000003B0)\r | |
| 1804 | @param EAX Lower 32-bits of MSR value.\r | |
| 1805 | @param EDX Upper 32-bits of MSR value.\r | |
| 1806 | \r | |
| 1807 | <b>Example usage</b>\r | |
| 1808 | @code\r | |
| 1809 | UINT64 Msr;\r | |
| 1810 | \r | |
| 1811 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0);\r | |
| 1812 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0, Msr);\r | |
| 1813 | @endcode\r | |
| 1814 | @note MSR_SKYLAKE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r | |
| 1815 | **/\r | |
| 2f88bd3a | 1816 | #define MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0\r |
| 37cea63f HW |
1817 | \r |
| 1818 | /**\r | |
| 1819 | Package. Uncore Arb unit, performance counter 1.\r | |
| 1820 | \r | |
| 1821 | @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR1 (0x000003B1)\r | |
| 1822 | @param EAX Lower 32-bits of MSR value.\r | |
| 1823 | @param EDX Upper 32-bits of MSR value.\r | |
| 1824 | \r | |
| 1825 | <b>Example usage</b>\r | |
| 1826 | @code\r | |
| 1827 | UINT64 Msr;\r | |
| 1828 | \r | |
| 1829 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1);\r | |
| 1830 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1, Msr);\r | |
| 1831 | @endcode\r | |
| 1832 | @note MSR_SKYLAKE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r | |
| 1833 | **/\r | |
| 2f88bd3a | 1834 | #define MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1\r |
| 37cea63f HW |
1835 | \r |
| 1836 | /**\r | |
| 1837 | Package. Uncore Arb unit, counter 0 event select MSR.\r | |
| 1838 | \r | |
| 1839 | @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 (0x000003B2)\r | |
| 1840 | @param EAX Lower 32-bits of MSR value.\r | |
| 1841 | @param EDX Upper 32-bits of MSR value.\r | |
| 1842 | \r | |
| 1843 | <b>Example usage</b>\r | |
| 1844 | @code\r | |
| 1845 | UINT64 Msr;\r | |
| 1846 | \r | |
| 1847 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0);\r | |
| 1848 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0, Msr);\r | |
| 1849 | @endcode\r | |
| 1850 | @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r | |
| 1851 | **/\r | |
| 2f88bd3a | 1852 | #define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2\r |
| 37cea63f HW |
1853 | \r |
| 1854 | /**\r | |
| 1855 | Package. Uncore Arb unit, counter 1 event select MSR.\r | |
| 1856 | \r | |
| 1857 | @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 (0x000003B3)\r | |
| 1858 | @param EAX Lower 32-bits of MSR value.\r | |
| 1859 | @param EDX Upper 32-bits of MSR value.\r | |
| 1860 | \r | |
| 1861 | <b>Example usage</b>\r | |
| 1862 | @code\r | |
| 1863 | UINT64 Msr;\r | |
| 1864 | \r | |
| 1865 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1);\r | |
| 1866 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1, Msr);\r | |
| 1867 | @endcode\r | |
| 1868 | @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 is defined as MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 in SDM.\r | |
| 1869 | **/\r | |
| 2f88bd3a | 1870 | #define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3\r |
| 37cea63f HW |
1871 | \r |
| 1872 | /**\r | |
| 1873 | Package. Uncore C-Box 0, counter 0 event select MSR.\r | |
| 1874 | \r | |
| 1875 | @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 (0x00000700)\r | |
| 1876 | @param EAX Lower 32-bits of MSR value.\r | |
| 1877 | @param EDX Upper 32-bits of MSR value.\r | |
| 1878 | \r | |
| 1879 | <b>Example usage</b>\r | |
| 1880 | @code\r | |
| 1881 | UINT64 Msr;\r | |
| 1882 | \r | |
| 1883 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0);\r | |
| 1884 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0, Msr);\r | |
| 1885 | @endcode\r | |
| 1886 | @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r | |
| 1887 | **/\r | |
| 2f88bd3a | 1888 | #define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700\r |
| 37cea63f HW |
1889 | \r |
| 1890 | /**\r | |
| 1891 | Package. Uncore C-Box 0, counter 1 event select MSR.\r | |
| 1892 | \r | |
| 1893 | @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 (0x00000701)\r | |
| 1894 | @param EAX Lower 32-bits of MSR value.\r | |
| 1895 | @param EDX Upper 32-bits of MSR value.\r | |
| 1896 | \r | |
| 1897 | <b>Example usage</b>\r | |
| 1898 | @code\r | |
| 1899 | UINT64 Msr;\r | |
| 1900 | \r | |
| 1901 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1);\r | |
| 1902 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1, Msr);\r | |
| 1903 | @endcode\r | |
| 1904 | @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r | |
| 1905 | **/\r | |
| 2f88bd3a | 1906 | #define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r |
| 37cea63f HW |
1907 | \r |
| 1908 | /**\r | |
| 1909 | Package. Uncore C-Box 0, performance counter 0.\r | |
| 1910 | \r | |
| 1911 | @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 (0x00000706)\r | |
| 1912 | @param EAX Lower 32-bits of MSR value.\r | |
| 1913 | @param EDX Upper 32-bits of MSR value.\r | |
| 1914 | \r | |
| 1915 | <b>Example usage</b>\r | |
| 1916 | @code\r | |
| 1917 | UINT64 Msr;\r | |
| 1918 | \r | |
| 1919 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0);\r | |
| 1920 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0, Msr);\r | |
| 1921 | @endcode\r | |
| 1922 | @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r | |
| 1923 | **/\r | |
| 2f88bd3a | 1924 | #define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706\r |
| 37cea63f HW |
1925 | \r |
| 1926 | /**\r | |
| 1927 | Package. Uncore C-Box 0, performance counter 1.\r | |
| 1928 | \r | |
| 1929 | @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 (0x00000707)\r | |
| 1930 | @param EAX Lower 32-bits of MSR value.\r | |
| 1931 | @param EDX Upper 32-bits of MSR value.\r | |
| 1932 | \r | |
| 1933 | <b>Example usage</b>\r | |
| 1934 | @code\r | |
| 1935 | UINT64 Msr;\r | |
| 1936 | \r | |
| 1937 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1);\r | |
| 1938 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1, Msr);\r | |
| 1939 | @endcode\r | |
| 1940 | @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r | |
| 1941 | **/\r | |
| 2f88bd3a | 1942 | #define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707\r |
| 37cea63f HW |
1943 | \r |
| 1944 | /**\r | |
| 1945 | Package. Uncore C-Box 1, counter 0 event select MSR.\r | |
| 1946 | \r | |
| 1947 | @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 (0x00000710)\r | |
| 1948 | @param EAX Lower 32-bits of MSR value.\r | |
| 1949 | @param EDX Upper 32-bits of MSR value.\r | |
| 1950 | \r | |
| 1951 | <b>Example usage</b>\r | |
| 1952 | @code\r | |
| 1953 | UINT64 Msr;\r | |
| 1954 | \r | |
| 1955 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0);\r | |
| 1956 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0, Msr);\r | |
| 1957 | @endcode\r | |
| 1958 | @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r | |
| 1959 | **/\r | |
| 2f88bd3a | 1960 | #define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710\r |
| 37cea63f HW |
1961 | \r |
| 1962 | /**\r | |
| 1963 | Package. Uncore C-Box 1, counter 1 event select MSR.\r | |
| 1964 | \r | |
| 1965 | @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 (0x00000711)\r | |
| 1966 | @param EAX Lower 32-bits of MSR value.\r | |
| 1967 | @param EDX Upper 32-bits of MSR value.\r | |
| 1968 | \r | |
| 1969 | <b>Example usage</b>\r | |
| 1970 | @code\r | |
| 1971 | UINT64 Msr;\r | |
| 1972 | \r | |
| 1973 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1);\r | |
| 1974 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1, Msr);\r | |
| 1975 | @endcode\r | |
| 1976 | @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r | |
| 1977 | **/\r | |
| 2f88bd3a | 1978 | #define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711\r |
| 37cea63f HW |
1979 | \r |
| 1980 | /**\r | |
| 1981 | Package. Uncore C-Box 1, performance counter 0.\r | |
| 1982 | \r | |
| 1983 | @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 (0x00000716)\r | |
| 1984 | @param EAX Lower 32-bits of MSR value.\r | |
| 1985 | @param EDX Upper 32-bits of MSR value.\r | |
| 1986 | \r | |
| 1987 | <b>Example usage</b>\r | |
| 1988 | @code\r | |
| 1989 | UINT64 Msr;\r | |
| 1990 | \r | |
| 1991 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0);\r | |
| 1992 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0, Msr);\r | |
| 1993 | @endcode\r | |
| 1994 | @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r | |
| 1995 | **/\r | |
| 2f88bd3a | 1996 | #define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716\r |
| 37cea63f HW |
1997 | \r |
| 1998 | /**\r | |
| 1999 | Package. Uncore C-Box 1, performance counter 1.\r | |
| 2000 | \r | |
| 2001 | @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 (0x00000717)\r | |
| 2002 | @param EAX Lower 32-bits of MSR value.\r | |
| 2003 | @param EDX Upper 32-bits of MSR value.\r | |
| 2004 | \r | |
| 2005 | <b>Example usage</b>\r | |
| 2006 | @code\r | |
| 2007 | UINT64 Msr;\r | |
| 2008 | \r | |
| 2009 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1);\r | |
| 2010 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1, Msr);\r | |
| 2011 | @endcode\r | |
| 2012 | @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r | |
| 2013 | **/\r | |
| 2f88bd3a | 2014 | #define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717\r |
| 37cea63f HW |
2015 | \r |
| 2016 | /**\r | |
| 2017 | Package. Uncore C-Box 2, counter 0 event select MSR.\r | |
| 2018 | \r | |
| 2019 | @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 (0x00000720)\r | |
| 2020 | @param EAX Lower 32-bits of MSR value.\r | |
| 2021 | @param EDX Upper 32-bits of MSR value.\r | |
| 2022 | \r | |
| 2023 | <b>Example usage</b>\r | |
| 2024 | @code\r | |
| 2025 | UINT64 Msr;\r | |
| 2026 | \r | |
| 2027 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0);\r | |
| 2028 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0, Msr);\r | |
| 2029 | @endcode\r | |
| 2030 | @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r | |
| 2031 | **/\r | |
| 2f88bd3a | 2032 | #define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720\r |
| 37cea63f HW |
2033 | \r |
| 2034 | /**\r | |
| 2035 | Package. Uncore C-Box 2, counter 1 event select MSR.\r | |
| 2036 | \r | |
| 2037 | @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 (0x00000721)\r | |
| 2038 | @param EAX Lower 32-bits of MSR value.\r | |
| 2039 | @param EDX Upper 32-bits of MSR value.\r | |
| 2040 | \r | |
| 2041 | <b>Example usage</b>\r | |
| 2042 | @code\r | |
| 2043 | UINT64 Msr;\r | |
| 2044 | \r | |
| 2045 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1);\r | |
| 2046 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1, Msr);\r | |
| 2047 | @endcode\r | |
| 2048 | @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r | |
| 2049 | **/\r | |
| 2f88bd3a | 2050 | #define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721\r |
| 37cea63f HW |
2051 | \r |
| 2052 | /**\r | |
| 2053 | Package. Uncore C-Box 2, performance counter 0.\r | |
| 2054 | \r | |
| 2055 | @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 (0x00000726)\r | |
| 2056 | @param EAX Lower 32-bits of MSR value.\r | |
| 2057 | @param EDX Upper 32-bits of MSR value.\r | |
| 2058 | \r | |
| 2059 | <b>Example usage</b>\r | |
| 2060 | @code\r | |
| 2061 | UINT64 Msr;\r | |
| 2062 | \r | |
| 2063 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0);\r | |
| 2064 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0, Msr);\r | |
| 2065 | @endcode\r | |
| 2066 | @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r | |
| 2067 | **/\r | |
| 2f88bd3a | 2068 | #define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726\r |
| 37cea63f HW |
2069 | \r |
| 2070 | /**\r | |
| 2071 | Package. Uncore C-Box 2, performance counter 1.\r | |
| 2072 | \r | |
| 2073 | @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 (0x00000727)\r | |
| 2074 | @param EAX Lower 32-bits of MSR value.\r | |
| 2075 | @param EDX Upper 32-bits of MSR value.\r | |
| 2076 | \r | |
| 2077 | <b>Example usage</b>\r | |
| 2078 | @code\r | |
| 2079 | UINT64 Msr;\r | |
| 2080 | \r | |
| 2081 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1);\r | |
| 2082 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1, Msr);\r | |
| 2083 | @endcode\r | |
| 2084 | @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r | |
| 2085 | **/\r | |
| 2f88bd3a | 2086 | #define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727\r |
| 37cea63f HW |
2087 | \r |
| 2088 | /**\r | |
| 2089 | Package. Uncore C-Box 3, counter 0 event select MSR.\r | |
| 2090 | \r | |
| 2091 | @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 (0x00000730)\r | |
| 2092 | @param EAX Lower 32-bits of MSR value.\r | |
| 2093 | @param EDX Upper 32-bits of MSR value.\r | |
| 2094 | \r | |
| 2095 | <b>Example usage</b>\r | |
| 2096 | @code\r | |
| 2097 | UINT64 Msr;\r | |
| 2098 | \r | |
| 2099 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0);\r | |
| 2100 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0, Msr);\r | |
| 2101 | @endcode\r | |
| 2102 | @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r | |
| 2103 | **/\r | |
| 2f88bd3a | 2104 | #define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730\r |
| 37cea63f HW |
2105 | \r |
| 2106 | /**\r | |
| 2107 | Package. Uncore C-Box 3, counter 1 event select MSR.\r | |
| 2108 | \r | |
| 2109 | @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 (0x00000731)\r | |
| 2110 | @param EAX Lower 32-bits of MSR value.\r | |
| 2111 | @param EDX Upper 32-bits of MSR value.\r | |
| 2112 | \r | |
| 2113 | <b>Example usage</b>\r | |
| 2114 | @code\r | |
| 2115 | UINT64 Msr;\r | |
| 2116 | \r | |
| 2117 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1);\r | |
| 2118 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1, Msr);\r | |
| 2119 | @endcode\r | |
| 2120 | @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r | |
| 2121 | **/\r | |
| 2f88bd3a | 2122 | #define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r |
| 37cea63f HW |
2123 | \r |
| 2124 | /**\r | |
| 2125 | Package. Uncore C-Box 3, performance counter 0.\r | |
| 2126 | \r | |
| 2127 | @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 (0x00000736)\r | |
| 2128 | @param EAX Lower 32-bits of MSR value.\r | |
| 2129 | @param EDX Upper 32-bits of MSR value.\r | |
| 2130 | \r | |
| 2131 | <b>Example usage</b>\r | |
| 2132 | @code\r | |
| 2133 | UINT64 Msr;\r | |
| 2134 | \r | |
| 2135 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0);\r | |
| 2136 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0, Msr);\r | |
| 2137 | @endcode\r | |
| 2138 | @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r | |
| 2139 | **/\r | |
| 2f88bd3a | 2140 | #define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736\r |
| 37cea63f HW |
2141 | \r |
| 2142 | /**\r | |
| 2143 | Package. Uncore C-Box 3, performance counter 1.\r | |
| 2144 | \r | |
| 2145 | @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 (0x00000737)\r | |
| 2146 | @param EAX Lower 32-bits of MSR value.\r | |
| 2147 | @param EDX Upper 32-bits of MSR value.\r | |
| 2148 | \r | |
| 2149 | <b>Example usage</b>\r | |
| 2150 | @code\r | |
| 2151 | UINT64 Msr;\r | |
| 2152 | \r | |
| 2153 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1);\r | |
| 2154 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1, Msr);\r | |
| 2155 | @endcode\r | |
| 2156 | @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r | |
| 2157 | **/\r | |
| 2f88bd3a | 2158 | #define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737\r |
| 37cea63f HW |
2159 | \r |
| 2160 | /**\r | |
| 2161 | Package. Uncore PMU global control.\r | |
| 2162 | \r | |
| 2163 | @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL (0x00000E01)\r | |
| 2164 | @param EAX Lower 32-bits of MSR value.\r | |
| 2165 | Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r | |
| 2166 | @param EDX Upper 32-bits of MSR value.\r | |
| 2167 | Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r | |
| 2168 | \r | |
| 2169 | <b>Example usage</b>\r | |
| 2170 | @code\r | |
| 2171 | MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;\r | |
| 2172 | \r | |
| 2173 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL);\r | |
| 2174 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);\r | |
| 2175 | @endcode\r | |
| 2176 | @note MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r | |
| 2177 | **/\r | |
| 2f88bd3a | 2178 | #define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01\r |
| 37cea63f HW |
2179 | \r |
| 2180 | /**\r | |
| 2181 | MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL\r | |
| 2182 | **/\r | |
| 2183 | typedef union {\r | |
| 2184 | ///\r | |
| 2185 | /// Individual bit fields\r | |
| 2186 | ///\r | |
| 2187 | struct {\r | |
| 2188 | ///\r | |
| 2189 | /// [Bit 0] Slice 0 select.\r | |
| 2190 | ///\r | |
| 2f88bd3a | 2191 | UINT32 PMI_Sel_Slice0 : 1;\r |
| 37cea63f HW |
2192 | ///\r |
| 2193 | /// [Bit 1] Slice 1 select.\r | |
| 2194 | ///\r | |
| 2f88bd3a | 2195 | UINT32 PMI_Sel_Slice1 : 1;\r |
| 37cea63f HW |
2196 | ///\r |
| 2197 | /// [Bit 2] Slice 2 select.\r | |
| 2198 | ///\r | |
| 2f88bd3a | 2199 | UINT32 PMI_Sel_Slice2 : 1;\r |
| 37cea63f HW |
2200 | ///\r |
| 2201 | /// [Bit 3] Slice 3 select.\r | |
| 2202 | ///\r | |
| 2f88bd3a | 2203 | UINT32 PMI_Sel_Slice3 : 1;\r |
| 37cea63f HW |
2204 | ///\r |
| 2205 | /// [Bit 4] Slice 4select.\r | |
| 2206 | ///\r | |
| 2f88bd3a MK |
2207 | UINT32 PMI_Sel_Slice4 : 1;\r |
| 2208 | UINT32 Reserved1 : 14;\r | |
| 2209 | UINT32 Reserved2 : 10;\r | |
| 37cea63f HW |
2210 | ///\r |
| 2211 | /// [Bit 29] Enable all uncore counters.\r | |
| 2212 | ///\r | |
| 2f88bd3a | 2213 | UINT32 EN : 1;\r |
| 37cea63f HW |
2214 | ///\r |
| 2215 | /// [Bit 30] Enable wake on PMI.\r | |
| 2216 | ///\r | |
| 2f88bd3a | 2217 | UINT32 WakePMI : 1;\r |
| 37cea63f HW |
2218 | ///\r |
| 2219 | /// [Bit 31] Enable Freezing counter when overflow.\r | |
| 2220 | ///\r | |
| 2f88bd3a MK |
2221 | UINT32 FREEZE : 1;\r |
| 2222 | UINT32 Reserved3 : 32;\r | |
| 37cea63f HW |
2223 | } Bits;\r |
| 2224 | ///\r | |
| 2225 | /// All bit fields as a 32-bit value\r | |
| 2226 | ///\r | |
| 2f88bd3a | 2227 | UINT32 Uint32;\r |
| 37cea63f HW |
2228 | ///\r |
| 2229 | /// All bit fields as a 64-bit value\r | |
| 2230 | ///\r | |
| 2f88bd3a | 2231 | UINT64 Uint64;\r |
| 37cea63f HW |
2232 | } MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER;\r |
| 2233 | \r | |
| 37cea63f HW |
2234 | /**\r |
| 2235 | Package. Uncore PMU main status.\r | |
| 2236 | \r | |
| 2237 | @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS (0x00000E02)\r | |
| 2238 | @param EAX Lower 32-bits of MSR value.\r | |
| 2239 | Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r | |
| 2240 | @param EDX Upper 32-bits of MSR value.\r | |
| 2241 | Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r | |
| 2242 | \r | |
| 2243 | <b>Example usage</b>\r | |
| 2244 | @code\r | |
| 2245 | MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;\r | |
| 2246 | \r | |
| 2247 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS);\r | |
| 2248 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);\r | |
| 2249 | @endcode\r | |
| 2250 | @note MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.\r | |
| 2251 | **/\r | |
| 2f88bd3a | 2252 | #define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02\r |
| 37cea63f HW |
2253 | \r |
| 2254 | /**\r | |
| 2255 | MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS\r | |
| 2256 | **/\r | |
| 2257 | typedef union {\r | |
| 2258 | ///\r | |
| 2259 | /// Individual bit fields\r | |
| 2260 | ///\r | |
| 2261 | struct {\r | |
| 2262 | ///\r | |
| 2263 | /// [Bit 0] Fixed counter overflowed.\r | |
| 2264 | ///\r | |
| 2f88bd3a | 2265 | UINT32 Fixed : 1;\r |
| 37cea63f HW |
2266 | ///\r |
| 2267 | /// [Bit 1] An ARB counter overflowed.\r | |
| 2268 | ///\r | |
| 2f88bd3a MK |
2269 | UINT32 ARB : 1;\r |
| 2270 | UINT32 Reserved1 : 1;\r | |
| 37cea63f HW |
2271 | ///\r |
| 2272 | /// [Bit 3] A CBox counter overflowed (on any slice).\r | |
| 2273 | ///\r | |
| 2f88bd3a MK |
2274 | UINT32 CBox : 1;\r |
| 2275 | UINT32 Reserved2 : 28;\r | |
| 2276 | UINT32 Reserved3 : 32;\r | |
| 37cea63f HW |
2277 | } Bits;\r |
| 2278 | ///\r | |
| 2279 | /// All bit fields as a 32-bit value\r | |
| 2280 | ///\r | |
| 2f88bd3a | 2281 | UINT32 Uint32;\r |
| 37cea63f HW |
2282 | ///\r |
| 2283 | /// All bit fields as a 64-bit value\r | |
| 2284 | ///\r | |
| 2f88bd3a | 2285 | UINT64 Uint64;\r |
| 37cea63f HW |
2286 | } MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER;\r |
| 2287 | \r | |
| 3add0205 ED |
2288 | /**\r |
| 2289 | Package. NPK Address Used by AET Messages (R/W).\r | |
| 2290 | \r | |
| 2291 | @param ECX MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE (0x00000080)\r | |
| 2292 | @param EAX Lower 32-bits of MSR value.\r | |
| 2293 | Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.\r | |
| 2294 | @param EDX Upper 32-bits of MSR value.\r | |
| 2295 | Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.\r | |
| 2296 | \r | |
| 2297 | <b>Example usage</b>\r | |
| 2298 | @code\r | |
| 2299 | MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER Msr;\r | |
| 2300 | \r | |
| 2301 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE);\r | |
| 2302 | AsmWriteMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE, Msr.Uint64);\r | |
| 2303 | @endcode\r | |
| 2304 | **/\r | |
| 2f88bd3a | 2305 | #define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080\r |
| 3add0205 ED |
2306 | \r |
| 2307 | /**\r | |
| 2308 | MSR information returned for MSR index\r | |
| 2309 | #MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE\r | |
| 2310 | **/\r | |
| 2311 | typedef union {\r | |
| 2312 | ///\r | |
| 2313 | /// Individual bit fields\r | |
| 2314 | ///\r | |
| 2315 | struct {\r | |
| 2316 | ///\r | |
| 2317 | /// [Bit 0] Lock Bit If set, this MSR cannot be re-written anymore. Lock\r | |
| 2318 | /// bit has to be set in order for the AET packets to be directed to NPK\r | |
| 2319 | /// MMIO.\r | |
| 2320 | ///\r | |
| 2f88bd3a MK |
2321 | UINT32 Fix_Me_1 : 1;\r |
| 2322 | UINT32 Reserved : 17;\r | |
| 3add0205 ED |
2323 | ///\r |
| 2324 | /// [Bits 31:18] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.\r | |
| 2325 | ///\r | |
| 2f88bd3a | 2326 | UINT32 ACPIBAR_BASE_ADDRESS : 14;\r |
| 3add0205 ED |
2327 | ///\r |
| 2328 | /// [Bits 63:32] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.\r | |
| 2329 | ///\r | |
| 2f88bd3a | 2330 | UINT32 Fix_Me_2 : 32;\r |
| 3add0205 ED |
2331 | } Bits;\r |
| 2332 | ///\r | |
| 2333 | /// All bit fields as a 64-bit value\r | |
| 2334 | ///\r | |
| 2f88bd3a | 2335 | UINT64 Uint64;\r |
| 3add0205 ED |
2336 | } MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER;\r |
| 2337 | \r | |
| 3add0205 ED |
2338 | /**\r |
| 2339 | Core. Processor Reserved Memory Range Register - Physical Base Control\r | |
| 2340 | Register (R/W).\r | |
| 2341 | \r | |
| 2342 | @param ECX MSR_SKYLAKE_PRMRR_PHYS_BASE (0x000001F4)\r | |
| 2343 | @param EAX Lower 32-bits of MSR value.\r | |
| 2344 | Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.\r | |
| 2345 | @param EDX Upper 32-bits of MSR value.\r | |
| 2346 | Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.\r | |
| 2347 | \r | |
| 2348 | <b>Example usage</b>\r | |
| 2349 | @code\r | |
| 2350 | MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER Msr;\r | |
| 2351 | \r | |
| 2352 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE);\r | |
| 2353 | AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE, Msr.Uint64);\r | |
| 2354 | @endcode\r | |
| 2355 | **/\r | |
| 2f88bd3a | 2356 | #define MSR_SKYLAKE_PRMRR_PHYS_BASE 0x000001F4\r |
| 3add0205 ED |
2357 | \r |
| 2358 | /**\r | |
| 2359 | MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_BASE\r | |
| 2360 | **/\r | |
| 2361 | typedef union {\r | |
| 2362 | ///\r | |
| 2363 | /// Individual bit fields\r | |
| 2364 | ///\r | |
| 2365 | struct {\r | |
| 2366 | ///\r | |
| 2367 | /// [Bits 2:0] MemType PRMRR BASE MemType.\r | |
| 2368 | ///\r | |
| 2f88bd3a MK |
2369 | UINT32 MemTypePRMRRBASEMemType : 3;\r |
| 2370 | UINT32 Reserved1 : 9;\r | |
| 3add0205 ED |
2371 | ///\r |
| 2372 | /// [Bits 31:12] Base PRMRR Base Address.\r | |
| 2373 | ///\r | |
| 2f88bd3a | 2374 | UINT32 BasePRMRRBaseAddress : 20;\r |
| 3add0205 ED |
2375 | ///\r |
| 2376 | /// [Bits 45:32] Base PRMRR Base Address.\r | |
| 2377 | ///\r | |
| 2f88bd3a MK |
2378 | UINT32 Fix_Me_1 : 14;\r |
| 2379 | UINT32 Reserved2 : 18;\r | |
| 3add0205 ED |
2380 | } Bits;\r |
| 2381 | ///\r | |
| 2382 | /// All bit fields as a 64-bit value\r | |
| 2383 | ///\r | |
| 2f88bd3a | 2384 | UINT64 Uint64;\r |
| 3add0205 ED |
2385 | } MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER;\r |
| 2386 | \r | |
| 3add0205 ED |
2387 | /**\r |
| 2388 | Core. Processor Reserved Memory Range Register - Physical Mask Control\r | |
| 2389 | Register (R/W).\r | |
| 2390 | \r | |
| 2391 | @param ECX MSR_SKYLAKE_PRMRR_PHYS_MASK (0x000001F5)\r | |
| 2392 | @param EAX Lower 32-bits of MSR value.\r | |
| 2393 | Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.\r | |
| 2394 | @param EDX Upper 32-bits of MSR value.\r | |
| 2395 | Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.\r | |
| 2396 | \r | |
| 2397 | <b>Example usage</b>\r | |
| 2398 | @code\r | |
| 2399 | MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER Msr;\r | |
| 2400 | \r | |
| 2401 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK);\r | |
| 2402 | AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK, Msr.Uint64);\r | |
| 2403 | @endcode\r | |
| 2404 | **/\r | |
| 2f88bd3a | 2405 | #define MSR_SKYLAKE_PRMRR_PHYS_MASK 0x000001F5\r |
| 3add0205 ED |
2406 | \r |
| 2407 | /**\r | |
| 2408 | MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_MASK\r | |
| 2409 | **/\r | |
| 2410 | typedef union {\r | |
| 2411 | ///\r | |
| 2412 | /// Individual bit fields\r | |
| 2413 | ///\r | |
| 2414 | struct {\r | |
| 2f88bd3a | 2415 | UINT32 Reserved1 : 10;\r |
| 3add0205 ED |
2416 | ///\r |
| 2417 | /// [Bit 10] Lock Lock bit for the PRMRR.\r | |
| 2418 | ///\r | |
| 2f88bd3a | 2419 | UINT32 Fix_Me_1 : 1;\r |
| 3add0205 ED |
2420 | ///\r |
| 2421 | /// [Bit 11] VLD Enable bit for the PRMRR.\r | |
| 2422 | ///\r | |
| 2f88bd3a | 2423 | UINT32 VLD : 1;\r |
| 3add0205 ED |
2424 | ///\r |
| 2425 | /// [Bits 31:12] Mask PRMRR MASK bits.\r | |
| 2426 | ///\r | |
| 2f88bd3a | 2427 | UINT32 Fix_Me_2 : 20;\r |
| 3add0205 ED |
2428 | ///\r |
| 2429 | /// [Bits 45:32] Mask PRMRR MASK bits.\r | |
| 2430 | ///\r | |
| 2f88bd3a MK |
2431 | UINT32 Fix_Me_3 : 14;\r |
| 2432 | UINT32 Reserved2 : 18;\r | |
| 3add0205 ED |
2433 | } Bits;\r |
| 2434 | ///\r | |
| 2435 | /// All bit fields as a 64-bit value\r | |
| 2436 | ///\r | |
| 2f88bd3a | 2437 | UINT64 Uint64;\r |
| 3add0205 ED |
2438 | } MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER;\r |
| 2439 | \r | |
| 3add0205 ED |
2440 | /**\r |
| 2441 | Core. Valid PRMRR Configurations (R/W).\r | |
| 2442 | \r | |
| 2443 | @param ECX MSR_SKYLAKE_PRMRR_VALID_CONFIG (0x000001FB)\r | |
| 2444 | @param EAX Lower 32-bits of MSR value.\r | |
| 2445 | Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.\r | |
| 2446 | @param EDX Upper 32-bits of MSR value.\r | |
| 2447 | Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.\r | |
| 2448 | \r | |
| 2449 | <b>Example usage</b>\r | |
| 2450 | @code\r | |
| 2451 | MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER Msr;\r | |
| 2452 | \r | |
| 2453 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG);\r | |
| 2454 | AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG, Msr.Uint64);\r | |
| 2455 | @endcode\r | |
| 2456 | **/\r | |
| 2f88bd3a | 2457 | #define MSR_SKYLAKE_PRMRR_VALID_CONFIG 0x000001FB\r |
| 3add0205 ED |
2458 | \r |
| 2459 | /**\r | |
| 2460 | MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_VALID_CONFIG\r | |
| 2461 | **/\r | |
| 2462 | typedef union {\r | |
| 2463 | ///\r | |
| 2464 | /// Individual bit fields\r | |
| 2465 | ///\r | |
| 2466 | struct {\r | |
| 2467 | ///\r | |
| 2468 | /// [Bit 0] 1M supported MEE size.\r | |
| 2469 | ///\r | |
| 2f88bd3a MK |
2470 | UINT32 Fix_Me_1 : 1;\r |
| 2471 | UINT32 Reserved1 : 4;\r | |
| 3add0205 ED |
2472 | ///\r |
| 2473 | /// [Bit 5] 32M supported MEE size.\r | |
| 2474 | ///\r | |
| 2f88bd3a | 2475 | UINT32 Fix_Me_2 : 1;\r |
| 3add0205 ED |
2476 | ///\r |
| 2477 | /// [Bit 6] 64M supported MEE size.\r | |
| 2478 | ///\r | |
| 2f88bd3a | 2479 | UINT32 Fix_Me_3 : 1;\r |
| 3add0205 ED |
2480 | ///\r |
| 2481 | /// [Bit 7] 128M supported MEE size.\r | |
| 2482 | ///\r | |
| 2f88bd3a MK |
2483 | UINT32 Fix_Me_4 : 1;\r |
| 2484 | UINT32 Reserved2 : 24;\r | |
| 2485 | UINT32 Reserved3 : 32;\r | |
| 3add0205 ED |
2486 | } Bits;\r |
| 2487 | ///\r | |
| 2488 | /// All bit fields as a 32-bit value\r | |
| 2489 | ///\r | |
| 2f88bd3a | 2490 | UINT32 Uint32;\r |
| 3add0205 ED |
2491 | ///\r |
| 2492 | /// All bit fields as a 64-bit value\r | |
| 2493 | ///\r | |
| 2f88bd3a | 2494 | UINT64 Uint64;\r |
| 3add0205 ED |
2495 | } MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER;\r |
| 2496 | \r | |
| 3add0205 ED |
2497 | /**\r |
| 2498 | Package. (R/W) The PRMRR range is used to protect Xucode memory from\r | |
| 2499 | unauthorized reads and writes. Any IO access to this range is aborted. This\r | |
| 2500 | register controls the location of the PRMRR range by indicating its starting\r | |
| 2501 | address. It functions in tandem with the PRMRR mask register.\r | |
| 2502 | \r | |
| 2503 | @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE (0x000002F4)\r | |
| 2504 | @param EAX Lower 32-bits of MSR value.\r | |
| 2505 | Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.\r | |
| 2506 | @param EDX Upper 32-bits of MSR value.\r | |
| 2507 | Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.\r | |
| 2508 | \r | |
| 2509 | <b>Example usage</b>\r | |
| 2510 | @code\r | |
| 2511 | MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER Msr;\r | |
| 2512 | \r | |
| 2513 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE);\r | |
| 2514 | AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE, Msr.Uint64);\r | |
| 2515 | @endcode\r | |
| 2516 | **/\r | |
| 2f88bd3a | 2517 | #define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE 0x000002F4\r |
| 3add0205 ED |
2518 | \r |
| 2519 | /**\r | |
| 2520 | MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE\r | |
| 2521 | **/\r | |
| 2522 | typedef union {\r | |
| 2523 | ///\r | |
| 2524 | /// Individual bit fields\r | |
| 2525 | ///\r | |
| 2526 | struct {\r | |
| 2f88bd3a | 2527 | UINT32 Reserved1 : 12;\r |
| 3add0205 ED |
2528 | ///\r |
| 2529 | /// [Bits 31:12] Range Base This field corresponds to bits 38:12 of the\r | |
| 2530 | /// base address memory range which is allocated to PRMRR memory.\r | |
| 2531 | ///\r | |
| 2f88bd3a | 2532 | UINT32 Fix_Me_1 : 20;\r |
| 3add0205 ED |
2533 | ///\r |
| 2534 | /// [Bits 38:32] Range Base This field corresponds to bits 38:12 of the\r | |
| 2535 | /// base address memory range which is allocated to PRMRR memory.\r | |
| 2536 | ///\r | |
| 2f88bd3a MK |
2537 | UINT32 Fix_Me_2 : 7;\r |
| 2538 | UINT32 Reserved2 : 25;\r | |
| 3add0205 ED |
2539 | } Bits;\r |
| 2540 | ///\r | |
| 2541 | /// All bit fields as a 64-bit value\r | |
| 2542 | ///\r | |
| 2f88bd3a | 2543 | UINT64 Uint64;\r |
| 3add0205 ED |
2544 | } MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER;\r |
| 2545 | \r | |
| 3add0205 ED |
2546 | /**\r |
| 2547 | Package. (R/W) This register controls the size of the PRMRR range by\r | |
| 2548 | indicating which address bits must match the PRMRR base register value.\r | |
| 2549 | \r | |
| 2550 | @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK (0x000002F5)\r | |
| 2551 | @param EAX Lower 32-bits of MSR value.\r | |
| 2552 | Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.\r | |
| 2553 | @param EDX Upper 32-bits of MSR value.\r | |
| 2554 | Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.\r | |
| 2555 | \r | |
| 2556 | <b>Example usage</b>\r | |
| 2557 | @code\r | |
| 2558 | MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER Msr;\r | |
| 2559 | \r | |
| 2560 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK);\r | |
| 2561 | AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK, Msr.Uint64);\r | |
| 2562 | @endcode\r | |
| 2563 | **/\r | |
| 2f88bd3a | 2564 | #define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK 0x000002F5\r |
| 3add0205 ED |
2565 | \r |
| 2566 | /**\r | |
| 2567 | MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK\r | |
| 2568 | **/\r | |
| 2569 | typedef union {\r | |
| 2570 | ///\r | |
| 2571 | /// Individual bit fields\r | |
| 2572 | ///\r | |
| 2573 | struct {\r | |
| 2f88bd3a | 2574 | UINT32 Reserved1 : 10;\r |
| 3add0205 ED |
2575 | ///\r |
| 2576 | /// [Bit 10] Lock Setting this bit locks all writeable settings in this\r | |
| 2577 | /// register, including itself.\r | |
| 2578 | ///\r | |
| 2f88bd3a | 2579 | UINT32 Fix_Me_1 : 1;\r |
| 3add0205 ED |
2580 | ///\r |
| 2581 | /// [Bit 11] Range_En Indicates whether the PRMRR range is enabled and\r | |
| 2582 | /// valid.\r | |
| 2583 | ///\r | |
| 2f88bd3a MK |
2584 | UINT32 Fix_Me_2 : 1;\r |
| 2585 | UINT32 Reserved2 : 20;\r | |
| 2586 | UINT32 Reserved3 : 32;\r | |
| 3add0205 ED |
2587 | } Bits;\r |
| 2588 | ///\r | |
| 2589 | /// All bit fields as a 32-bit value\r | |
| 2590 | ///\r | |
| 2f88bd3a | 2591 | UINT32 Uint32;\r |
| 3add0205 ED |
2592 | ///\r |
| 2593 | /// All bit fields as a 64-bit value\r | |
| 2594 | ///\r | |
| 2f88bd3a | 2595 | UINT64 Uint64;\r |
| 3add0205 ED |
2596 | } MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER;\r |
| 2597 | \r | |
| 2598 | /**\r | |
| 2599 | Package. Ring Ratio Limit (R/W) This register provides Min/Max Ratio Limits\r | |
| 2600 | for the LLC and Ring.\r | |
| 2601 | \r | |
| 2602 | @param ECX MSR_SKYLAKE_RING_RATIO_LIMIT (0x00000620)\r | |
| 2603 | @param EAX Lower 32-bits of MSR value.\r | |
| 2604 | Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.\r | |
| 2605 | @param EDX Upper 32-bits of MSR value.\r | |
| 2606 | Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.\r | |
| 2607 | \r | |
| 2608 | <b>Example usage</b>\r | |
| 2609 | @code\r | |
| 2610 | MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER Msr;\r | |
| 2611 | \r | |
| 2612 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT);\r | |
| 2613 | AsmWriteMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT, Msr.Uint64);\r | |
| 2614 | @endcode\r | |
| 2615 | **/\r | |
| 2f88bd3a | 2616 | #define MSR_SKYLAKE_RING_RATIO_LIMIT 0x00000620\r |
| 3add0205 ED |
2617 | \r |
| 2618 | /**\r | |
| 2619 | MSR information returned for MSR index #MSR_SKYLAKE_RING_RATIO_LIMIT\r | |
| 2620 | **/\r | |
| 2621 | typedef union {\r | |
| 2622 | ///\r | |
| 2623 | /// Individual bit fields\r | |
| 2624 | ///\r | |
| 2625 | struct {\r | |
| 2626 | ///\r | |
| 2627 | /// [Bits 6:0] MAX_Ratio This field is used to limit the max ratio of the\r | |
| 2628 | /// LLC/Ring.\r | |
| 2629 | ///\r | |
| 2f88bd3a MK |
2630 | UINT32 Fix_Me_1 : 7;\r |
| 2631 | UINT32 Reserved1 : 1;\r | |
| 3add0205 ED |
2632 | ///\r |
| 2633 | /// [Bits 14:8] MIN_Ratio Writing to this field controls the minimum\r | |
| 2634 | /// possible ratio of the LLC/Ring.\r | |
| 2635 | ///\r | |
| 2f88bd3a MK |
2636 | UINT32 Fix_Me_2 : 7;\r |
| 2637 | UINT32 Reserved2 : 17;\r | |
| 2638 | UINT32 Reserved3 : 32;\r | |
| 3add0205 ED |
2639 | } Bits;\r |
| 2640 | ///\r | |
| 2641 | /// All bit fields as a 32-bit value\r | |
| 2642 | ///\r | |
| 2f88bd3a | 2643 | UINT32 Uint32;\r |
| 3add0205 ED |
2644 | ///\r |
| 2645 | /// All bit fields as a 64-bit value\r | |
| 2646 | ///\r | |
| 2f88bd3a | 2647 | UINT64 Uint64;\r |
| 3add0205 ED |
2648 | } MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER;\r |
| 2649 | \r | |
| 3add0205 ED |
2650 | /**\r |
| 2651 | Branch Monitoring Global Control (R/W).\r | |
| 2652 | \r | |
| 2653 | @param ECX MSR_SKYLAKE_BR_DETECT_CTRL (0x00000350)\r | |
| 2654 | @param EAX Lower 32-bits of MSR value.\r | |
| 2655 | Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.\r | |
| 2656 | @param EDX Upper 32-bits of MSR value.\r | |
| 2657 | Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.\r | |
| 2658 | \r | |
| 2659 | <b>Example usage</b>\r | |
| 2660 | @code\r | |
| 2661 | MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER Msr;\r | |
| 2662 | \r | |
| 2663 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL);\r | |
| 2664 | AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL, Msr.Uint64);\r | |
| 2665 | @endcode\r | |
| 2666 | **/\r | |
| 2f88bd3a | 2667 | #define MSR_SKYLAKE_BR_DETECT_CTRL 0x00000350\r |
| 3add0205 ED |
2668 | \r |
| 2669 | /**\r | |
| 2670 | MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_CTRL\r | |
| 2671 | **/\r | |
| 2672 | typedef union {\r | |
| 2673 | ///\r | |
| 2674 | /// Individual bit fields\r | |
| 2675 | ///\r | |
| 2676 | struct {\r | |
| 2677 | ///\r | |
| 2678 | /// [Bit 0] EnMonitoring Global enable for branch monitoring.\r | |
| 2679 | ///\r | |
| 2f88bd3a | 2680 | UINT32 EnMonitoring : 1;\r |
| 3add0205 ED |
2681 | ///\r |
| 2682 | /// [Bit 1] EnExcept Enable branch monitoring event signaling on threshold\r | |
| 2683 | /// trip. The branch monitoring event handler is signaled via the existing\r | |
| 2684 | /// PMI signaling mechanism as programmed from the corresponding local\r | |
| 2685 | /// APIC LVT entry.\r | |
| 2686 | ///\r | |
| 2f88bd3a | 2687 | UINT32 EnExcept : 1;\r |
| 3add0205 ED |
2688 | ///\r |
| 2689 | /// [Bit 2] EnLBRFrz Enable LBR freeze on threshold trip. This will cause\r | |
| 2690 | /// the LBR frozen bit 58 to be set in IA32_PERF_GLOBAL_STATUS when a\r | |
| 2691 | /// triggering condition occurs and this bit is enabled.\r | |
| 2692 | ///\r | |
| 2f88bd3a | 2693 | UINT32 EnLBRFrz : 1;\r |
| 3add0205 ED |
2694 | ///\r |
| 2695 | /// [Bit 3] DisableInGuest When set to '1', branch monitoring, event\r | |
| 2696 | /// triggering and LBR freeze actions are disabled when operating at VMX\r | |
| 2697 | /// non-root operation.\r | |
| 2698 | ///\r | |
| 2f88bd3a MK |
2699 | UINT32 DisableInGuest : 1;\r |
| 2700 | UINT32 Reserved1 : 4;\r | |
| 3add0205 ED |
2701 | ///\r |
| 2702 | /// [Bits 17:8] WindowSize Window size defined by WindowCntSel. Values 0 -\r | |
| 2703 | /// 1023 are supported. Once the Window counter reaches the WindowSize\r | |
| 2704 | /// count both the Window Counter and all Branch Monitoring Counters are\r | |
| 2705 | /// cleared.\r | |
| 2706 | ///\r | |
| 2f88bd3a MK |
2707 | UINT32 WindowSize : 10;\r |
| 2708 | UINT32 Reserved2 : 6;\r | |
| 3add0205 ED |
2709 | ///\r |
| 2710 | /// [Bits 25:24] WindowCntSel Window event count select: '00 =\r | |
| 2711 | /// Instructions retired. '01 = Branch instructions retired '10 = Return\r | |
| 2712 | /// instructions retired. '11 = Indirect branch instructions retired.\r | |
| 2713 | ///\r | |
| 2f88bd3a | 2714 | UINT32 WindowCntSel : 2;\r |
| 3add0205 ED |
2715 | ///\r |
| 2716 | /// [Bit 26] CntAndMode When set to '1', the overall branch monitoring\r | |
| 2717 | /// event triggering condition is true only if all enabled counters'\r | |
| 2718 | /// threshold conditions are true. When '0', the threshold tripping\r | |
| 2719 | /// condition is true if any enabled counters' threshold is true.\r | |
| 2720 | ///\r | |
| 2f88bd3a MK |
2721 | UINT32 CntAndMode : 1;\r |
| 2722 | UINT32 Reserved3 : 5;\r | |
| 2723 | UINT32 Reserved4 : 32;\r | |
| 3add0205 ED |
2724 | } Bits;\r |
| 2725 | ///\r | |
| 2726 | /// All bit fields as a 32-bit value\r | |
| 2727 | ///\r | |
| 2f88bd3a | 2728 | UINT32 Uint32;\r |
| 3add0205 ED |
2729 | ///\r |
| 2730 | /// All bit fields as a 64-bit value\r | |
| 2731 | ///\r | |
| 2f88bd3a | 2732 | UINT64 Uint64;\r |
| 3add0205 ED |
2733 | } MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER;\r |
| 2734 | \r | |
| 2735 | /**\r | |
| 2736 | Branch Monitoring Global Status (R/W).\r | |
| 2737 | \r | |
| 2738 | @param ECX MSR_SKYLAKE_BR_DETECT_STATUS (0x00000351)\r | |
| 2739 | @param EAX Lower 32-bits of MSR value.\r | |
| 2740 | Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.\r | |
| 2741 | @param EDX Upper 32-bits of MSR value.\r | |
| 2742 | Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.\r | |
| 2743 | \r | |
| 2744 | <b>Example usage</b>\r | |
| 2745 | @code\r | |
| 2746 | MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER Msr;\r | |
| 2747 | \r | |
| 2748 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS);\r | |
| 2749 | AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS, Msr.Uint64);\r | |
| 2750 | @endcode\r | |
| 2751 | **/\r | |
| 2f88bd3a | 2752 | #define MSR_SKYLAKE_BR_DETECT_STATUS 0x00000351\r |
| 3add0205 ED |
2753 | \r |
| 2754 | /**\r | |
| 2755 | MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_STATUS\r | |
| 2756 | **/\r | |
| 2757 | typedef union {\r | |
| 2758 | ///\r | |
| 2759 | /// Individual bit fields\r | |
| 2760 | ///\r | |
| 2761 | struct {\r | |
| 2762 | ///\r | |
| 2763 | /// [Bit 0] Branch Monitoring Event Signaled When set to '1', Branch\r | |
| 2764 | /// Monitoring event signaling is blocked until this bit is cleared by\r | |
| 2765 | /// software.\r | |
| 2766 | ///\r | |
| 2f88bd3a | 2767 | UINT32 BranchMonitoringEventSignaled : 1;\r |
| 3add0205 ED |
2768 | ///\r |
| 2769 | /// [Bit 1] LBRsValid This status bit is set to '1' if the LBR state is\r | |
| 2770 | /// considered valid for sampling by branch monitoring software.\r | |
| 2771 | ///\r | |
| 2f88bd3a MK |
2772 | UINT32 LBRsValid : 1;\r |
| 2773 | UINT32 Reserved1 : 6;\r | |
| 3add0205 ED |
2774 | ///\r |
| 2775 | /// [Bit 8] CntrHit0 Branch monitoring counter #0 threshold hit. This\r | |
| 2776 | /// status bit is sticky and once set requires clearing by software.\r | |
| 2777 | /// Counter operation continues independent of the state of the bit.\r | |
| 2778 | ///\r | |
| 2f88bd3a | 2779 | UINT32 CntrHit0 : 1;\r |
| 3add0205 ED |
2780 | ///\r |
| 2781 | /// [Bit 9] CntrHit1 Branch monitoring counter #1 threshold hit. This\r | |
| 2782 | /// status bit is sticky and once set requires clearing by software.\r | |
| 2783 | /// Counter operation continues independent of the state of the bit.\r | |
| 2784 | ///\r | |
| 2f88bd3a MK |
2785 | UINT32 CntrHit1 : 1;\r |
| 2786 | UINT32 Reserved2 : 6;\r | |
| 3add0205 ED |
2787 | ///\r |
| 2788 | /// [Bits 25:16] CountWindow The current value of the window counter. The\r | |
| 2789 | /// count value is frozen on a valid branch monitoring triggering\r | |
| 2790 | /// condition. This is a 10-bit unsigned value.\r | |
| 2791 | ///\r | |
| 2f88bd3a MK |
2792 | UINT32 CountWindow : 10;\r |
| 2793 | UINT32 Reserved3 : 6;\r | |
| 3add0205 ED |
2794 | ///\r |
| 2795 | /// [Bits 39:32] Count0 The current value of counter 0 updated after each\r | |
| 2796 | /// occurrence of the event being counted. The count value is frozen on a\r | |
| 2797 | /// valid branch monitoring triggering condition (in which case CntrHit0\r | |
| 2798 | /// will also be set). This is an 8-bit signed value (2's complement).\r | |
| 2799 | /// Heuristic events which only increment will saturate and freeze at\r | |
| 2800 | /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum\r | |
| 2801 | /// value 0x7F (+127) and minimum value 0x80 (-128).\r | |
| 2802 | ///\r | |
| 2f88bd3a | 2803 | UINT32 Count0 : 8;\r |
| 3add0205 ED |
2804 | ///\r |
| 2805 | /// [Bits 47:40] Count1 The current value of counter 1 updated after each\r | |
| 2806 | /// occurrence of the event being counted. The count value is frozen on a\r | |
| 2807 | /// valid branch monitoring triggering condition (in which case CntrHit1\r | |
| 2808 | /// will also be set). This is an 8-bit signed value (2's complement).\r | |
| 2809 | /// Heuristic events which only increment will saturate and freeze at\r | |
| 2810 | /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum\r | |
| 2811 | /// value 0x7F (+127) and minimum value 0x80 (-128).\r | |
| 2812 | ///\r | |
| 2f88bd3a MK |
2813 | UINT32 Count1 : 8;\r |
| 2814 | UINT32 Reserved4 : 16;\r | |
| 3add0205 ED |
2815 | } Bits;\r |
| 2816 | ///\r | |
| 2817 | /// All bit fields as a 32-bit value\r | |
| 2818 | ///\r | |
| 2f88bd3a | 2819 | UINT32 Uint32;\r |
| 3add0205 ED |
2820 | ///\r |
| 2821 | /// All bit fields as a 64-bit value\r | |
| 2822 | ///\r | |
| 2f88bd3a | 2823 | UINT64 Uint64;\r |
| 3add0205 ED |
2824 | } MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER;\r |
| 2825 | \r | |
| 3add0205 ED |
2826 | /**\r |
| 2827 | Package. Package C3 Residency Counter (R/O). Note: C-state values are\r | |
| 2828 | processor specific C-state code names, unrelated to MWAIT extension C-state\r | |
| 2829 | parameters or ACPI C-states.\r | |
| 2830 | \r | |
| 2831 | @param ECX MSR_SKYLAKE_PKG_C3_RESIDENCY (0x000003F8)\r | |
| 2832 | @param EAX Lower 32-bits of MSR value.\r | |
| 2833 | @param EDX Upper 32-bits of MSR value.\r | |
| 2834 | \r | |
| 2835 | <b>Example usage</b>\r | |
| 2836 | @code\r | |
| 2837 | UINT64 Msr;\r | |
| 2838 | \r | |
| 2839 | Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_C3_RESIDENCY);\r | |
| 2840 | @endcode\r | |
| 2841 | **/\r | |
| 2f88bd3a | 2842 | #define MSR_SKYLAKE_PKG_C3_RESIDENCY 0x000003F8\r |
| 3add0205 ED |
2843 | \r |
| 2844 | /**\r | |
| 2845 | Core. Core C1 Residency Counter (R/O). Value since last reset for the Core\r | |
| 2846 | C1 residency. Counter rate is the Max Non-Turbo frequency (same as TSC).\r | |
| 2847 | This counter counts in case both of the core's threads are in an idle state\r | |
| 2848 | and at least one of the core's thread residency is in a C1 state or in one\r | |
| 2849 | of its sub states. The counter is updated only after a core C state exit.\r | |
| 2850 | Note: Always reads 0 if core C1 is unsupported. A value of zero indicates\r | |
| 2851 | that this processor does not support core C1 or never entered core C1 level\r | |
| 2852 | state.\r | |
| 2853 | \r | |
| 2854 | @param ECX MSR_SKYLAKE_CORE_C1_RESIDENCY (0x00000660)\r | |
| 2855 | @param EAX Lower 32-bits of MSR value.\r | |
| 2856 | @param EDX Upper 32-bits of MSR value.\r | |
| 2857 | \r | |
| 2858 | <b>Example usage</b>\r | |
| 2859 | @code\r | |
| 2860 | UINT64 Msr;\r | |
| 2861 | \r | |
| 2862 | Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C1_RESIDENCY);\r | |
| 2863 | @endcode\r | |
| 2864 | **/\r | |
| 2f88bd3a | 2865 | #define MSR_SKYLAKE_CORE_C1_RESIDENCY 0x00000660\r |
| 3add0205 ED |
2866 | \r |
| 2867 | /**\r | |
| 2868 | Core. Core C3 Residency Counter (R/O). Will always return 0.\r | |
| 2869 | \r | |
| 2870 | @param ECX MSR_SKYLAKE_CORE_C3_RESIDENCY (0x00000662)\r | |
| 2871 | @param EAX Lower 32-bits of MSR value.\r | |
| 2872 | @param EDX Upper 32-bits of MSR value.\r | |
| 2873 | \r | |
| 2874 | <b>Example usage</b>\r | |
| 2875 | @code\r | |
| 2876 | UINT64 Msr;\r | |
| 2877 | \r | |
| 2878 | Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C3_RESIDENCY);\r | |
| 2879 | @endcode\r | |
| 2880 | **/\r | |
| 2f88bd3a | 2881 | #define MSR_SKYLAKE_CORE_C3_RESIDENCY 0x00000662\r |
| 3add0205 ED |
2882 | \r |
| 2883 | /**\r | |
| 2884 | Package. Protected Processor Inventory Number Enable Control (R/W).\r | |
| 2885 | \r | |
| 2886 | @param ECX MSR_SKYLAKE_PPIN_CTL (0x0000004E)\r | |
| 2887 | @param EAX Lower 32-bits of MSR value.\r | |
| 2888 | Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.\r | |
| 2889 | @param EDX Upper 32-bits of MSR value.\r | |
| 2890 | Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.\r | |
| 2891 | \r | |
| 2892 | <b>Example usage</b>\r | |
| 2893 | @code\r | |
| 2894 | MSR_SKYLAKE_PPIN_CTL_REGISTER Msr;\r | |
| 2895 | \r | |
| 2896 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PPIN_CTL);\r | |
| 2897 | AsmWriteMsr64 (MSR_SKYLAKE_PPIN_CTL, Msr.Uint64);\r | |
| 2898 | @endcode\r | |
| 2899 | **/\r | |
| 2f88bd3a | 2900 | #define MSR_SKYLAKE_PPIN_CTL 0x0000004E\r |
| 3add0205 ED |
2901 | \r |
| 2902 | /**\r | |
| 2903 | MSR information returned for MSR index #MSR_SKYLAKE_PPIN_CTL\r | |
| 2904 | **/\r | |
| 2905 | typedef union {\r | |
| 2906 | ///\r | |
| 2907 | /// Individual bit fields\r | |
| 2908 | ///\r | |
| 2909 | struct {\r | |
| 2910 | ///\r | |
| 2911 | /// [Bit 0] LockOut (R/WO) See Table 2-25.\r | |
| 2912 | ///\r | |
| 2f88bd3a | 2913 | UINT32 LockOut : 1;\r |
| 3add0205 ED |
2914 | ///\r |
| 2915 | /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.\r | |
| 2916 | ///\r | |
| 2f88bd3a MK |
2917 | UINT32 Enable_PPIN : 1;\r |
| 2918 | UINT32 Reserved1 : 30;\r | |
| 2919 | UINT32 Reserved2 : 32;\r | |
| 3add0205 ED |
2920 | } Bits;\r |
| 2921 | ///\r | |
| 2922 | /// All bit fields as a 32-bit value\r | |
| 2923 | ///\r | |
| 2f88bd3a | 2924 | UINT32 Uint32;\r |
| 3add0205 ED |
2925 | ///\r |
| 2926 | /// All bit fields as a 64-bit value\r | |
| 2927 | ///\r | |
| 2f88bd3a | 2928 | UINT64 Uint64;\r |
| 3add0205 ED |
2929 | } MSR_SKYLAKE_PPIN_CTL_REGISTER;\r |
| 2930 | \r | |
| 3add0205 ED |
2931 | /**\r |
| 2932 | Package. Protected Processor Inventory Number (R/O). Protected Processor\r | |
| 2933 | Inventory Number (R/O) See Table 2-25.\r | |
| 2934 | \r | |
| 2935 | @param ECX MSR_SKYLAKE_PPIN (0x0000004F)\r | |
| 2936 | @param EAX Lower 32-bits of MSR value.\r | |
| 2937 | @param EDX Upper 32-bits of MSR value.\r | |
| 2938 | \r | |
| 2939 | <b>Example usage</b>\r | |
| 2940 | @code\r | |
| 2941 | UINT64 Msr;\r | |
| 2942 | \r | |
| 2943 | Msr = AsmReadMsr64 (MSR_SKYLAKE_PPIN);\r | |
| 2944 | @endcode\r | |
| 2945 | **/\r | |
| 2f88bd3a | 2946 | #define MSR_SKYLAKE_PPIN 0x0000004F\r |
| 3add0205 ED |
2947 | \r |
| 2948 | /**\r | |
| 2949 | Package. Platform Information Contains power management and other model\r | |
| 2950 | specific features enumeration. See http://biosbits.org.\r | |
| 2951 | \r | |
| 2952 | @param ECX MSR_SKYLAKE_PLATFORM_INFO (0x000000CE)\r | |
| 2953 | @param EAX Lower 32-bits of MSR value.\r | |
| 2954 | Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.\r | |
| 2955 | @param EDX Upper 32-bits of MSR value.\r | |
| 2956 | Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.\r | |
| 2957 | \r | |
| 2958 | <b>Example usage</b>\r | |
| 2959 | @code\r | |
| 2960 | MSR_SKYLAKE_PLATFORM_INFO_REGISTER Msr;\r | |
| 2961 | \r | |
| 2962 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_INFO);\r | |
| 2963 | AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_INFO, Msr.Uint64);\r | |
| 2964 | @endcode\r | |
| 2965 | **/\r | |
| 2f88bd3a | 2966 | #define MSR_SKYLAKE_PLATFORM_INFO 0x000000CE\r |
| 3add0205 ED |
2967 | \r |
| 2968 | /**\r | |
| 2969 | MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_INFO\r | |
| 2970 | **/\r | |
| 2971 | typedef union {\r | |
| 2972 | ///\r | |
| 2973 | /// Individual bit fields\r | |
| 2974 | ///\r | |
| 2975 | struct {\r | |
| 2f88bd3a | 2976 | UINT32 Reserved1 : 8;\r |
| 3add0205 ED |
2977 | ///\r |
| 2978 | /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.\r | |
| 2979 | ///\r | |
| 2f88bd3a MK |
2980 | UINT32 MaximumNon_TurboRatio : 8;\r |
| 2981 | UINT32 Reserved2 : 7;\r | |
| 3add0205 ED |
2982 | ///\r |
| 2983 | /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.\r | |
| 2984 | ///\r | |
| 2f88bd3a MK |
2985 | UINT32 PPIN_CAP : 1;\r |
| 2986 | UINT32 Reserved3 : 4;\r | |
| 3add0205 ED |
2987 | ///\r |
| 2988 | /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See\r | |
| 2989 | /// Table 2-25.\r | |
| 2990 | ///\r | |
| 2f88bd3a | 2991 | UINT32 ProgrammableRatioLimit : 1;\r |
| 3add0205 ED |
2992 | ///\r |
| 2993 | /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See\r | |
| 2994 | /// Table 2-25.\r | |
| 2995 | ///\r | |
| 2f88bd3a | 2996 | UINT32 ProgrammableTDPLimit : 1;\r |
| 3add0205 ED |
2997 | ///\r |
| 2998 | /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.\r | |
| 2999 | ///\r | |
| 2f88bd3a MK |
3000 | UINT32 ProgrammableTJOFFSET : 1;\r |
| 3001 | UINT32 Reserved4 : 1;\r | |
| 3002 | UINT32 Reserved5 : 8;\r | |
| 3add0205 ED |
3003 | ///\r |
| 3004 | /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.\r | |
| 3005 | ///\r | |
| 2f88bd3a MK |
3006 | UINT32 MaximumEfficiencyRatio : 8;\r |
| 3007 | UINT32 Reserved6 : 16;\r | |
| 3add0205 ED |
3008 | } Bits;\r |
| 3009 | ///\r | |
| 3010 | /// All bit fields as a 64-bit value\r | |
| 3011 | ///\r | |
| 2f88bd3a | 3012 | UINT64 Uint64;\r |
| 3add0205 ED |
3013 | } MSR_SKYLAKE_PLATFORM_INFO_REGISTER;\r |
| 3014 | \r | |
| 3add0205 ED |
3015 | /**\r |
| 3016 | Core. C-State Configuration Control (R/W) Note: C-state values are processor\r | |
| 3017 | specific C-state code names, unrelated to MWAIT extension C-state parameters\r | |
| 3018 | or ACPI C-states. `See http://biosbits.org. <http://biosbits.org/>`__.\r | |
| 3019 | \r | |
| 3020 | @param ECX MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL (0x000000E2)\r | |
| 3021 | @param EAX Lower 32-bits of MSR value.\r | |
| 3022 | Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 3023 | @param EDX Upper 32-bits of MSR value.\r | |
| 3024 | Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 3025 | \r | |
| 3026 | <b>Example usage</b>\r | |
| 3027 | @code\r | |
| 3028 | MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r | |
| 3029 | \r | |
| 3030 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL);\r | |
| 3031 | AsmWriteMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r | |
| 3032 | @endcode\r | |
| 3033 | **/\r | |
| 2f88bd3a | 3034 | #define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL 0x000000E2\r |
| 3add0205 ED |
3035 | \r |
| 3036 | /**\r | |
| 3037 | MSR information returned for MSR index #MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL\r | |
| 3038 | **/\r | |
| 3039 | typedef union {\r | |
| 3040 | ///\r | |
| 3041 | /// Individual bit fields\r | |
| 3042 | ///\r | |
| 3043 | struct {\r | |
| 3044 | ///\r | |
| 3045 | /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r | |
| 3046 | /// processor-specific C-state code name (consuming the least power) for\r | |
| 3047 | /// the package. The default is set as factory-configured package Cstate\r | |
| 3048 | /// limit. The following C-state code name encodings are supported: 000b:\r | |
| 3049 | /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)\r | |
| 3050 | /// 011b: C6 (retention) 111b: No Package C state limits. All C states\r | |
| 3051 | /// supported by the processor are available.\r | |
| 3052 | ///\r | |
| 2f88bd3a MK |
3053 | UINT32 C_StateLimit : 3;\r |
| 3054 | UINT32 Reserved1 : 7;\r | |
| 3add0205 ED |
3055 | ///\r |
| 3056 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r | |
| 3057 | ///\r | |
| 2f88bd3a MK |
3058 | UINT32 MWAITRedirectionEnable : 1;\r |
| 3059 | UINT32 Reserved2 : 4;\r | |
| 3add0205 ED |
3060 | ///\r |
| 3061 | /// [Bit 15] CFG Lock (R/WO).\r | |
| 3062 | ///\r | |
| 2f88bd3a | 3063 | UINT32 CFGLock : 1;\r |
| 3add0205 ED |
3064 | ///\r |
| 3065 | /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor\r | |
| 3066 | /// will convert HALT or MWAT(C1) to MWAIT(C6).\r | |
| 3067 | ///\r | |
| 2f88bd3a MK |
3068 | UINT32 AutomaticC_StateConversionEnable : 1;\r |
| 3069 | UINT32 Reserved3 : 8;\r | |
| 3add0205 ED |
3070 | ///\r |
| 3071 | /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r | |
| 3072 | ///\r | |
| 2f88bd3a | 3073 | UINT32 C3StateAutoDemotionEnable : 1;\r |
| 3add0205 ED |
3074 | ///\r |
| 3075 | /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r | |
| 3076 | ///\r | |
| 2f88bd3a | 3077 | UINT32 C1StateAutoDemotionEnable : 1;\r |
| 3add0205 ED |
3078 | ///\r |
| 3079 | /// [Bit 27] Enable C3 Undemotion (R/W).\r | |
| 3080 | ///\r | |
| 2f88bd3a | 3081 | UINT32 EnableC3Undemotion : 1;\r |
| 3add0205 ED |
3082 | ///\r |
| 3083 | /// [Bit 28] Enable C1 Undemotion (R/W).\r | |
| 3084 | ///\r | |
| 2f88bd3a | 3085 | UINT32 EnableC1Undemotion : 1;\r |
| 3add0205 ED |
3086 | ///\r |
| 3087 | /// [Bit 29] Package C State Demotion Enable (R/W).\r | |
| 3088 | ///\r | |
| 2f88bd3a | 3089 | UINT32 CStateDemotionEnable : 1;\r |
| 3add0205 ED |
3090 | ///\r |
| 3091 | /// [Bit 30] Package C State UnDemotion Enable (R/W).\r | |
| 3092 | ///\r | |
| 2f88bd3a MK |
3093 | UINT32 CStateUnDemotionEnable : 1;\r |
| 3094 | UINT32 Reserved4 : 1;\r | |
| 3095 | UINT32 Reserved5 : 32;\r | |
| 3add0205 ED |
3096 | } Bits;\r |
| 3097 | ///\r | |
| 3098 | /// All bit fields as a 32-bit value\r | |
| 3099 | ///\r | |
| 2f88bd3a | 3100 | UINT32 Uint32;\r |
| 3add0205 ED |
3101 | ///\r |
| 3102 | /// All bit fields as a 64-bit value\r | |
| 3103 | ///\r | |
| 2f88bd3a | 3104 | UINT64 Uint64;\r |
| 3add0205 ED |
3105 | } MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER;\r |
| 3106 | \r | |
| 3add0205 ED |
3107 | /**\r |
| 3108 | Thread. Global Machine Check Capability (R/O).\r | |
| 3109 | \r | |
| 3110 | @param ECX MSR_SKYLAKE_IA32_MCG_CAP (0x00000179)\r | |
| 3111 | @param EAX Lower 32-bits of MSR value.\r | |
| 3112 | Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.\r | |
| 3113 | @param EDX Upper 32-bits of MSR value.\r | |
| 3114 | Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.\r | |
| 3115 | \r | |
| 3116 | <b>Example usage</b>\r | |
| 3117 | @code\r | |
| 3118 | MSR_SKYLAKE_IA32_MCG_CAP_REGISTER Msr;\r | |
| 3119 | \r | |
| 3120 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_MCG_CAP);\r | |
| 3121 | @endcode\r | |
| 3122 | **/\r | |
| 2f88bd3a | 3123 | #define MSR_SKYLAKE_IA32_MCG_CAP 0x00000179\r |
| 3add0205 ED |
3124 | \r |
| 3125 | /**\r | |
| 3126 | MSR information returned for MSR index #MSR_SKYLAKE_IA32_MCG_CAP\r | |
| 3127 | **/\r | |
| 3128 | typedef union {\r | |
| 3129 | ///\r | |
| 3130 | /// Individual bit fields\r | |
| 3131 | ///\r | |
| 3132 | struct {\r | |
| 3133 | ///\r | |
| 3134 | /// [Bits 7:0] Count.\r | |
| 3135 | ///\r | |
| 2f88bd3a | 3136 | UINT32 Count : 8;\r |
| 3add0205 ED |
3137 | ///\r |
| 3138 | /// [Bit 8] MCG_CTL_P.\r | |
| 3139 | ///\r | |
| 2f88bd3a | 3140 | UINT32 MCG_CTL_P : 1;\r |
| 3add0205 ED |
3141 | ///\r |
| 3142 | /// [Bit 9] MCG_EXT_P.\r | |
| 3143 | ///\r | |
| 2f88bd3a | 3144 | UINT32 MCG_EXT_P : 1;\r |
| 3add0205 ED |
3145 | ///\r |
| 3146 | /// [Bit 10] MCP_CMCI_P.\r | |
| 3147 | ///\r | |
| 2f88bd3a | 3148 | UINT32 MCP_CMCI_P : 1;\r |
| 3add0205 ED |
3149 | ///\r |
| 3150 | /// [Bit 11] MCG_TES_P.\r | |
| 3151 | ///\r | |
| 2f88bd3a MK |
3152 | UINT32 MCG_TES_P : 1;\r |
| 3153 | UINT32 Reserved1 : 4;\r | |
| 3add0205 ED |
3154 | ///\r |
| 3155 | /// [Bits 23:16] MCG_EXT_CNT.\r | |
| 3156 | ///\r | |
| 2f88bd3a | 3157 | UINT32 MCG_EXT_CNT : 8;\r |
| 3add0205 ED |
3158 | ///\r |
| 3159 | /// [Bit 24] MCG_SER_P.\r | |
| 3160 | ///\r | |
| 2f88bd3a | 3161 | UINT32 MCG_SER_P : 1;\r |
| 3add0205 ED |
3162 | ///\r |
| 3163 | /// [Bit 25] MCG_EM_P.\r | |
| 3164 | ///\r | |
| 2f88bd3a | 3165 | UINT32 MCG_EM_P : 1;\r |
| 3add0205 ED |
3166 | ///\r |
| 3167 | /// [Bit 26] MCG_ELOG_P.\r | |
| 3168 | ///\r | |
| 2f88bd3a MK |
3169 | UINT32 MCG_ELOG_P : 1;\r |
| 3170 | UINT32 Reserved2 : 5;\r | |
| 3171 | UINT32 Reserved3 : 32;\r | |
| 3add0205 ED |
3172 | } Bits;\r |
| 3173 | ///\r | |
| 3174 | /// All bit fields as a 32-bit value\r | |
| 3175 | ///\r | |
| 2f88bd3a | 3176 | UINT32 Uint32;\r |
| 3add0205 ED |
3177 | ///\r |
| 3178 | /// All bit fields as a 64-bit value\r | |
| 3179 | ///\r | |
| 2f88bd3a | 3180 | UINT64 Uint64;\r |
| 3add0205 ED |
3181 | } MSR_SKYLAKE_IA32_MCG_CAP_REGISTER;\r |
| 3182 | \r | |
| 3add0205 ED |
3183 | /**\r |
| 3184 | THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r | |
| 3185 | Enhancement. Accessible only while in SMM.\r | |
| 3186 | \r | |
| 3187 | @param ECX MSR_SKYLAKE_SMM_MCA_CAP (0x0000017D)\r | |
| 3188 | @param EAX Lower 32-bits of MSR value.\r | |
| 3189 | Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.\r | |
| 3190 | @param EDX Upper 32-bits of MSR value.\r | |
| 3191 | Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.\r | |
| 3192 | \r | |
| 3193 | <b>Example usage</b>\r | |
| 3194 | @code\r | |
| 3195 | MSR_SKYLAKE_SMM_MCA_CAP_REGISTER Msr;\r | |
| 3196 | \r | |
| 3197 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_SMM_MCA_CAP);\r | |
| 3198 | AsmWriteMsr64 (MSR_SKYLAKE_SMM_MCA_CAP, Msr.Uint64);\r | |
| 3199 | @endcode\r | |
| 3200 | **/\r | |
| 2f88bd3a | 3201 | #define MSR_SKYLAKE_SMM_MCA_CAP 0x0000017D\r |
| 3add0205 ED |
3202 | \r |
| 3203 | /**\r | |
| 3204 | MSR information returned for MSR index #MSR_SKYLAKE_SMM_MCA_CAP\r | |
| 3205 | **/\r | |
| 3206 | typedef union {\r | |
| 3207 | ///\r | |
| 3208 | /// Individual bit fields\r | |
| 3209 | ///\r | |
| 3210 | struct {\r | |
| 2f88bd3a MK |
3211 | UINT32 Reserved1 : 32;\r |
| 3212 | UINT32 Reserved2 : 26;\r | |
| 3add0205 ED |
3213 | ///\r |
| 3214 | /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r | |
| 3215 | /// SMM code access restriction is supported and a host-space interface is\r | |
| 3216 | /// available to SMM handler.\r | |
| 3217 | ///\r | |
| 2f88bd3a | 3218 | UINT32 SMM_Code_Access_Chk : 1;\r |
| 3add0205 ED |
3219 | ///\r |
| 3220 | /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r | |
| 3221 | /// SMM long flow indicator is supported and a host-space interface is\r | |
| 3222 | /// available to SMM handler.\r | |
| 3223 | ///\r | |
| 2f88bd3a MK |
3224 | UINT32 Long_Flow_Indication : 1;\r |
| 3225 | UINT32 Reserved3 : 4;\r | |
| 3add0205 ED |
3226 | } Bits;\r |
| 3227 | ///\r | |
| 3228 | /// All bit fields as a 64-bit value\r | |
| 3229 | ///\r | |
| 2f88bd3a | 3230 | UINT64 Uint64;\r |
| 3add0205 ED |
3231 | } MSR_SKYLAKE_SMM_MCA_CAP_REGISTER;\r |
| 3232 | \r | |
| 3add0205 ED |
3233 | /**\r |
| 3234 | Package. Temperature Target.\r | |
| 3235 | \r | |
| 3236 | @param ECX MSR_SKYLAKE_TEMPERATURE_TARGET (0x000001A2)\r | |
| 3237 | @param EAX Lower 32-bits of MSR value.\r | |
| 3238 | Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.\r | |
| 3239 | @param EDX Upper 32-bits of MSR value.\r | |
| 3240 | Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.\r | |
| 3241 | \r | |
| 3242 | <b>Example usage</b>\r | |
| 3243 | @code\r | |
| 3244 | MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER Msr;\r | |
| 3245 | \r | |
| 3246 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET);\r | |
| 3247 | AsmWriteMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET, Msr.Uint64);\r | |
| 3248 | @endcode\r | |
| 3249 | **/\r | |
| 2f88bd3a | 3250 | #define MSR_SKYLAKE_TEMPERATURE_TARGET 0x000001A2\r |
| 3add0205 ED |
3251 | \r |
| 3252 | /**\r | |
| 3253 | MSR information returned for MSR index #MSR_SKYLAKE_TEMPERATURE_TARGET\r | |
| 3254 | **/\r | |
| 3255 | typedef union {\r | |
| 3256 | ///\r | |
| 3257 | /// Individual bit fields\r | |
| 3258 | ///\r | |
| 3259 | struct {\r | |
| 2f88bd3a | 3260 | UINT32 Reserved1 : 16;\r |
| 3add0205 ED |
3261 | ///\r |
| 3262 | /// [Bits 23:16] Temperature Target (RO) See Table 2-25.\r | |
| 3263 | ///\r | |
| 2f88bd3a | 3264 | UINT32 TemperatureTarget : 8;\r |
| 3add0205 ED |
3265 | ///\r |
| 3266 | /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.\r | |
| 3267 | ///\r | |
| 2f88bd3a MK |
3268 | UINT32 TCCActivationOffset : 4;\r |
| 3269 | UINT32 Reserved2 : 4;\r | |
| 3270 | UINT32 Reserved3 : 32;\r | |
| 3add0205 ED |
3271 | } Bits;\r |
| 3272 | ///\r | |
| 3273 | /// All bit fields as a 32-bit value\r | |
| 3274 | ///\r | |
| 2f88bd3a | 3275 | UINT32 Uint32;\r |
| 3add0205 ED |
3276 | ///\r |
| 3277 | /// All bit fields as a 64-bit value\r | |
| 3278 | ///\r | |
| 2f88bd3a | 3279 | UINT64 Uint64;\r |
| 3add0205 ED |
3280 | } MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER;\r |
| 3281 | \r | |
| 3282 | /**\r | |
| 3283 | Package. This register defines the active core ranges for each frequency\r | |
| 3284 | point. NUMCORE[0:7] must be populated in ascending order. NUMCORE[i+1] must\r | |
| 3285 | be greater than NUMCORE[i]. Entries with NUMCORE[i] == 0 will be ignored.\r | |
| 3286 | The last valid entry must have NUMCORE >= the number of cores in the SKU. If\r | |
| 3287 | any of the rules above are broken, the configuration is silently rejected.\r | |
| 3288 | \r | |
| 3289 | @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES (0x000001AE)\r | |
| 3290 | @param EAX Lower 32-bits of MSR value.\r | |
| 3291 | Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.\r | |
| 3292 | @param EDX Upper 32-bits of MSR value.\r | |
| 3293 | Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.\r | |
| 3294 | \r | |
| 3295 | <b>Example usage</b>\r | |
| 3296 | @code\r | |
| 3297 | MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER Msr;\r | |
| 3298 | \r | |
| 3299 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES);\r | |
| 3300 | AsmWriteMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES, Msr.Uint64);\r | |
| 3301 | @endcode\r | |
| 3302 | **/\r | |
| 2f88bd3a | 3303 | #define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES 0x000001AE\r |
| 3add0205 ED |
3304 | \r |
| 3305 | /**\r | |
| 3306 | MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES\r | |
| 3307 | **/\r | |
| 3308 | typedef union {\r | |
| 3309 | ///\r | |
| 3310 | /// Individual bit fields\r | |
| 3311 | ///\r | |
| 3312 | struct {\r | |
| 3313 | ///\r | |
| 3314 | /// [Bits 7:0] NUMCORE_0 Defines the active core ranges for each frequency\r | |
| 3315 | /// point.\r | |
| 3316 | ///\r | |
| 2f88bd3a | 3317 | UINT32 NUMCORE_0 : 8;\r |
| 3add0205 ED |
3318 | ///\r |
| 3319 | /// [Bits 15:8] NUMCORE_1 Defines the active core ranges for each\r | |
| 3320 | /// frequency point.\r | |
| 3321 | ///\r | |
| 2f88bd3a | 3322 | UINT32 NUMCORE_1 : 8;\r |
| 3add0205 ED |
3323 | ///\r |
| 3324 | /// [Bits 23:16] NUMCORE_2 Defines the active core ranges for each\r | |
| 3325 | /// frequency point.\r | |
| 3326 | ///\r | |
| 2f88bd3a | 3327 | UINT32 NUMCORE_2 : 8;\r |
| 3add0205 ED |
3328 | ///\r |
| 3329 | /// [Bits 31:24] NUMCORE_3 Defines the active core ranges for each\r | |
| 3330 | /// frequency point.\r | |
| 3331 | ///\r | |
| 2f88bd3a | 3332 | UINT32 NUMCORE_3 : 8;\r |
| 3add0205 ED |
3333 | ///\r |
| 3334 | /// [Bits 39:32] NUMCORE_4 Defines the active core ranges for each\r | |
| 3335 | /// frequency point.\r | |
| 3336 | ///\r | |
| 2f88bd3a | 3337 | UINT32 NUMCORE_4 : 8;\r |
| 3add0205 ED |
3338 | ///\r |
| 3339 | /// [Bits 47:40] NUMCORE_5 Defines the active core ranges for each\r | |
| 3340 | /// frequency point.\r | |
| 3341 | ///\r | |
| 2f88bd3a | 3342 | UINT32 NUMCORE_5 : 8;\r |
| 3add0205 ED |
3343 | ///\r |
| 3344 | /// [Bits 55:48] NUMCORE_6 Defines the active core ranges for each\r | |
| 3345 | /// frequency point.\r | |
| 3346 | ///\r | |
| 2f88bd3a | 3347 | UINT32 NUMCORE_6 : 8;\r |
| 3add0205 ED |
3348 | ///\r |
| 3349 | /// [Bits 63:56] NUMCORE_7 Defines the active core ranges for each\r | |
| 3350 | /// frequency point.\r | |
| 3351 | ///\r | |
| 2f88bd3a | 3352 | UINT32 NUMCORE_7 : 8;\r |
| 3add0205 ED |
3353 | } Bits;\r |
| 3354 | ///\r | |
| 3355 | /// All bit fields as a 64-bit value\r | |
| 3356 | ///\r | |
| 2f88bd3a | 3357 | UINT64 Uint64;\r |
| 3add0205 ED |
3358 | } MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER;\r |
| 3359 | \r | |
| 3add0205 ED |
3360 | /**\r |
| 3361 | Package. Unit Multipliers Used in RAPL Interfaces (R/O).\r | |
| 3362 | \r | |
| 3363 | @param ECX MSR_SKYLAKE_RAPL_POWER_UNIT (0x00000606)\r | |
| 3364 | @param EAX Lower 32-bits of MSR value.\r | |
| 3365 | Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.\r | |
| 3366 | @param EDX Upper 32-bits of MSR value.\r | |
| 3367 | Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.\r | |
| 3368 | \r | |
| 3369 | <b>Example usage</b>\r | |
| 3370 | @code\r | |
| 3371 | MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER Msr;\r | |
| 3372 | \r | |
| 3373 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RAPL_POWER_UNIT);\r | |
| 3374 | @endcode\r | |
| 3375 | **/\r | |
| 2f88bd3a | 3376 | #define MSR_SKYLAKE_RAPL_POWER_UNIT 0x00000606\r |
| 3add0205 ED |
3377 | \r |
| 3378 | /**\r | |
| 3379 | MSR information returned for MSR index #MSR_SKYLAKE_RAPL_POWER_UNIT\r | |
| 3380 | **/\r | |
| 3381 | typedef union {\r | |
| 3382 | ///\r | |
| 3383 | /// Individual bit fields\r | |
| 3384 | ///\r | |
| 3385 | struct {\r | |
| 3386 | ///\r | |
| 3387 | /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r | |
| 3388 | ///\r | |
| 2f88bd3a MK |
3389 | UINT32 PowerUnits : 4;\r |
| 3390 | UINT32 Reserved1 : 4;\r | |
| 3add0205 ED |
3391 | ///\r |
| 3392 | /// [Bits 12:8] Package. Energy Status Units Energy related information\r | |
| 3393 | /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r | |
| 3394 | /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r | |
| 3395 | /// micro-joules).\r | |
| 3396 | ///\r | |
| 2f88bd3a MK |
3397 | UINT32 EnergyStatusUnits : 5;\r |
| 3398 | UINT32 Reserved2 : 3;\r | |
| 3add0205 ED |
3399 | ///\r |
| 3400 | /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r | |
| 3401 | /// Interfaces.".\r | |
| 3402 | ///\r | |
| 2f88bd3a MK |
3403 | UINT32 TimeUnits : 4;\r |
| 3404 | UINT32 Reserved3 : 12;\r | |
| 3405 | UINT32 Reserved4 : 32;\r | |
| 3add0205 ED |
3406 | } Bits;\r |
| 3407 | ///\r | |
| 3408 | /// All bit fields as a 32-bit value\r | |
| 3409 | ///\r | |
| 2f88bd3a | 3410 | UINT32 Uint32;\r |
| 3add0205 ED |
3411 | ///\r |
| 3412 | /// All bit fields as a 64-bit value\r | |
| 3413 | ///\r | |
| 2f88bd3a | 3414 | UINT64 Uint64;\r |
| 3add0205 ED |
3415 | } MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER;\r |
| 3416 | \r | |
| 3add0205 ED |
3417 | /**\r |
| 3418 | Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r | |
| 3419 | Domain.".\r | |
| 3420 | \r | |
| 3421 | @param ECX MSR_SKYLAKE_DRAM_POWER_LIMIT (0x00000618)\r | |
| 3422 | @param EAX Lower 32-bits of MSR value.\r | |
| 3423 | @param EDX Upper 32-bits of MSR value.\r | |
| 3424 | \r | |
| 3425 | <b>Example usage</b>\r | |
| 3426 | @code\r | |
| 3427 | UINT64 Msr;\r | |
| 3428 | \r | |
| 3429 | Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT);\r | |
| 3430 | AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT, Msr);\r | |
| 3431 | @endcode\r | |
| 3432 | **/\r | |
| 2f88bd3a | 3433 | #define MSR_SKYLAKE_DRAM_POWER_LIMIT 0x00000618\r |
| 3add0205 ED |
3434 | \r |
| 3435 | /**\r | |
| 3436 | Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.\r | |
| 3437 | \r | |
| 3438 | @param ECX MSR_SKYLAKE_DRAM_ENERGY_STATUS (0x00000619)\r | |
| 3439 | @param EAX Lower 32-bits of MSR value.\r | |
| 3440 | Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.\r | |
| 3441 | @param EDX Upper 32-bits of MSR value.\r | |
| 3442 | Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.\r | |
| 3443 | \r | |
| 3444 | <b>Example usage</b>\r | |
| 3445 | @code\r | |
| 3446 | MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER Msr;\r | |
| 3447 | \r | |
| 3448 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_DRAM_ENERGY_STATUS);\r | |
| 3449 | @endcode\r | |
| 3450 | **/\r | |
| 2f88bd3a | 3451 | #define MSR_SKYLAKE_DRAM_ENERGY_STATUS 0x00000619\r |
| 3add0205 ED |
3452 | \r |
| 3453 | /**\r | |
| 3454 | MSR information returned for MSR index #MSR_SKYLAKE_DRAM_ENERGY_STATUS\r | |
| 3455 | **/\r | |
| 3456 | typedef union {\r | |
| 3457 | ///\r | |
| 3458 | /// Individual bit fields\r | |
| 3459 | ///\r | |
| 3460 | struct {\r | |
| 3461 | ///\r | |
| 3462 | /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r | |
| 3463 | /// to enable DRAM RAPL mode 0 (Direct VR).\r | |
| 3464 | ///\r | |
| 2f88bd3a MK |
3465 | UINT32 Energy : 32;\r |
| 3466 | UINT32 Reserved : 32;\r | |
| 3add0205 ED |
3467 | } Bits;\r |
| 3468 | ///\r | |
| 3469 | /// All bit fields as a 32-bit value\r | |
| 3470 | ///\r | |
| 2f88bd3a | 3471 | UINT32 Uint32;\r |
| 3add0205 ED |
3472 | ///\r |
| 3473 | /// All bit fields as a 64-bit value\r | |
| 3474 | ///\r | |
| 2f88bd3a | 3475 | UINT64 Uint64;\r |
| 3add0205 ED |
3476 | } MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER;\r |
| 3477 | \r | |
| 3add0205 ED |
3478 | /**\r |
| 3479 | Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r | |
| 3480 | RAPL Domain.".\r | |
| 3481 | \r | |
| 3482 | @param ECX MSR_SKYLAKE_DRAM_PERF_STATUS (0x0000061B)\r | |
| 3483 | @param EAX Lower 32-bits of MSR value.\r | |
| 3484 | @param EDX Upper 32-bits of MSR value.\r | |
| 3485 | \r | |
| 3486 | <b>Example usage</b>\r | |
| 3487 | @code\r | |
| 3488 | UINT64 Msr;\r | |
| 3489 | \r | |
| 3490 | Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_PERF_STATUS);\r | |
| 3491 | @endcode\r | |
| 3492 | **/\r | |
| 2f88bd3a | 3493 | #define MSR_SKYLAKE_DRAM_PERF_STATUS 0x0000061B\r |
| 3add0205 ED |
3494 | \r |
| 3495 | /**\r | |
| 3496 | Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
| 3497 | \r | |
| 3498 | @param ECX MSR_SKYLAKE_DRAM_POWER_INFO (0x0000061C)\r | |
| 3499 | @param EAX Lower 32-bits of MSR value.\r | |
| 3500 | @param EDX Upper 32-bits of MSR value.\r | |
| 3501 | \r | |
| 3502 | <b>Example usage</b>\r | |
| 3503 | @code\r | |
| 3504 | UINT64 Msr;\r | |
| 3505 | \r | |
| 3506 | Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO);\r | |
| 3507 | AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO, Msr);\r | |
| 3508 | @endcode\r | |
| 3509 | **/\r | |
| 2f88bd3a | 3510 | #define MSR_SKYLAKE_DRAM_POWER_INFO 0x0000061C\r |
| 3add0205 ED |
3511 | \r |
| 3512 | /**\r | |
| 3513 | Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r | |
| 3514 | fields represent the widest possible range of uncore frequencies. Writing to\r | |
| 3515 | these fields allows software to control the minimum and the maximum\r | |
| 3516 | frequency that hardware will select.\r | |
| 3517 | \r | |
| 3518 | @param ECX MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT (0x00000620)\r | |
| 3519 | @param EAX Lower 32-bits of MSR value.\r | |
| 3520 | Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.\r | |
| 3521 | @param EDX Upper 32-bits of MSR value.\r | |
| 3522 | Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.\r | |
| 3523 | \r | |
| 3524 | <b>Example usage</b>\r | |
| 3525 | @code\r | |
| 3526 | MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r | |
| 3527 | \r | |
| 3528 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT);\r | |
| 3529 | AsmWriteMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r | |
| 3530 | @endcode\r | |
| 3531 | **/\r | |
| 2f88bd3a | 3532 | #define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT 0x00000620\r |
| 3add0205 ED |
3533 | \r |
| 3534 | /**\r | |
| 3535 | MSR information returned for MSR index #MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT\r | |
| 3536 | **/\r | |
| 3537 | typedef union {\r | |
| 3538 | ///\r | |
| 3539 | /// Individual bit fields\r | |
| 3540 | ///\r | |
| 3541 | struct {\r | |
| 3542 | ///\r | |
| 3543 | /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r | |
| 3544 | /// LLC/Ring.\r | |
| 3545 | ///\r | |
| 2f88bd3a MK |
3546 | UINT32 MAX_RATIO : 7;\r |
| 3547 | UINT32 Reserved1 : 1;\r | |
| 3add0205 ED |
3548 | ///\r |
| 3549 | /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r | |
| 3550 | /// possible ratio of the LLC/Ring.\r | |
| 3551 | ///\r | |
| 2f88bd3a MK |
3552 | UINT32 MIN_RATIO : 7;\r |
| 3553 | UINT32 Reserved2 : 17;\r | |
| 3554 | UINT32 Reserved3 : 32;\r | |
| 3add0205 ED |
3555 | } Bits;\r |
| 3556 | ///\r | |
| 3557 | /// All bit fields as a 32-bit value\r | |
| 3558 | ///\r | |
| 2f88bd3a | 3559 | UINT32 Uint32;\r |
| 3add0205 ED |
3560 | ///\r |
| 3561 | /// All bit fields as a 64-bit value\r | |
| 3562 | ///\r | |
| 2f88bd3a | 3563 | UINT64 Uint64;\r |
| 3add0205 ED |
3564 | } MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER;\r |
| 3565 | \r | |
| 3add0205 ED |
3566 | /**\r |
| 3567 | Package. Reserved (R/O) Reads return 0.\r | |
| 3568 | \r | |
| 3569 | @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)\r | |
| 3570 | @param EAX Lower 32-bits of MSR value.\r | |
| 3571 | @param EDX Upper 32-bits of MSR value.\r | |
| 3572 | \r | |
| 3573 | <b>Example usage</b>\r | |
| 3574 | @code\r | |
| 3575 | UINT64 Msr;\r | |
| 3576 | \r | |
| 3577 | Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);\r | |
| 3578 | @endcode\r | |
| 3579 | **/\r | |
| 2f88bd3a | 3580 | #define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639\r |
| 3add0205 ED |
3581 | \r |
| 3582 | /**\r | |
| 3583 | THREAD. Monitoring Event Select Register (R/W) If CPUID.(EAX=07H,\r | |
| 3584 | ECX=0):EBX.RDT-M[bit 12] = 1.\r | |
| 3585 | \r | |
| 3586 | @param ECX MSR_SKYLAKE_IA32_QM_EVTSEL (0x00000C8D)\r | |
| 3587 | @param EAX Lower 32-bits of MSR value.\r | |
| 3588 | Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.\r | |
| 3589 | @param EDX Upper 32-bits of MSR value.\r | |
| 3590 | Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.\r | |
| 3591 | \r | |
| 3592 | <b>Example usage</b>\r | |
| 3593 | @code\r | |
| 3594 | MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER Msr;\r | |
| 3595 | \r | |
| 3596 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL);\r | |
| 3597 | AsmWriteMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL, Msr.Uint64);\r | |
| 3598 | @endcode\r | |
| 3599 | **/\r | |
| 2f88bd3a | 3600 | #define MSR_SKYLAKE_IA32_QM_EVTSEL 0x00000C8D\r |
| 3add0205 ED |
3601 | \r |
| 3602 | /**\r | |
| 3603 | MSR information returned for MSR index #MSR_SKYLAKE_IA32_QM_EVTSEL\r | |
| 3604 | **/\r | |
| 3605 | typedef union {\r | |
| 3606 | ///\r | |
| 3607 | /// Individual bit fields\r | |
| 3608 | ///\r | |
| 3609 | struct {\r | |
| 3610 | ///\r | |
| 3611 | /// [Bits 7:0] EventID (RW) Event encoding: 0x00: No monitoring. 0x01: L3\r | |
| 3612 | /// occupancy monitoring. 0x02: Total memory bandwidth monitoring. 0x03:\r | |
| 3613 | /// Local memory bandwidth monitoring. All other encoding reserved.\r | |
| 3614 | ///\r | |
| 2f88bd3a MK |
3615 | UINT32 EventID : 8;\r |
| 3616 | UINT32 Reserved1 : 24;\r | |
| 3add0205 ED |
3617 | ///\r |
| 3618 | /// [Bits 41:32] RMID (RW).\r | |
| 3619 | ///\r | |
| 2f88bd3a MK |
3620 | UINT32 RMID : 10;\r |
| 3621 | UINT32 Reserved2 : 22;\r | |
| 3add0205 ED |
3622 | } Bits;\r |
| 3623 | ///\r | |
| 3624 | /// All bit fields as a 64-bit value\r | |
| 3625 | ///\r | |
| 2f88bd3a | 3626 | UINT64 Uint64;\r |
| 3add0205 ED |
3627 | } MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER;\r |
| 3628 | \r | |
| 3add0205 ED |
3629 | /**\r |
| 3630 | THREAD. Resource Association Register (R/W).\r | |
| 3631 | \r | |
| 3632 | @param ECX MSR_SKYLAKE_IA32_PQR_ASSOC (0x00000C8F)\r | |
| 3633 | @param EAX Lower 32-bits of MSR value.\r | |
| 3634 | Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.\r | |
| 3635 | @param EDX Upper 32-bits of MSR value.\r | |
| 3636 | Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.\r | |
| 3637 | \r | |
| 3638 | <b>Example usage</b>\r | |
| 3639 | @code\r | |
| 3640 | MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER Msr;\r | |
| 3641 | \r | |
| 3642 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC);\r | |
| 3643 | AsmWriteMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC, Msr.Uint64);\r | |
| 3644 | @endcode\r | |
| 3645 | **/\r | |
| 2f88bd3a | 3646 | #define MSR_SKYLAKE_IA32_PQR_ASSOC 0x00000C8F\r |
| 3add0205 ED |
3647 | \r |
| 3648 | /**\r | |
| 3649 | MSR information returned for MSR index #MSR_SKYLAKE_IA32_PQR_ASSOC\r | |
| 3650 | **/\r | |
| 3651 | typedef union {\r | |
| 3652 | ///\r | |
| 3653 | /// Individual bit fields\r | |
| 3654 | ///\r | |
| 3655 | struct {\r | |
| 3656 | ///\r | |
| 3657 | /// [Bits 9:0] RMID.\r | |
| 3658 | ///\r | |
| 2f88bd3a MK |
3659 | UINT32 RMID : 10;\r |
| 3660 | UINT32 Reserved1 : 22;\r | |
| 3add0205 ED |
3661 | ///\r |
| 3662 | /// [Bits 51:32] COS (R/W).\r | |
| 3663 | ///\r | |
| 2f88bd3a MK |
3664 | UINT32 COS : 20;\r |
| 3665 | UINT32 Reserved2 : 12;\r | |
| 3add0205 ED |
3666 | } Bits;\r |
| 3667 | ///\r | |
| 3668 | /// All bit fields as a 64-bit value\r | |
| 3669 | ///\r | |
| 2f88bd3a | 3670 | UINT64 Uint64;\r |
| 3add0205 ED |
3671 | } MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER;\r |
| 3672 | \r | |
| 3add0205 ED |
3673 | /**\r |
| 3674 | Package. L3 Class Of Service Mask - COS N (R/W) If CPUID.(EAX=10H,\r | |
| 3675 | ECX=1):EDX.COS_MAX[15:0] >=0.\r | |
| 3676 | \r | |
| 3677 | @param ECX MSR_SKYLAKE_IA32_L3_QOS_MASK_N\r | |
| 3678 | @param EAX Lower 32-bits of MSR value.\r | |
| 3679 | Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.\r | |
| 3680 | @param EDX Upper 32-bits of MSR value.\r | |
| 3681 | Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.\r | |
| 3682 | \r | |
| 3683 | <b>Example usage</b>\r | |
| 3684 | @code\r | |
| 3685 | MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER Msr;\r | |
| 3686 | \r | |
| 3687 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N);\r | |
| 3688 | AsmWriteMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N, Msr.Uint64);\r | |
| 3689 | @endcode\r | |
| 3690 | **/\r | |
| 2f88bd3a MK |
3691 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_0 0x00000C90\r |
| 3692 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_1 0x00000C91\r | |
| 3693 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_2 0x00000C92\r | |
| 3694 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_3 0x00000C93\r | |
| 3695 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_4 0x00000C94\r | |
| 3696 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_5 0x00000C95\r | |
| 3697 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_6 0x00000C96\r | |
| 3698 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_7 0x00000C97\r | |
| 3699 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_8 0x00000C98\r | |
| 3700 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_9 0x00000C99\r | |
| 3701 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_10 0x00000C9A\r | |
| 3702 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_11 0x00000C9B\r | |
| 3703 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_12 0x00000C9C\r | |
| 3704 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_13 0x00000C9D\r | |
| 3705 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_14 0x00000C9E\r | |
| 3706 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_15 0x00000C9F\r | |
| 3add0205 ED |
3707 | \r |
| 3708 | /**\r | |
| 3709 | MSR information returned for MSR index #MSR_SKYLAKE_IA32_L3_QOS_MASK_N\r | |
| 3710 | **/\r | |
| 3711 | typedef union {\r | |
| 3712 | ///\r | |
| 3713 | /// Individual bit fields\r | |
| 3714 | ///\r | |
| 3715 | struct {\r | |
| 3716 | ///\r | |
| 3717 | /// [Bit 19:0] CBM: Bit vector of available L3 ways for COS N enforcement.\r | |
| 3718 | ///\r | |
| 2f88bd3a MK |
3719 | UINT32 CBM : 20;\r |
| 3720 | UINT32 Reserved2 : 12;\r | |
| 3721 | UINT32 Reserved3 : 32;\r | |
| 3add0205 ED |
3722 | } Bits;\r |
| 3723 | ///\r | |
| 3724 | /// All bit fields as a 32-bit value\r | |
| 3725 | ///\r | |
| 2f88bd3a | 3726 | UINT32 Uint32;\r |
| 3add0205 ED |
3727 | ///\r |
| 3728 | /// All bit fields as a 64-bit value\r | |
| 3729 | ///\r | |
| 2f88bd3a | 3730 | UINT64 Uint64;\r |
| 3add0205 ED |
3731 | } MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER;\r |
| 3732 | \r | |
| 6b55a245 | 3733 | #endif\r |