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1 | ;------------------------------------------------------------------------------\r |
2 | ;\r | |
3 | ; CpuBreakpoint() for AArch64\r | |
4 | ;\r | |
5 | ; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r | |
6 | ; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
7 | ; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r | |
8 | ; This program and the accompanying materials\r | |
9 | ; are licensed and made available under the terms and conditions of the BSD License\r | |
10 | ; which accompanies this distribution. The full text of the license may be found at\r | |
11 | ; http://opensource.org/licenses/bsd-license.php.\r | |
12 | ;\r | |
13 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
14 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
15 | ;\r | |
16 | ;------------------------------------------------------------------------------\r | |
17 | \r | |
18 | \r | |
19 | EXPORT CpuBreakpoint\r | |
20 | AREA BaseLib_LowLevel, CODE, READONLY\r | |
21 | \r | |
22 | ;/**\r | |
23 | ; Generates a breakpoint on the CPU.\r | |
24 | ;\r | |
25 | ; Generates a breakpoint on the CPU. The breakpoint must be implemented such\r | |
26 | ; that code can resume normal execution after the breakpoint.\r | |
27 | ;\r | |
28 | ;**/\r | |
29 | ;VOID\r | |
30 | ;EFIAPI\r | |
31 | ;CpuBreakpoint (\r | |
32 | ; VOID\r | |
33 | ; );\r | |
34 | ;\r | |
35 | CpuBreakpoint\r | |
36 | svc 0xdbdb // Superviser exception. Takes 16bit arg -> Armv7 had 'swi' here.\r | |
37 | ret\r | |
38 | \r | |
39 | END\r |