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Commit | Line | Data |
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e1f414b6 | 1 | /** @file\r |
2 | AsmFlushCacheLine function\r | |
3 | \r | |
9095d37b | 4 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
e1f414b6 | 6 | \r |
7 | **/\r | |
8 | \r | |
1efcc4ae | 9 | \r |
f734a10a | 10 | \r |
e1f414b6 | 11 | \r |
42eedea9 | 12 | /**\r |
13 | Flushes a cache line from all the instruction and data caches within the\r | |
14 | coherency domain of the CPU.\r | |
15 | \r | |
16 | Flushed the cache line specified by LinearAddress, and returns LinearAddress.\r | |
030cd1a2 | 17 | This function is only available on IA-32 and x64.\r |
42eedea9 | 18 | \r |
19 | @param LinearAddress The address of the cache line to flush. If the CPU is\r | |
20 | in a physical addressing mode, then LinearAddress is a\r | |
21 | physical address. If the CPU is in a virtual\r | |
22 | addressing mode, then LinearAddress is a virtual\r | |
23 | address.\r | |
24 | \r | |
25 | @return LinearAddress\r | |
26 | **/\r | |
e1f414b6 | 27 | VOID *\r |
28 | EFIAPI\r | |
29 | AsmFlushCacheLine (\r | |
30 | IN VOID *LinearAddress\r | |
31 | )\r | |
32 | {\r | |
881813d7 | 33 | //\r |
9095d37b | 34 | // If the CPU does not support CLFLUSH instruction,\r |
881813d7 MK |
35 | // then promote flush range to flush entire cache.\r |
36 | //\r | |
e1f414b6 | 37 | _asm {\r |
881813d7 MK |
38 | mov eax, 1\r |
39 | cpuid\r | |
40 | test edx, BIT19\r | |
41 | jz NoClflush\r | |
6f7878a9 | 42 | mov eax, dword ptr [LinearAddress]\r |
e1f414b6 | 43 | clflush [eax]\r |
881813d7 MK |
44 | jmp Done\r |
45 | NoClflush:\r | |
46 | wbinvd\r | |
47 | Done:\r | |
e1f414b6 | 48 | }\r |
9095d37b | 49 | \r |
881813d7 | 50 | return LinearAddress;\r |
e1f414b6 | 51 | }\r |
52 | \r |