[mirror_edk2.git] / MdePkg / Library / BaseLib / X64 / Thunk16.S

#------------------------------------------------------------------------------\r
#\r
# Copyright (c) 2006 - 2009, Intel Corporation\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution.  The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php\r
#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
# Module Name:\r
#\r
#   Thunk16.S\r
#\r
# Abstract:\r
#\r
#   Real mode thunk\r
#\r
#------------------------------------------------------------------------------\r
\r
#include <Library/BaseLib.h>\r
\r
ASM_GLOBAL ASM_PFX(m16Start)\r
ASM_GLOBAL ASM_PFX(m16Size)\r
ASM_GLOBAL ASM_PFX(mThunk16Attr)\r
ASM_GLOBAL ASM_PFX(m16Gdt)\r
ASM_GLOBAL ASM_PFX(m16GdtrBase)\r
ASM_GLOBAL ASM_PFX(mTransition)\r
ASM_GLOBAL ASM_PFX(InternalAsmThunk16)\r
\r
# define the structure of IA32_REGS\r
.set  _EDI, 0       #size 4\r
.set  _ESI, 4       #size 4\r
.set  _EBP, 8       #size 4\r
.set  _ESP, 12      #size 4\r
.set  _EBX, 16      #size 4\r
.set  _EDX, 20      #size 4\r
.set  _ECX, 24      #size 4\r
.set  _EAX, 28      #size 4\r
.set  _DS,  32      #size 2\r
.set  _ES,  34      #size 2\r
.set  _FS,  36      #size 2\r
.set  _GS,  38      #size 2\r
.set  _EFLAGS, 40   #size 8\r
.set  _EIP, 48      #size 4\r
.set  _CS, 52       #size 2\r
.set  _SS, 54       #size 2\r
.set  IA32_REGS_SIZE, 56\r
\r
    .data\r
\r
ASM_PFX(m16Size):         .word      ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)\r
ASM_PFX(mThunk16Attr):    .word      _ThunkAttr - ASM_PFX(m16Start)\r
ASM_PFX(m16Gdt):          .word      ASM_PFX(NullSeg) - ASM_PFX(m16Start)\r
ASM_PFX(m16GdtrBase):     .word      _16GdtrBase - ASM_PFX(m16Start)\r
ASM_PFX(mTransition):     .word      _EntryPoint - ASM_PFX(m16Start)\r
\r
    .text\r
\r
ASM_PFX(m16Start):\r
\r
SavedGdt:    .space 10\r
\r
#------------------------------------------------------------------------------\r
# _BackFromUserCode() takes control in real mode after 'retf' has been executed\r
# by user code. It will be shadowed to somewhere in memory below 1MB.\r
#------------------------------------------------------------------------------\r
ASM_GLOBAL ASM_PFX(BackFromUserCode)\r
ASM_PFX(BackFromUserCode):\r
    #\r
    # The order of saved registers on the stack matches the order they appears\r
    # in IA32_REGS structure. This facilitates wrapper function to extract them\r
    # into that structure.\r
    #\r
    # Some instructions for manipulation of segment registers have to be written\r
    # in opcode since 64-bit MASM prevents accesses to those registers.\r
    #\r
    .byte 0x16                          # push ss\r
    .byte 0xe                           # push cs\r
    .byte 0x66\r
    call    L_Base                       # push eip\r
L_Base: \r
    .byte 0x66\r
    pushq   $0                          # reserved high order 32 bits of EFlags\r
    .byte 0x66, 0x9c                    # pushfd actually\r
    cli                                 # disable interrupts\r
    push    %gs\r
    push    %fs\r
    .byte 6                             # push es\r
    .byte 0x1e                          # push ds\r
    .byte 0x66,0x60                     # pushad\r
    .byte 0x66,0xba                     # mov edx, imm32\r
_ThunkAttr:  .space  4\r
    testb   $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl\r
    jz      L_1\r
    movl    $0x15cd2401,%eax            # mov ax, 2401h & int 15h\r
    cli                                 # disable interrupts\r
    jnc     L_2\r
L_1: \r
    testb   $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl\r
    jz      L_2\r
    inb     $0x92,%al\r
    orb     $2,%al\r
    outb    %al, $0x92                   # deactivate A20M#\r
L_2: \r
    movl    %ss,%eax\r
    lea     IA32_REGS_SIZE(%esp), %bp\r
    #\r
    # rsi in the following 2 instructions is indeed bp in 16-bit code\r
    #\r
    movw    %bp, (_ESP - IA32_REGS_SIZE)(%rsi)\r
    .byte 0x66\r
    movl    (_EIP - IA32_REGS_SIZE)(%rsi), %ebx\r
    shlw    $4,%ax                      # shl eax, 4\r
    addw    %ax,%bp                     # add ebp, eax\r
    movw    %cs,%ax\r
    shlw    $4,%ax\r
    lea     (L_64BitCode - L_Base)(%ebx, %eax), %ax\r
    .byte 0x66,0x2e,0x89,0x87           # mov cs:[bx + (L_64Eip - L_Base)], eax\r
    .word   L_64Eip - L_Base\r
    .byte 0x66,0xb8                     # mov eax, imm32\r
SavedCr4:   .space  4\r
    movq    %rax, %cr4\r
    #\r
    # rdi in the instruction below is indeed bx in 16-bit code\r
    #\r
    .byte 0x66,0x2e                     # 2eh is "cs:" segment override\r
    lgdt    (SavedGdt - L_Base)(%rdi)\r
    .byte 0x66\r
    movl    $0xc0000080,%ecx\r
    rdmsr\r
    orb     $1,%ah\r
    wrmsr\r
    .byte 0x66,0xb8                     # mov eax, imm32\r
SavedCr0:    .space      4\r
    movq    %rax, %cr0\r
    .byte 0x66,0xea                     # jmp far cs:L_64Bit\r
L_64Eip:     .space      4\r
SavedCs:     .space      2\r
L_64BitCode: \r
    .byte   0x90\r
    .byte   0x67,0xbc                  # mov esp, imm32\r
SavedSp:    .space 4                   # restore stack\r
    nop\r
    ret\r
\r
_EntryPoint: .long      ASM_PFX(ToUserCode) - ASM_PFX(m16Start)\r
             .word      CODE16\r
_16Gdtr:     .word      GDT_SIZE - 1\r
_16GdtrBase: .quad      ASM_PFX(NullSeg)\r
_16Idtr:     .word      0x3ff\r
             .long      0\r
\r
#------------------------------------------------------------------------------\r
# _ToUserCode() takes control in real mode before passing control to user code.\r
# It will be shadowed to somewhere in memory below 1MB.\r
#------------------------------------------------------------------------------\r
ASM_GLOBAL ASM_PFX(ToUserCode)\r
ASM_PFX(ToUserCode):\r
    movl    %edx,%ss                    # set new segment selectors\r
    movl    %edx,%ds\r
    movl    %edx,%es\r
    movl    %edx,%fs\r
    movl    %edx,%gs\r
    .byte 0x66\r
    movl    $0xc0000080,%ecx\r
    movq    %rax, %cr0\r
    rdmsr\r
    andb    $0xfe, %ah                  # $0b11111110\r
    wrmsr\r
    movq    %rbp, %cr4\r
    movl    %esi,%ss                    # set up 16-bit stack segment\r
    movw    %bx,%sp                     # set up 16-bit stack pointer\r
    .byte 0x66                          # make the following call 32-bit\r
    call    L_Base1                       # push eip\r
L_Base1: \r
    popw    %bp                         # ebp <- address of L_Base1\r
    pushq   (IA32_REGS_SIZE + 2)(%esp)\r
    lea     0x0c(%rsi), %eax\r
    pushq   %rax\r
    lret                                # execution begins at next instruction\r
L_RealMode: \r
    .byte 0x66,0x2e                     # CS and operand size override\r
    lidt    (_16Idtr - L_Base1)(%rsi)\r
    .byte 0x66,0x61                     # popad\r
    .byte 0x1f                          # pop ds\r
    .byte 0x7                           # pop es\r
    .byte 0x0f, 0xa1                    # pop fs\r
    .byte 0x0f, 0xa9                    # pop gs\r
    .byte 0x66, 0x9d                    # popfd\r
    leaw    4(%esp),%sp                 # skip high order 32 bits of EFlags\r
    .byte 0x66                          # make the following retf 32-bit\r
    lret                                # transfer control to user code\r
\r
.set  CODE16,  ASM_PFX(_16Code) - .\r
.set  DATA16,  ASM_PFX(_16Data) - .\r
.set  DATA32,  ASM_PFX(_32Data) - .\r
\r
ASM_PFX(NullSeg):   .quad      0\r
ASM_PFX(_16Code):\r
            .word -1\r
            .word 0\r
            .byte 0\r
            .byte 0x9b\r
            .byte 0x8f                  # 16-bit segment, 4GB limit\r
            .byte 0\r
ASM_PFX(_16Data):\r
            .word -1\r
            .word 0\r
            .byte 0\r
            .byte 0x93\r
            .byte 0x8f                  # 16-bit segment, 4GB limit\r
            .byte 0\r
ASM_PFX(_32Data):\r
            .word -1\r
            .word 0\r
            .byte 0\r
            .byte 0x93\r
            .byte 0xcf                  # 16-bit segment, 4GB limit\r
            .byte 0\r
\r
.set  GDT_SIZE, . - ASM_PFX(NullSeg)\r
\r
#------------------------------------------------------------------------------\r
# IA32_REGISTER_SET *\r
# EFIAPI\r
# InternalAsmThunk16 (\r
#   IN      IA32_REGISTER_SET         *RegisterSet,\r
#   IN OUT  VOID                      *Transition\r
#   );\r
#------------------------------------------------------------------------------\r
\r
ASM_GLOBAL ASM_PFX(InternalAsmThunk16)\r
ASM_PFX(InternalAsmThunk16):\r
    pushq   %rbp\r
    pushq   %rbx\r
    pushq   %rsi\r
    pushq   %rdi\r
    \r
    movl    %ds, %ebx\r
    pushq   %rbx      # Save ds segment register on the stack\r
    movl    %es, %ebx\r
    pushq   %rbx      # Save es segment register on the stack\r
    movl    %ss, %ebx\r
    pushq   %rbx      # Save ss segment register on the stack\r
\r
    .byte   0x0f, 0xa0                  #push   fs\r
    .byte   0x0f, 0xa8                  #push   gs\r
    movq    %rcx, %rsi\r
    movzwl  _SS(%rsi), %r8d\r
    movl    _ESP(%rsi), %edi\r
    lea     -(IA32_REGS_SIZE + 4)(%edi), %rdi\r
    imul    $16, %r8d, %eax \r
    movl    %edi,%ebx                   # ebx <- stack for 16-bit code\r
    pushq   $(IA32_REGS_SIZE / 4)\r
    addl    %eax,%edi                   # edi <- linear address of 16-bit stack\r
    popq    %rcx\r
    rep\r
    movsl                               # copy RegSet\r
    lea     (SavedCr4 - ASM_PFX(m16Start))(%rdx), %ecx\r
    movl    %edx,%eax                   # eax <- transition code address\r
    andl    $0xf,%edx\r
    shll    $12,%eax                    # segment address in high order 16 bits\r
    lea     (ASM_PFX(BackFromUserCode) - ASM_PFX(m16Start))(%rdx), %ax\r
    stosl                               # [edi] <- return address of user code\r
    sgdt    0x60(%rsp)                  # save GDT stack in argument space\r
    movzwq  0x60(%rsp), %r10            # r10 <- GDT limit \r
    lea     ((ASM_PFX(InternalAsmThunk16) - SavedCr4) + 0xf)(%rcx), %r11 \r
    andq    $0xfffffffffffffff0, %r11   # r11 <- 16-byte aligned shadowed GDT table in real mode buffer      \r
    \r
    movw    %r10w, (SavedGdt - SavedCr4)(%rcx)       # save the limit of shadowed GDT table\r
    movq    %r11, (SavedGdt - SavedCr4 + 0x2)(%rcx)  # save the base address of shadowed GDT table\r
    \r
    movq    0x62(%rsp) ,%rsi            # rsi <- the original GDT base address\r
    xchg   %r10, %rcx                   # save rcx to r10 and initialize rcx to be the limit of GDT table \r
    incq   %rcx                         # rcx <- the size of memory to copy\r
    xchg   %r11, %rdi                   # save rdi to r11 and initialize rdi to the base address of shadowed GDT table\r
    rep\r
    movsb                               # perform memory copy to shadow GDT table\r
    movq   %r10, %rcx                   # restore the orignal rcx before memory copy\r
    movq   %r11, %rdi                   # restore the original rdi before memory copy\r
       \r
    sidt    0x50(%rsp)\r
    movq    %cr0, %rax\r
    movl    %eax, (SavedCr0 - SavedCr4)(%rcx)\r
    andl    $0x7ffffffe,%eax            # clear PE, PG bits\r
    movq    %cr4, %rbp\r
    movl    %ebp, (%rcx)                # save CR4 in SavedCr4\r
    andl    $0x300,%ebp                 # clear all but PCE and OSFXSR bits\r
    movl    %r8d, %esi                  # esi <- 16-bit stack segment\r
    .byte      0x6a, DATA32\r
    popq    %rdx\r
    lgdt    (_16Gdtr - SavedCr4)(%rcx)\r
    movl    %edx,%ss\r
    pushfq\r
    lea     -8(%rdx), %edx\r
    lea     L_RetFromRealMode(%rip), %r8\r
    pushq   %r8\r
    movl    %cs, %r8d\r
    movw    %r8w, (SavedCs - SavedCr4)(%rcx)\r
    movl    %esp, (SavedSp - SavedCr4)(%rcx)\r
    .byte   0xff, 0x69                  #  jmp (_EntryPoint - SavedCr4)(%rcx)\r
    .byte   _EntryPoint - SavedCr4\r
L_RetFromRealMode: \r
    popfq\r
    lgdt    0x60(%rsp)                  # restore protected mode GDTR\r
    lidt    0x50(%rsp)                  # restore protected mode IDTR\r
    lea     -IA32_REGS_SIZE(%rbp), %eax\r
    .byte 0x0f, 0xa9                    # pop gs\r
    .byte 0x0f, 0xa1                    # pop fs\r
    \r
    popq     %rbx\r
    movl     %ebx, %ss\r
    popq     %rbx\r
    movl     %ebx, %es\r
    popq     %rbx\r
    movl     %ebx, %ds\r
    \r
    popq    %rdi\r
    popq    %rsi\r
    popq    %rbx\r
    popq    %rbp\r
\r
    ret\r
Commit	Line	Data
b1ff428c	1	#------------------------------------------------------------------------------\r
b1ff428c	2	#\r
c9268416	3	# Copyright (c) 2006 - 2009, Intel Corporation\r
b1ff428c	4	# All rights reserved. This program and the accompanying materials\r
	5	# are licensed and made available under the terms and conditions of the BSD License\r
	6	# which accompanies this distribution. The full text of the license may be found at\r
	7	# http://opensource.org/licenses/bsd-license.php\r
	8	#\r
	9	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	10	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	11	#\r
	12	# Module Name:\r
	13	#\r
	14	# Thunk16.S\r
	15	#\r
	16	# Abstract:\r
	17	#\r
	18	# Real mode thunk\r
	19	#\r
	20	#------------------------------------------------------------------------------\r
	21	\r
	22	#include <Library/BaseLib.h>\r
	23	\r
132f41f0	24	ASM_GLOBAL ASM_PFX(m16Start)\r
	25	ASM_GLOBAL ASM_PFX(m16Size)\r
	26	ASM_GLOBAL ASM_PFX(mThunk16Attr)\r
	27	ASM_GLOBAL ASM_PFX(m16Gdt)\r
	28	ASM_GLOBAL ASM_PFX(m16GdtrBase)\r
	29	ASM_GLOBAL ASM_PFX(mTransition)\r
	30	ASM_GLOBAL ASM_PFX(InternalAsmThunk16)\r
b1ff428c	31	\r
b1ff428c	32	# define the structure of IA32_REGS\r
1afe0401 A	33	.set _EDI, 0 #size 4\r
	34	.set _ESI, 4 #size 4\r
	35	.set _EBP, 8 #size 4\r
	36	.set _ESP, 12 #size 4\r
	37	.set _EBX, 16 #size 4\r
	38	.set _EDX, 20 #size 4\r
	39	.set _ECX, 24 #size 4\r
	40	.set _EAX, 28 #size 4\r
	41	.set _DS, 32 #size 2\r
	42	.set _ES, 34 #size 2\r
	43	.set _FS, 36 #size 2\r
	44	.set _GS, 38 #size 2\r
	45	.set _EFLAGS, 40 #size 8\r
	46	.set _EIP, 48 #size 4\r
	47	.set _CS, 52 #size 2\r
	48	.set _SS, 54 #size 2\r
	49	.set IA32_REGS_SIZE, 56\r
b1ff428c	50	\r
	51	.data\r
	52	\r
	53	ASM_PFX(m16Size): .word ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)\r
	54	ASM_PFX(mThunk16Attr): .word _ThunkAttr - ASM_PFX(m16Start)\r
c9268416	55	ASM_PFX(m16Gdt): .word ASM_PFX(NullSeg) - ASM_PFX(m16Start)\r
b1ff428c	56	ASM_PFX(m16GdtrBase): .word _16GdtrBase - ASM_PFX(m16Start)\r
	57	ASM_PFX(mTransition): .word _EntryPoint - ASM_PFX(m16Start)\r
	58	\r
	59	.text\r
	60	\r
	61	ASM_PFX(m16Start):\r
	62	\r
	63	SavedGdt: .space 10\r
	64	\r
	65	#------------------------------------------------------------------------------\r
	66	# _BackFromUserCode() takes control in real mode after 'retf' has been executed\r
	67	# by user code. It will be shadowed to somewhere in memory below 1MB.\r
	68	#------------------------------------------------------------------------------\r
132f41f0	69	ASM_GLOBAL ASM_PFX(BackFromUserCode)\r
b1ff428c	70	ASM_PFX(BackFromUserCode):\r
	71	#\r
	72	# The order of saved registers on the stack matches the order they appears\r
	73	# in IA32_REGS structure. This facilitates wrapper function to extract them\r
	74	# into that structure.\r
	75	#\r
	76	# Some instructions for manipulation of segment registers have to be written\r
	77	# in opcode since 64-bit MASM prevents accesses to those registers.\r
	78	#\r
	79	.byte 0x16 # push ss\r
	80	.byte 0xe # push cs\r
	81	.byte 0x66\r
	82	call L_Base # push eip\r
	83	L_Base: \r
	84	.byte 0x66\r
	85	pushq $0 # reserved high order 32 bits of EFlags\r
	86	.byte 0x66, 0x9c # pushfd actually\r
	87	cli # disable interrupts\r
	88	push %gs\r
	89	push %fs\r
	90	.byte 6 # push es\r
	91	.byte 0x1e # push ds\r
	92	.byte 0x66,0x60 # pushad\r
	93	.byte 0x66,0xba # mov edx, imm32\r
	94	_ThunkAttr: .space 4\r
	95	testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl\r
	96	jz L_1\r
	97	movl $0x15cd2401,%eax # mov ax, 2401h & int 15h\r
	98	cli # disable interrupts\r
	99	jnc L_2\r
	100	L_1: \r
	101	testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl\r
	102	jz L_2\r
	103	inb $0x92,%al\r
	104	orb $2,%al\r
	105	outb %al, $0x92 # deactivate A20M#\r
	106	L_2: \r
	107	movl %ss,%eax\r
	108	lea IA32_REGS_SIZE(%esp), %bp\r
	109	#\r
	110	# rsi in the following 2 instructions is indeed bp in 16-bit code\r
	111	#\r
	112	movw %bp, (_ESP - IA32_REGS_SIZE)(%rsi)\r
	113	.byte 0x66\r
	114	movl (_EIP - IA32_REGS_SIZE)(%rsi), %ebx\r
	115	shlw $4,%ax # shl eax, 4\r
	116	addw %ax,%bp # add ebp, eax\r
	117	movw %cs,%ax\r
	118	shlw $4,%ax\r
	119	lea (L_64BitCode - L_Base)(%ebx, %eax), %ax\r
	120	.byte 0x66,0x2e,0x89,0x87 # mov cs:[bx + (L_64Eip - L_Base)], eax\r
	121	.word L_64Eip - L_Base\r
	122	.byte 0x66,0xb8 # mov eax, imm32\r
	123	SavedCr4: .space 4\r
	124	movq %rax, %cr4\r
	125	#\r
	126	# rdi in the instruction below is indeed bx in 16-bit code\r
	127	#\r
	128	.byte 0x66,0x2e # 2eh is "cs:" segment override\r
	129	lgdt (SavedGdt - L_Base)(%rdi)\r
	130	.byte 0x66\r
	131	movl $0xc0000080,%ecx\r
	132	rdmsr\r
	133	orb $1,%ah\r
134	wrmsr\r
135	.byte 0x66,0xb8 # mov eax, imm32\r
136	SavedCr0: .space 4\r
137	movq %rax, %cr0\r
138	.byte 0x66,0xea # jmp far cs:L_64Bit\r
0fe43214	139	L_64Eip: .space 4\r
b1ff428c	140	SavedCs: .space 2\r
b1ff428c	141	L_64BitCode: \r
0fe43214	142	.byte 0x90\r
	143	.byte 0x67,0xbc # mov esp, imm32\r
	144	SavedSp: .space 4 # restore stack\r
	145	nop\r
b1ff428c	146	ret\r
	147	\r
	148	_EntryPoint: .long ASM_PFX(ToUserCode) - ASM_PFX(m16Start)\r
	149	.word CODE16\r
	150	_16Gdtr: .word GDT_SIZE - 1\r
c9268416	151	_16GdtrBase: .quad ASM_PFX(NullSeg)\r
b1ff428c	152	_16Idtr: .word 0x3ff\r
	153	.long 0\r
	154	\r
	155	#------------------------------------------------------------------------------\r
	156	# _ToUserCode() takes control in real mode before passing control to user code.\r
	157	# It will be shadowed to somewhere in memory below 1MB.\r
	158	#------------------------------------------------------------------------------\r
132f41f0	159	ASM_GLOBAL ASM_PFX(ToUserCode)\r
b1ff428c	160	ASM_PFX(ToUserCode):\r
	161	movl %edx,%ss # set new segment selectors\r
	162	movl %edx,%ds\r
	163	movl %edx,%es\r
	164	movl %edx,%fs\r
	165	movl %edx,%gs\r
	166	.byte 0x66\r
	167	movl $0xc0000080,%ecx\r
	168	movq %rax, %cr0\r
	169	rdmsr\r
1afe0401	170	andb $0xfe, %ah # $0b11111110\r
b1ff428c	171	wrmsr\r
	172	movq %rbp, %cr4\r
	173	movl %esi,%ss # set up 16-bit stack segment\r
	174	movw %bx,%sp # set up 16-bit stack pointer\r
	175	.byte 0x66 # make the following call 32-bit\r
	176	call L_Base1 # push eip\r
	177	L_Base1: \r
	178	popw %bp # ebp <- address of L_Base1\r
	179	pushq (IA32_REGS_SIZE + 2)(%esp)\r
	180	lea 0x0c(%rsi), %eax\r
	181	pushq %rax\r
	182	lret # execution begins at next instruction\r
	183	L_RealMode: \r
	184	.byte 0x66,0x2e # CS and operand size override\r
	185	lidt (_16Idtr - L_Base1)(%rsi)\r
	186	.byte 0x66,0x61 # popad\r
	187	.byte 0x1f # pop ds\r
	188	.byte 0x7 # pop es\r
	189	.byte 0x0f, 0xa1 # pop fs\r
	190	.byte 0x0f, 0xa9 # pop gs\r
	191	.byte 0x66, 0x9d # popfd\r
	192	leaw 4(%esp),%sp # skip high order 32 bits of EFlags\r
	193	.byte 0x66 # make the following retf 32-bit\r
	194	lret # transfer control to user code\r
	195	\r
1afe0401 A	196	.set CODE16, ASM_PFX(_16Code) - .\r
	197	.set DATA16, ASM_PFX(_16Data) - .\r
	198	.set DATA32, ASM_PFX(_32Data) - .\r
b1ff428c	199	\r
c9268416	200	ASM_PFX(NullSeg): .quad 0\r
c9268416	201	ASM_PFX(_16Code):\r
b1ff428c	202	.word -1\r
	203	.word 0\r
	204	.byte 0\r
	205	.byte 0x9b\r
	206	.byte 0x8f # 16-bit segment, 4GB limit\r
	207	.byte 0\r
c9268416	208	ASM_PFX(_16Data):\r
b1ff428c	209	.word -1\r
	210	.word 0\r
	211	.byte 0\r
	212	.byte 0x93\r
	213	.byte 0x8f # 16-bit segment, 4GB limit\r
	214	.byte 0\r
c9268416	215	ASM_PFX(_32Data):\r
b1ff428c	216	.word -1\r
	217	.word 0\r
	218	.byte 0\r
	219	.byte 0x93\r
	220	.byte 0xcf # 16-bit segment, 4GB limit\r
	221	.byte 0\r
	222	\r
1afe0401	223	.set GDT_SIZE, . - ASM_PFX(NullSeg)\r
b1ff428c	224	\r
	225	#------------------------------------------------------------------------------\r
	226	# IA32_REGISTER_SET *\r
	227	# EFIAPI\r
	228	# InternalAsmThunk16 (\r
	229	# IN IA32_REGISTER_SET *RegisterSet,\r
	230	# IN OUT VOID *Transition\r
	231	# );\r
	232	#------------------------------------------------------------------------------\r
b1ff428c	233	\r
132f41f0	234	ASM_GLOBAL ASM_PFX(InternalAsmThunk16)\r
b1ff428c	235	ASM_PFX(InternalAsmThunk16):\r
	236	pushq %rbp\r
	237	pushq %rbx\r
	238	pushq %rsi\r
	239	pushq %rdi\r
	240	\r
1afe0401	241	movl %ds, %ebx\r
0fe43214	242	pushq %rbx # Save ds segment register on the stack\r
1afe0401	243	movl %es, %ebx\r
0fe43214	244	pushq %rbx # Save es segment register on the stack\r
1afe0401	245	movl %ss, %ebx\r
0fe43214	246	pushq %rbx # Save ss segment register on the stack\r
0fe43214	247	\r
b1ff428c	248	.byte 0x0f, 0xa0 #push fs\r
	249	.byte 0x0f, 0xa8 #push gs\r
	250	movq %rcx, %rsi\r
	251	movzwl _SS(%rsi), %r8d\r
	252	movl _ESP(%rsi), %edi\r
	253	lea -(IA32_REGS_SIZE + 4)(%edi), %rdi\r
	254	imul $16, %r8d, %eax \r
	255	movl %edi,%ebx # ebx <- stack for 16-bit code\r
	256	pushq $(IA32_REGS_SIZE / 4)\r
	257	addl %eax,%edi # edi <- linear address of 16-bit stack\r
	258	popq %rcx\r
	259	rep\r
	260	movsl # copy RegSet\r
	261	lea (SavedCr4 - ASM_PFX(m16Start))(%rdx), %ecx\r
	262	movl %edx,%eax # eax <- transition code address\r
	263	andl $0xf,%edx\r
	264	shll $12,%eax # segment address in high order 16 bits\r
4e57f240	265	lea (ASM_PFX(BackFromUserCode) - ASM_PFX(m16Start))(%rdx), %ax\r
b1ff428c	266	stosl # [edi] <- return address of user code\r
a1487801	267	sgdt 0x60(%rsp) # save GDT stack in argument space\r
	268	movzwq 0x60(%rsp), %r10 # r10 <- GDT limit \r
	269	lea ((ASM_PFX(InternalAsmThunk16) - SavedCr4) + 0xf)(%rcx), %r11 \r
1afe0401	270	andq $0xfffffffffffffff0, %r11 # r11 <- 16-byte aligned shadowed GDT table in real mode buffer \r
a1487801	271	\r
	272	movw %r10w, (SavedGdt - SavedCr4)(%rcx) # save the limit of shadowed GDT table\r
	273	movq %r11, (SavedGdt - SavedCr4 + 0x2)(%rcx) # save the base address of shadowed GDT table\r
	274	\r
	275	movq 0x62(%rsp) ,%rsi # rsi <- the original GDT base address\r
	276	xchg %r10, %rcx # save rcx to r10 and initialize rcx to be the limit of GDT table \r
	277	incq %rcx # rcx <- the size of memory to copy\r
	278	xchg %r11, %rdi # save rdi to r11 and initialize rdi to the base address of shadowed GDT table\r
	279	rep\r
	280	movsb # perform memory copy to shadow GDT table\r
	281	movq %r10, %rcx # restore the orignal rcx before memory copy\r
	282	movq %r11, %rdi # restore the original rdi before memory copy\r
	283	\r
0fe43214	284	sidt 0x50(%rsp)\r
b1ff428c	285	movq %cr0, %rax\r
	286	movl %eax, (SavedCr0 - SavedCr4)(%rcx)\r
	287	andl $0x7ffffffe,%eax # clear PE, PG bits\r
	288	movq %cr4, %rbp\r
	289	movl %ebp, (%rcx) # save CR4 in SavedCr4\r
	290	andl $0x300,%ebp # clear all but PCE and OSFXSR bits\r
	291	movl %r8d, %esi # esi <- 16-bit stack segment\r
	292	.byte 0x6a, DATA32\r
	293	popq %rdx\r
	294	lgdt (_16Gdtr - SavedCr4)(%rcx)\r
	295	movl %edx,%ss\r
	296	pushfq\r
	297	lea -8(%rdx), %edx\r
d48e8b0a	298	lea L_RetFromRealMode(%rip), %r8\r
b1ff428c	299	pushq %r8\r
	300	movl %cs, %r8d\r
	301	movw %r8w, (SavedCs - SavedCr4)(%rcx)\r
0fe43214	302	movl %esp, (SavedSp - SavedCr4)(%rcx)\r
b1ff428c	303	.byte 0xff, 0x69 # jmp (_EntryPoint - SavedCr4)(%rcx)\r
	304	.byte _EntryPoint - SavedCr4\r
	305	L_RetFromRealMode: \r
	306	popfq\r
a1487801	307	lgdt 0x60(%rsp) # restore protected mode GDTR\r
a1487801	308	lidt 0x50(%rsp) # restore protected mode IDTR\r
b1ff428c	309	lea -IA32_REGS_SIZE(%rbp), %eax\r
	310	.byte 0x0f, 0xa9 # pop gs\r
	311	.byte 0x0f, 0xa1 # pop fs\r
0fe43214	312	\r
132f41f0	313	popq %rbx\r
1afe0401	314	movl %ebx, %ss\r
132f41f0	315	popq %rbx\r
1afe0401	316	movl %ebx, %es\r
132f41f0	317	popq %rbx\r
1afe0401	318	movl %ebx, %ds\r
b1ff428c	319	\r
	320	popq %rdi\r
	321	popq %rsi\r
	322	popq %rbx\r
	323	popq %rbp\r
	324	\r
	325	ret\r