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e1f414b6 | 1 | /** @file\r |
5c57f3ea | 2 | PCI Library functions that use the 256 MB PCI Express MMIO window to perform PCI\r |
3 | Configuration cycles. Layers on PCI Express Library.\r | |
e1f414b6 | 4 | \r |
9095d37b | 5 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
e1f414b6 | 7 | \r |
e1f414b6 | 8 | **/\r |
9 | \r | |
c7d265a9 | 10 | #include <Base.h>\r |
c892d846 | 11 | \r |
c7d265a9 | 12 | #include <Library/PciLib.h>\r |
13 | #include <Library/PciExpressLib.h>\r | |
e1f414b6 | 14 | \r |
3e3ae634 | 15 | /**\r |
9095d37b | 16 | Registers a PCI device so PCI configuration registers may be accessed after\r |
3e3ae634 | 17 | SetVirtualAddressMap().\r |
9095d37b LG |
18 | \r |
19 | Registers the PCI device specified by Address so all the PCI configuration registers\r | |
d11195a3 | 20 | associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r |
9095d37b | 21 | \r |
3e3ae634 | 22 | If Address > 0x0FFFFFFF, then ASSERT().\r |
23 | \r | |
2fc59a00 | 24 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
3e3ae634 | 25 | Register.\r |
9095d37b | 26 | \r |
3e3ae634 | 27 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
9095d37b | 28 | @retval RETURN_UNSUPPORTED An attempt was made to call this function\r |
3e3ae634 | 29 | after ExitBootServices().\r |
30 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
31 | at runtime could not be mapped.\r | |
32 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
33 | complete the registration.\r | |
34 | \r | |
35 | **/\r | |
36 | RETURN_STATUS\r | |
37 | EFIAPI\r | |
38 | PciRegisterForRuntimeAccess (\r | |
39 | IN UINTN Address\r | |
40 | )\r | |
41 | {\r | |
42 | return PciExpressRegisterForRuntimeAccess (Address);\r | |
43 | }\r | |
44 | \r | |
e1f414b6 | 45 | /**\r |
46 | Reads an 8-bit PCI configuration register.\r | |
47 | \r | |
48 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
49 | This function must guarantee that all PCI read and write operations are\r | |
50 | serialized.\r | |
51 | \r | |
52 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
53 | \r | |
2fc59a00 | 54 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 55 | Register.\r |
56 | \r | |
57 | @return The read value from the PCI configuration register.\r | |
58 | \r | |
59 | **/\r | |
60 | UINT8\r | |
61 | EFIAPI\r | |
62 | PciRead8 (\r | |
2f88bd3a | 63 | IN UINTN Address\r |
e1f414b6 | 64 | )\r |
65 | {\r | |
66 | return PciExpressRead8 (Address);\r | |
67 | }\r | |
68 | \r | |
69 | /**\r | |
70 | Writes an 8-bit PCI configuration register.\r | |
71 | \r | |
72 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
73 | value specified by Value. Value is returned. This function must guarantee\r | |
74 | that all PCI read and write operations are serialized.\r | |
75 | \r | |
76 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
77 | \r | |
2fc59a00 | 78 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 79 | Register.\r |
7612cbf0 | 80 | @param Value The value to write.\r |
e1f414b6 | 81 | \r |
82 | @return The value written to the PCI configuration register.\r | |
83 | \r | |
84 | **/\r | |
85 | UINT8\r | |
86 | EFIAPI\r | |
87 | PciWrite8 (\r | |
2f88bd3a MK |
88 | IN UINTN Address,\r |
89 | IN UINT8 Value\r | |
e1f414b6 | 90 | )\r |
91 | {\r | |
94646ec0 | 92 | return PciExpressWrite8 (Address, Value);\r |
e1f414b6 | 93 | }\r |
94 | \r | |
95 | /**\r | |
62991af2 | 96 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
e1f414b6 | 97 | an 8-bit value.\r |
98 | \r | |
99 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 100 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 101 | OrData, and writes the result to the 8-bit PCI configuration register\r |
102 | specified by Address. The value written to the PCI configuration register is\r | |
103 | returned. This function must guarantee that all PCI read and write operations\r | |
104 | are serialized.\r | |
105 | \r | |
106 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
107 | \r | |
2fc59a00 | 108 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 109 | Register.\r |
110 | @param OrData The value to OR with the PCI configuration register.\r | |
111 | \r | |
112 | @return The value written back to the PCI configuration register.\r | |
113 | \r | |
114 | **/\r | |
115 | UINT8\r | |
116 | EFIAPI\r | |
117 | PciOr8 (\r | |
2f88bd3a MK |
118 | IN UINTN Address,\r |
119 | IN UINT8 OrData\r | |
e1f414b6 | 120 | )\r |
121 | {\r | |
122 | return PciExpressOr8 (Address, OrData);\r | |
123 | }\r | |
124 | \r | |
125 | /**\r | |
126 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
127 | value.\r | |
128 | \r | |
129 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
130 | bitwise AND between the read result and the value specified by AndData, and\r | |
131 | writes the result to the 8-bit PCI configuration register specified by\r | |
132 | Address. The value written to the PCI configuration register is returned.\r | |
133 | This function must guarantee that all PCI read and write operations are\r | |
134 | serialized.\r | |
135 | \r | |
136 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
137 | \r | |
2fc59a00 | 138 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 139 | Register.\r |
140 | @param AndData The value to AND with the PCI configuration register.\r | |
141 | \r | |
142 | @return The value written back to the PCI configuration register.\r | |
143 | \r | |
144 | **/\r | |
145 | UINT8\r | |
146 | EFIAPI\r | |
147 | PciAnd8 (\r | |
2f88bd3a MK |
148 | IN UINTN Address,\r |
149 | IN UINT8 AndData\r | |
e1f414b6 | 150 | )\r |
151 | {\r | |
152 | return PciExpressAnd8 (Address, AndData);\r | |
153 | }\r | |
154 | \r | |
155 | /**\r | |
156 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
62991af2 | 157 | value, followed a bitwise OR with another 8-bit value.\r |
e1f414b6 | 158 | \r |
159 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
160 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 161 | performs a bitwise OR between the result of the AND operation and\r |
e1f414b6 | 162 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
163 | configuration register specified by Address. The value written to the PCI\r | |
164 | configuration register is returned. This function must guarantee that all PCI\r | |
165 | read and write operations are serialized.\r | |
166 | \r | |
167 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
168 | \r | |
2fc59a00 | 169 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 170 | Register.\r |
171 | @param AndData The value to AND with the PCI configuration register.\r | |
172 | @param OrData The value to OR with the result of the AND operation.\r | |
173 | \r | |
174 | @return The value written back to the PCI configuration register.\r | |
175 | \r | |
176 | **/\r | |
177 | UINT8\r | |
178 | EFIAPI\r | |
179 | PciAndThenOr8 (\r | |
2f88bd3a MK |
180 | IN UINTN Address,\r |
181 | IN UINT8 AndData,\r | |
182 | IN UINT8 OrData\r | |
e1f414b6 | 183 | )\r |
184 | {\r | |
185 | return PciExpressAndThenOr8 (Address, AndData, OrData);\r | |
186 | }\r | |
187 | \r | |
188 | /**\r | |
189 | Reads a bit field of a PCI configuration register.\r | |
190 | \r | |
191 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
192 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
193 | returned.\r | |
194 | \r | |
195 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
196 | If StartBit is greater than 7, then ASSERT().\r | |
197 | If EndBit is greater than 7, then ASSERT().\r | |
198 | If EndBit is less than StartBit, then ASSERT().\r | |
199 | \r | |
2fc59a00 | 200 | @param Address The PCI configuration register to read.\r |
e1f414b6 | 201 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
202 | Range 0..7.\r | |
203 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
204 | Range 0..7.\r | |
205 | \r | |
206 | @return The value of the bit field read from the PCI configuration register.\r | |
207 | \r | |
208 | **/\r | |
209 | UINT8\r | |
210 | EFIAPI\r | |
211 | PciBitFieldRead8 (\r | |
2f88bd3a MK |
212 | IN UINTN Address,\r |
213 | IN UINTN StartBit,\r | |
214 | IN UINTN EndBit\r | |
e1f414b6 | 215 | )\r |
216 | {\r | |
217 | return PciExpressBitFieldRead8 (Address, StartBit, EndBit);\r | |
218 | }\r | |
219 | \r | |
220 | /**\r | |
221 | Writes a bit field to a PCI configuration register.\r | |
222 | \r | |
223 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
224 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
225 | destination PCI configuration register are preserved. The new value of the\r | |
226 | 8-bit register is returned.\r | |
227 | \r | |
228 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
229 | If StartBit is greater than 7, then ASSERT().\r | |
230 | If EndBit is greater than 7, then ASSERT().\r | |
231 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 232 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 233 | \r |
2fc59a00 | 234 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 235 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
236 | Range 0..7.\r | |
237 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
238 | Range 0..7.\r | |
2fc59a00 | 239 | @param Value The new value of the bit field.\r |
e1f414b6 | 240 | \r |
241 | @return The value written back to the PCI configuration register.\r | |
242 | \r | |
243 | **/\r | |
244 | UINT8\r | |
245 | EFIAPI\r | |
246 | PciBitFieldWrite8 (\r | |
2f88bd3a MK |
247 | IN UINTN Address,\r |
248 | IN UINTN StartBit,\r | |
249 | IN UINTN EndBit,\r | |
250 | IN UINT8 Value\r | |
e1f414b6 | 251 | )\r |
252 | {\r | |
253 | return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value);\r | |
254 | }\r | |
255 | \r | |
256 | /**\r | |
257 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
258 | writes the result back to the bit field in the 8-bit port.\r | |
259 | \r | |
260 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 261 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 262 | OrData, and writes the result to the 8-bit PCI configuration register\r |
263 | specified by Address. The value written to the PCI configuration register is\r | |
264 | returned. This function must guarantee that all PCI read and write operations\r | |
265 | are serialized. Extra left bits in OrData are stripped.\r | |
266 | \r | |
267 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
268 | If StartBit is greater than 7, then ASSERT().\r | |
269 | If EndBit is greater than 7, then ASSERT().\r | |
270 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 271 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 272 | \r |
2fc59a00 | 273 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 274 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
275 | Range 0..7.\r | |
276 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
277 | Range 0..7.\r | |
278 | @param OrData The value to OR with the PCI configuration register.\r | |
279 | \r | |
280 | @return The value written back to the PCI configuration register.\r | |
281 | \r | |
282 | **/\r | |
283 | UINT8\r | |
284 | EFIAPI\r | |
285 | PciBitFieldOr8 (\r | |
2f88bd3a MK |
286 | IN UINTN Address,\r |
287 | IN UINTN StartBit,\r | |
288 | IN UINTN EndBit,\r | |
289 | IN UINT8 OrData\r | |
e1f414b6 | 290 | )\r |
291 | {\r | |
292 | return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData);\r | |
293 | }\r | |
294 | \r | |
295 | /**\r | |
296 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
297 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
298 | \r | |
299 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
300 | bitwise AND between the read result and the value specified by AndData, and\r | |
301 | writes the result to the 8-bit PCI configuration register specified by\r | |
302 | Address. The value written to the PCI configuration register is returned.\r | |
303 | This function must guarantee that all PCI read and write operations are\r | |
304 | serialized. Extra left bits in AndData are stripped.\r | |
305 | \r | |
306 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
307 | If StartBit is greater than 7, then ASSERT().\r | |
308 | If EndBit is greater than 7, then ASSERT().\r | |
309 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 310 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 311 | \r |
2fc59a00 | 312 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 313 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
314 | Range 0..7.\r | |
315 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
316 | Range 0..7.\r | |
317 | @param AndData The value to AND with the PCI configuration register.\r | |
318 | \r | |
319 | @return The value written back to the PCI configuration register.\r | |
320 | \r | |
321 | **/\r | |
322 | UINT8\r | |
323 | EFIAPI\r | |
324 | PciBitFieldAnd8 (\r | |
2f88bd3a MK |
325 | IN UINTN Address,\r |
326 | IN UINTN StartBit,\r | |
327 | IN UINTN EndBit,\r | |
328 | IN UINT8 AndData\r | |
e1f414b6 | 329 | )\r |
330 | {\r | |
331 | return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData);\r | |
332 | }\r | |
333 | \r | |
334 | /**\r | |
335 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 336 | bitwise OR, and writes the result back to the bit field in the\r |
e1f414b6 | 337 | 8-bit port.\r |
338 | \r | |
339 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 340 | bitwise AND followed by a bitwise OR between the read result and\r |
e1f414b6 | 341 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
342 | configuration register specified by Address. The value written to the PCI\r | |
343 | configuration register is returned. This function must guarantee that all PCI\r | |
344 | read and write operations are serialized. Extra left bits in both AndData and\r | |
345 | OrData are stripped.\r | |
346 | \r | |
347 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
348 | If StartBit is greater than 7, then ASSERT().\r | |
349 | If EndBit is greater than 7, then ASSERT().\r | |
350 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
351 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
352 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
e1f414b6 | 353 | \r |
2fc59a00 | 354 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 355 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
356 | Range 0..7.\r | |
357 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
358 | Range 0..7.\r | |
359 | @param AndData The value to AND with the PCI configuration register.\r | |
360 | @param OrData The value to OR with the result of the AND operation.\r | |
361 | \r | |
362 | @return The value written back to the PCI configuration register.\r | |
363 | \r | |
364 | **/\r | |
365 | UINT8\r | |
366 | EFIAPI\r | |
367 | PciBitFieldAndThenOr8 (\r | |
2f88bd3a MK |
368 | IN UINTN Address,\r |
369 | IN UINTN StartBit,\r | |
370 | IN UINTN EndBit,\r | |
371 | IN UINT8 AndData,\r | |
372 | IN UINT8 OrData\r | |
e1f414b6 | 373 | )\r |
374 | {\r | |
375 | return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);\r | |
376 | }\r | |
377 | \r | |
378 | /**\r | |
379 | Reads a 16-bit PCI configuration register.\r | |
380 | \r | |
381 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
382 | This function must guarantee that all PCI read and write operations are\r | |
383 | serialized.\r | |
384 | \r | |
385 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 386 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 387 | \r |
2fc59a00 | 388 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 389 | Register.\r |
390 | \r | |
391 | @return The read value from the PCI configuration register.\r | |
392 | \r | |
393 | **/\r | |
394 | UINT16\r | |
395 | EFIAPI\r | |
396 | PciRead16 (\r | |
2f88bd3a | 397 | IN UINTN Address\r |
e1f414b6 | 398 | )\r |
399 | {\r | |
400 | return PciExpressRead16 (Address);\r | |
401 | }\r | |
402 | \r | |
403 | /**\r | |
404 | Writes a 16-bit PCI configuration register.\r | |
405 | \r | |
406 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
407 | value specified by Value. Value is returned. This function must guarantee\r | |
408 | that all PCI read and write operations are serialized.\r | |
409 | \r | |
410 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 411 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 412 | \r |
2fc59a00 | 413 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 414 | Register.\r |
9638ba6d | 415 | @param Value The value to write.\r |
e1f414b6 | 416 | \r |
417 | @return The value written to the PCI configuration register.\r | |
418 | \r | |
419 | **/\r | |
420 | UINT16\r | |
421 | EFIAPI\r | |
422 | PciWrite16 (\r | |
2f88bd3a MK |
423 | IN UINTN Address,\r |
424 | IN UINT16 Value\r | |
e1f414b6 | 425 | )\r |
426 | {\r | |
94646ec0 | 427 | return PciExpressWrite16 (Address, Value);\r |
e1f414b6 | 428 | }\r |
429 | \r | |
430 | /**\r | |
62991af2 | 431 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
e1f414b6 | 432 | a 16-bit value.\r |
433 | \r | |
434 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 435 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 436 | OrData, and writes the result to the 16-bit PCI configuration register\r |
437 | specified by Address. The value written to the PCI configuration register is\r | |
438 | returned. This function must guarantee that all PCI read and write operations\r | |
439 | are serialized.\r | |
440 | \r | |
441 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 442 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 443 | \r |
2fc59a00 | 444 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 445 | Register.\r |
446 | @param OrData The value to OR with the PCI configuration register.\r | |
447 | \r | |
448 | @return The value written back to the PCI configuration register.\r | |
449 | \r | |
450 | **/\r | |
451 | UINT16\r | |
452 | EFIAPI\r | |
453 | PciOr16 (\r | |
2f88bd3a MK |
454 | IN UINTN Address,\r |
455 | IN UINT16 OrData\r | |
e1f414b6 | 456 | )\r |
457 | {\r | |
458 | return PciExpressOr16 (Address, OrData);\r | |
459 | }\r | |
460 | \r | |
461 | /**\r | |
462 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
463 | value.\r | |
464 | \r | |
465 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
466 | bitwise AND between the read result and the value specified by AndData, and\r | |
467 | writes the result to the 16-bit PCI configuration register specified by\r | |
468 | Address. The value written to the PCI configuration register is returned.\r | |
469 | This function must guarantee that all PCI read and write operations are\r | |
470 | serialized.\r | |
471 | \r | |
472 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 473 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 474 | \r |
2fc59a00 | 475 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 476 | Register.\r |
477 | @param AndData The value to AND with the PCI configuration register.\r | |
478 | \r | |
479 | @return The value written back to the PCI configuration register.\r | |
480 | \r | |
481 | **/\r | |
482 | UINT16\r | |
483 | EFIAPI\r | |
484 | PciAnd16 (\r | |
2f88bd3a MK |
485 | IN UINTN Address,\r |
486 | IN UINT16 AndData\r | |
e1f414b6 | 487 | )\r |
488 | {\r | |
489 | return PciExpressAnd16 (Address, AndData);\r | |
490 | }\r | |
491 | \r | |
492 | /**\r | |
493 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
62991af2 | 494 | value, followed a bitwise OR with another 16-bit value.\r |
e1f414b6 | 495 | \r |
496 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
497 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 498 | performs a bitwise OR between the result of the AND operation and\r |
e1f414b6 | 499 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
500 | configuration register specified by Address. The value written to the PCI\r | |
501 | configuration register is returned. This function must guarantee that all PCI\r | |
502 | read and write operations are serialized.\r | |
503 | \r | |
504 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 505 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 506 | \r |
2fc59a00 | 507 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 508 | Register.\r |
509 | @param AndData The value to AND with the PCI configuration register.\r | |
510 | @param OrData The value to OR with the result of the AND operation.\r | |
511 | \r | |
512 | @return The value written back to the PCI configuration register.\r | |
513 | \r | |
514 | **/\r | |
515 | UINT16\r | |
516 | EFIAPI\r | |
517 | PciAndThenOr16 (\r | |
2f88bd3a MK |
518 | IN UINTN Address,\r |
519 | IN UINT16 AndData,\r | |
520 | IN UINT16 OrData\r | |
e1f414b6 | 521 | )\r |
522 | {\r | |
523 | return PciExpressAndThenOr16 (Address, AndData, OrData);\r | |
524 | }\r | |
525 | \r | |
526 | /**\r | |
527 | Reads a bit field of a PCI configuration register.\r | |
528 | \r | |
529 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
530 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
531 | returned.\r | |
532 | \r | |
533 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 534 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 535 | If StartBit is greater than 15, then ASSERT().\r |
536 | If EndBit is greater than 15, then ASSERT().\r | |
537 | If EndBit is less than StartBit, then ASSERT().\r | |
538 | \r | |
2fc59a00 | 539 | @param Address The PCI configuration register to read.\r |
e1f414b6 | 540 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
541 | Range 0..15.\r | |
542 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
543 | Range 0..15.\r | |
544 | \r | |
545 | @return The value of the bit field read from the PCI configuration register.\r | |
546 | \r | |
547 | **/\r | |
548 | UINT16\r | |
549 | EFIAPI\r | |
550 | PciBitFieldRead16 (\r | |
2f88bd3a MK |
551 | IN UINTN Address,\r |
552 | IN UINTN StartBit,\r | |
553 | IN UINTN EndBit\r | |
e1f414b6 | 554 | )\r |
555 | {\r | |
556 | return PciExpressBitFieldRead16 (Address, StartBit, EndBit);\r | |
557 | }\r | |
558 | \r | |
559 | /**\r | |
560 | Writes a bit field to a PCI configuration register.\r | |
561 | \r | |
562 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
563 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
564 | destination PCI configuration register are preserved. The new value of the\r | |
565 | 16-bit register is returned.\r | |
566 | \r | |
567 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 568 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 569 | If StartBit is greater than 15, then ASSERT().\r |
570 | If EndBit is greater than 15, then ASSERT().\r | |
571 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 572 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 573 | \r |
2fc59a00 | 574 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 575 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
576 | Range 0..15.\r | |
577 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
578 | Range 0..15.\r | |
2fc59a00 | 579 | @param Value The new value of the bit field.\r |
e1f414b6 | 580 | \r |
581 | @return The value written back to the PCI configuration register.\r | |
582 | \r | |
583 | **/\r | |
584 | UINT16\r | |
585 | EFIAPI\r | |
586 | PciBitFieldWrite16 (\r | |
2f88bd3a MK |
587 | IN UINTN Address,\r |
588 | IN UINTN StartBit,\r | |
589 | IN UINTN EndBit,\r | |
590 | IN UINT16 Value\r | |
e1f414b6 | 591 | )\r |
592 | {\r | |
593 | return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value);\r | |
594 | }\r | |
595 | \r | |
596 | /**\r | |
597 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
598 | writes the result back to the bit field in the 16-bit port.\r | |
599 | \r | |
600 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 601 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 602 | OrData, and writes the result to the 16-bit PCI configuration register\r |
603 | specified by Address. The value written to the PCI configuration register is\r | |
604 | returned. This function must guarantee that all PCI read and write operations\r | |
605 | are serialized. Extra left bits in OrData are stripped.\r | |
606 | \r | |
607 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 608 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 609 | If StartBit is greater than 15, then ASSERT().\r |
610 | If EndBit is greater than 15, then ASSERT().\r | |
611 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 612 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 613 | \r |
2fc59a00 | 614 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 615 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
616 | Range 0..15.\r | |
617 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
618 | Range 0..15.\r | |
619 | @param OrData The value to OR with the PCI configuration register.\r | |
620 | \r | |
621 | @return The value written back to the PCI configuration register.\r | |
622 | \r | |
623 | **/\r | |
624 | UINT16\r | |
625 | EFIAPI\r | |
626 | PciBitFieldOr16 (\r | |
2f88bd3a MK |
627 | IN UINTN Address,\r |
628 | IN UINTN StartBit,\r | |
629 | IN UINTN EndBit,\r | |
630 | IN UINT16 OrData\r | |
e1f414b6 | 631 | )\r |
632 | {\r | |
633 | return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData);\r | |
634 | }\r | |
635 | \r | |
636 | /**\r | |
637 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
638 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
639 | \r | |
640 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
641 | bitwise AND between the read result and the value specified by AndData, and\r | |
642 | writes the result to the 16-bit PCI configuration register specified by\r | |
643 | Address. The value written to the PCI configuration register is returned.\r | |
644 | This function must guarantee that all PCI read and write operations are\r | |
645 | serialized. Extra left bits in AndData are stripped.\r | |
646 | \r | |
647 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 648 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 649 | If StartBit is greater than 15, then ASSERT().\r |
650 | If EndBit is greater than 15, then ASSERT().\r | |
651 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 652 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 653 | \r |
2fc59a00 | 654 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 655 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
656 | Range 0..15.\r | |
657 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
658 | Range 0..15.\r | |
659 | @param AndData The value to AND with the PCI configuration register.\r | |
660 | \r | |
661 | @return The value written back to the PCI configuration register.\r | |
662 | \r | |
663 | **/\r | |
664 | UINT16\r | |
665 | EFIAPI\r | |
666 | PciBitFieldAnd16 (\r | |
2f88bd3a MK |
667 | IN UINTN Address,\r |
668 | IN UINTN StartBit,\r | |
669 | IN UINTN EndBit,\r | |
670 | IN UINT16 AndData\r | |
e1f414b6 | 671 | )\r |
672 | {\r | |
673 | return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData);\r | |
674 | }\r | |
675 | \r | |
676 | /**\r | |
677 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 678 | bitwise OR, and writes the result back to the bit field in the\r |
e1f414b6 | 679 | 16-bit port.\r |
680 | \r | |
681 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 682 | bitwise AND followed by a bitwise OR between the read result and\r |
e1f414b6 | 683 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
684 | configuration register specified by Address. The value written to the PCI\r | |
685 | configuration register is returned. This function must guarantee that all PCI\r | |
686 | read and write operations are serialized. Extra left bits in both AndData and\r | |
687 | OrData are stripped.\r | |
688 | \r | |
689 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 690 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 691 | If StartBit is greater than 15, then ASSERT().\r |
692 | If EndBit is greater than 15, then ASSERT().\r | |
693 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
694 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
695 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
e1f414b6 | 696 | \r |
2fc59a00 | 697 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 698 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
699 | Range 0..15.\r | |
700 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
701 | Range 0..15.\r | |
702 | @param AndData The value to AND with the PCI configuration register.\r | |
703 | @param OrData The value to OR with the result of the AND operation.\r | |
704 | \r | |
705 | @return The value written back to the PCI configuration register.\r | |
706 | \r | |
707 | **/\r | |
708 | UINT16\r | |
709 | EFIAPI\r | |
710 | PciBitFieldAndThenOr16 (\r | |
2f88bd3a MK |
711 | IN UINTN Address,\r |
712 | IN UINTN StartBit,\r | |
713 | IN UINTN EndBit,\r | |
714 | IN UINT16 AndData,\r | |
715 | IN UINT16 OrData\r | |
e1f414b6 | 716 | )\r |
717 | {\r | |
718 | return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);\r | |
719 | }\r | |
720 | \r | |
721 | /**\r | |
722 | Reads a 32-bit PCI configuration register.\r | |
723 | \r | |
724 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
725 | This function must guarantee that all PCI read and write operations are\r | |
726 | serialized.\r | |
727 | \r | |
728 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 729 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 730 | \r |
2fc59a00 | 731 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 732 | Register.\r |
733 | \r | |
734 | @return The read value from the PCI configuration register.\r | |
735 | \r | |
736 | **/\r | |
737 | UINT32\r | |
738 | EFIAPI\r | |
739 | PciRead32 (\r | |
2f88bd3a | 740 | IN UINTN Address\r |
e1f414b6 | 741 | )\r |
742 | {\r | |
743 | return PciExpressRead32 (Address);\r | |
744 | }\r | |
745 | \r | |
746 | /**\r | |
747 | Writes a 32-bit PCI configuration register.\r | |
748 | \r | |
749 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
750 | value specified by Value. Value is returned. This function must guarantee\r | |
751 | that all PCI read and write operations are serialized.\r | |
752 | \r | |
753 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 754 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 755 | \r |
2fc59a00 | 756 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 757 | Register.\r |
7612cbf0 | 758 | @param Value The value to write.\r |
e1f414b6 | 759 | \r |
760 | @return The value written to the PCI configuration register.\r | |
761 | \r | |
762 | **/\r | |
763 | UINT32\r | |
764 | EFIAPI\r | |
765 | PciWrite32 (\r | |
2f88bd3a MK |
766 | IN UINTN Address,\r |
767 | IN UINT32 Value\r | |
e1f414b6 | 768 | )\r |
769 | {\r | |
94646ec0 | 770 | return PciExpressWrite32 (Address, Value);\r |
e1f414b6 | 771 | }\r |
772 | \r | |
773 | /**\r | |
62991af2 | 774 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
e1f414b6 | 775 | a 32-bit value.\r |
776 | \r | |
777 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 778 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 779 | OrData, and writes the result to the 32-bit PCI configuration register\r |
780 | specified by Address. The value written to the PCI configuration register is\r | |
781 | returned. This function must guarantee that all PCI read and write operations\r | |
782 | are serialized.\r | |
783 | \r | |
784 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 785 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 786 | \r |
2fc59a00 | 787 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 788 | Register.\r |
789 | @param OrData The value to OR with the PCI configuration register.\r | |
790 | \r | |
791 | @return The value written back to the PCI configuration register.\r | |
792 | \r | |
793 | **/\r | |
794 | UINT32\r | |
795 | EFIAPI\r | |
796 | PciOr32 (\r | |
2f88bd3a MK |
797 | IN UINTN Address,\r |
798 | IN UINT32 OrData\r | |
e1f414b6 | 799 | )\r |
800 | {\r | |
801 | return PciExpressOr32 (Address, OrData);\r | |
802 | }\r | |
803 | \r | |
804 | /**\r | |
805 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
806 | value.\r | |
807 | \r | |
808 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
809 | bitwise AND between the read result and the value specified by AndData, and\r | |
810 | writes the result to the 32-bit PCI configuration register specified by\r | |
811 | Address. The value written to the PCI configuration register is returned.\r | |
812 | This function must guarantee that all PCI read and write operations are\r | |
813 | serialized.\r | |
814 | \r | |
815 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 816 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 817 | \r |
2fc59a00 | 818 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 819 | Register.\r |
820 | @param AndData The value to AND with the PCI configuration register.\r | |
821 | \r | |
822 | @return The value written back to the PCI configuration register.\r | |
823 | \r | |
824 | **/\r | |
825 | UINT32\r | |
826 | EFIAPI\r | |
827 | PciAnd32 (\r | |
2f88bd3a MK |
828 | IN UINTN Address,\r |
829 | IN UINT32 AndData\r | |
e1f414b6 | 830 | )\r |
831 | {\r | |
832 | return PciExpressAnd32 (Address, AndData);\r | |
833 | }\r | |
834 | \r | |
835 | /**\r | |
836 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
62991af2 | 837 | value, followed a bitwise OR with another 32-bit value.\r |
e1f414b6 | 838 | \r |
839 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
840 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 841 | performs a bitwise OR between the result of the AND operation and\r |
e1f414b6 | 842 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
843 | configuration register specified by Address. The value written to the PCI\r | |
844 | configuration register is returned. This function must guarantee that all PCI\r | |
845 | read and write operations are serialized.\r | |
846 | \r | |
847 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 848 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 849 | \r |
2fc59a00 | 850 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 851 | Register.\r |
852 | @param AndData The value to AND with the PCI configuration register.\r | |
853 | @param OrData The value to OR with the result of the AND operation.\r | |
854 | \r | |
855 | @return The value written back to the PCI configuration register.\r | |
856 | \r | |
857 | **/\r | |
858 | UINT32\r | |
859 | EFIAPI\r | |
860 | PciAndThenOr32 (\r | |
2f88bd3a MK |
861 | IN UINTN Address,\r |
862 | IN UINT32 AndData,\r | |
863 | IN UINT32 OrData\r | |
e1f414b6 | 864 | )\r |
865 | {\r | |
866 | return PciExpressAndThenOr32 (Address, AndData, OrData);\r | |
867 | }\r | |
868 | \r | |
869 | /**\r | |
870 | Reads a bit field of a PCI configuration register.\r | |
871 | \r | |
872 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
873 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
874 | returned.\r | |
875 | \r | |
876 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 877 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 878 | If StartBit is greater than 31, then ASSERT().\r |
879 | If EndBit is greater than 31, then ASSERT().\r | |
880 | If EndBit is less than StartBit, then ASSERT().\r | |
881 | \r | |
2fc59a00 | 882 | @param Address The PCI configuration register to read.\r |
e1f414b6 | 883 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
884 | Range 0..31.\r | |
885 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
886 | Range 0..31.\r | |
887 | \r | |
888 | @return The value of the bit field read from the PCI configuration register.\r | |
889 | \r | |
890 | **/\r | |
891 | UINT32\r | |
892 | EFIAPI\r | |
893 | PciBitFieldRead32 (\r | |
2f88bd3a MK |
894 | IN UINTN Address,\r |
895 | IN UINTN StartBit,\r | |
896 | IN UINTN EndBit\r | |
e1f414b6 | 897 | )\r |
898 | {\r | |
899 | return PciExpressBitFieldRead32 (Address, StartBit, EndBit);\r | |
900 | }\r | |
901 | \r | |
902 | /**\r | |
903 | Writes a bit field to a PCI configuration register.\r | |
904 | \r | |
905 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
906 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
907 | destination PCI configuration register are preserved. The new value of the\r | |
908 | 32-bit register is returned.\r | |
909 | \r | |
910 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 911 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 912 | If StartBit is greater than 31, then ASSERT().\r |
913 | If EndBit is greater than 31, then ASSERT().\r | |
914 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 915 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 916 | \r |
2fc59a00 | 917 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 918 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
919 | Range 0..31.\r | |
920 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
921 | Range 0..31.\r | |
2fc59a00 | 922 | @param Value The new value of the bit field.\r |
e1f414b6 | 923 | \r |
924 | @return The value written back to the PCI configuration register.\r | |
925 | \r | |
926 | **/\r | |
927 | UINT32\r | |
928 | EFIAPI\r | |
929 | PciBitFieldWrite32 (\r | |
2f88bd3a MK |
930 | IN UINTN Address,\r |
931 | IN UINTN StartBit,\r | |
932 | IN UINTN EndBit,\r | |
933 | IN UINT32 Value\r | |
e1f414b6 | 934 | )\r |
935 | {\r | |
936 | return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value);\r | |
937 | }\r | |
938 | \r | |
939 | /**\r | |
940 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
941 | writes the result back to the bit field in the 32-bit port.\r | |
942 | \r | |
943 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 944 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 945 | OrData, and writes the result to the 32-bit PCI configuration register\r |
946 | specified by Address. The value written to the PCI configuration register is\r | |
947 | returned. This function must guarantee that all PCI read and write operations\r | |
948 | are serialized. Extra left bits in OrData are stripped.\r | |
949 | \r | |
950 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 951 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 952 | If StartBit is greater than 31, then ASSERT().\r |
953 | If EndBit is greater than 31, then ASSERT().\r | |
954 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 955 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 956 | \r |
2fc59a00 | 957 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 958 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
959 | Range 0..31.\r | |
960 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
961 | Range 0..31.\r | |
962 | @param OrData The value to OR with the PCI configuration register.\r | |
963 | \r | |
964 | @return The value written back to the PCI configuration register.\r | |
965 | \r | |
966 | **/\r | |
967 | UINT32\r | |
968 | EFIAPI\r | |
969 | PciBitFieldOr32 (\r | |
2f88bd3a MK |
970 | IN UINTN Address,\r |
971 | IN UINTN StartBit,\r | |
972 | IN UINTN EndBit,\r | |
973 | IN UINT32 OrData\r | |
e1f414b6 | 974 | )\r |
975 | {\r | |
976 | return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData);\r | |
977 | }\r | |
978 | \r | |
979 | /**\r | |
980 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
981 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
982 | \r | |
983 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
984 | bitwise AND between the read result and the value specified by AndData, and\r | |
985 | writes the result to the 32-bit PCI configuration register specified by\r | |
986 | Address. The value written to the PCI configuration register is returned.\r | |
987 | This function must guarantee that all PCI read and write operations are\r | |
988 | serialized. Extra left bits in AndData are stripped.\r | |
989 | \r | |
990 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 991 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 992 | If StartBit is greater than 31, then ASSERT().\r |
993 | If EndBit is greater than 31, then ASSERT().\r | |
994 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 995 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 996 | \r |
2fc59a00 | 997 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 998 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
999 | Range 0..31.\r | |
1000 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1001 | Range 0..31.\r | |
1002 | @param AndData The value to AND with the PCI configuration register.\r | |
1003 | \r | |
1004 | @return The value written back to the PCI configuration register.\r | |
1005 | \r | |
1006 | **/\r | |
1007 | UINT32\r | |
1008 | EFIAPI\r | |
1009 | PciBitFieldAnd32 (\r | |
2f88bd3a MK |
1010 | IN UINTN Address,\r |
1011 | IN UINTN StartBit,\r | |
1012 | IN UINTN EndBit,\r | |
1013 | IN UINT32 AndData\r | |
e1f414b6 | 1014 | )\r |
1015 | {\r | |
1016 | return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData);\r | |
1017 | }\r | |
1018 | \r | |
1019 | /**\r | |
1020 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 1021 | bitwise OR, and writes the result back to the bit field in the\r |
e1f414b6 | 1022 | 32-bit port.\r |
1023 | \r | |
1024 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1025 | bitwise AND followed by a bitwise OR between the read result and\r |
e1f414b6 | 1026 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
1027 | configuration register specified by Address. The value written to the PCI\r | |
1028 | configuration register is returned. This function must guarantee that all PCI\r | |
1029 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1030 | OrData are stripped.\r | |
1031 | \r | |
1032 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 1033 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 1034 | If StartBit is greater than 31, then ASSERT().\r |
1035 | If EndBit is greater than 31, then ASSERT().\r | |
1036 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
1037 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1038 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
e1f414b6 | 1039 | \r |
2fc59a00 | 1040 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 1041 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1042 | Range 0..31.\r | |
1043 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1044 | Range 0..31.\r | |
1045 | @param AndData The value to AND with the PCI configuration register.\r | |
1046 | @param OrData The value to OR with the result of the AND operation.\r | |
1047 | \r | |
1048 | @return The value written back to the PCI configuration register.\r | |
1049 | \r | |
1050 | **/\r | |
1051 | UINT32\r | |
1052 | EFIAPI\r | |
1053 | PciBitFieldAndThenOr32 (\r | |
2f88bd3a MK |
1054 | IN UINTN Address,\r |
1055 | IN UINTN StartBit,\r | |
1056 | IN UINTN EndBit,\r | |
1057 | IN UINT32 AndData,\r | |
1058 | IN UINT32 OrData\r | |
e1f414b6 | 1059 | )\r |
1060 | {\r | |
1061 | return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);\r | |
1062 | }\r | |
1063 | \r | |
1064 | /**\r | |
1065 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1066 | \r | |
1067 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1068 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1069 | configuration registers from a single PCI function to be read. Size is\r | |
1070 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1071 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1072 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1073 | end of the range.\r | |
1074 | \r | |
1075 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1076 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1077 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1078 | \r | |
2fc59a00 | 1079 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r |
e1f414b6 | 1080 | Function and Register.\r |
2fc59a00 | 1081 | @param Size The size in bytes of the transfer.\r |
1082 | @param Buffer The pointer to a buffer receiving the data read.\r | |
e1f414b6 | 1083 | \r |
1084 | @return Size\r | |
1085 | \r | |
1086 | **/\r | |
1087 | UINTN\r | |
1088 | EFIAPI\r | |
1089 | PciReadBuffer (\r | |
2f88bd3a MK |
1090 | IN UINTN StartAddress,\r |
1091 | IN UINTN Size,\r | |
1092 | OUT VOID *Buffer\r | |
e1f414b6 | 1093 | )\r |
1094 | {\r | |
1095 | return PciExpressReadBuffer (StartAddress, Size, Buffer);\r | |
1096 | }\r | |
1097 | \r | |
1098 | /**\r | |
1099 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1100 | configuration space.\r | |
1101 | \r | |
1102 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1103 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1104 | configuration registers from a single PCI function to be written. Size is\r | |
1105 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1106 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1107 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1108 | and the end of the range.\r | |
1109 | \r | |
1110 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1111 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1112 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1113 | \r | |
2fc59a00 | 1114 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r |
e1f414b6 | 1115 | Function and Register.\r |
2fc59a00 | 1116 | @param Size The size in bytes of the transfer.\r |
1117 | @param Buffer The pointer to a buffer containing the data to write.\r | |
e1f414b6 | 1118 | \r |
efb23117 | 1119 | @return Size written to StartAddress.\r |
e1f414b6 | 1120 | \r |
1121 | **/\r | |
1122 | UINTN\r | |
1123 | EFIAPI\r | |
1124 | PciWriteBuffer (\r | |
2f88bd3a MK |
1125 | IN UINTN StartAddress,\r |
1126 | IN UINTN Size,\r | |
1127 | IN VOID *Buffer\r | |
e1f414b6 | 1128 | )\r |
1129 | {\r | |
1130 | return PciExpressWriteBuffer (StartAddress, Size, Buffer);\r | |
1131 | }\r |