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e1f414b6 | 1 | /** @file\r |
5c57f3ea | 2 | PCI Library functions that use the 256 MB PCI Express MMIO window to perform PCI\r |
3 | Configuration cycles. Layers on PCI Express Library.\r | |
e1f414b6 | 4 | \r |
94646ec0 | 5 | Copyright (c) 2006 - 2008, Intel Corporation<BR>\r |
e1f414b6 | 6 | All rights reserved. This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
e1f414b6 | 14 | **/\r |
15 | \r | |
c892d846 | 16 | \r |
c7d265a9 | 17 | #include <Base.h>\r |
c892d846 | 18 | \r |
c7d265a9 | 19 | #include <Library/PciLib.h>\r |
20 | #include <Library/PciExpressLib.h>\r | |
e1f414b6 | 21 | \r |
3e3ae634 | 22 | /**\r |
d11195a3 | 23 | Registers a PCI device so PCI configuration registers may be accessed after \r |
3e3ae634 | 24 | SetVirtualAddressMap().\r |
25 | \r | |
d11195a3 | 26 | Registers the PCI device specified by Address so all the PCI configuration registers \r |
27 | associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r | |
28 | \r | |
3e3ae634 | 29 | If Address > 0x0FFFFFFF, then ASSERT().\r |
30 | \r | |
31 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
32 | Register.\r | |
33 | \r | |
34 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
35 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
36 | after ExitBootServices().\r | |
37 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
38 | at runtime could not be mapped.\r | |
39 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
40 | complete the registration.\r | |
41 | \r | |
42 | **/\r | |
43 | RETURN_STATUS\r | |
44 | EFIAPI\r | |
45 | PciRegisterForRuntimeAccess (\r | |
46 | IN UINTN Address\r | |
47 | )\r | |
48 | {\r | |
49 | return PciExpressRegisterForRuntimeAccess (Address);\r | |
50 | }\r | |
51 | \r | |
e1f414b6 | 52 | /**\r |
53 | Reads an 8-bit PCI configuration register.\r | |
54 | \r | |
55 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
56 | This function must guarantee that all PCI read and write operations are\r | |
57 | serialized.\r | |
58 | \r | |
59 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
60 | \r | |
61 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
62 | Register.\r | |
63 | \r | |
64 | @return The read value from the PCI configuration register.\r | |
65 | \r | |
66 | **/\r | |
67 | UINT8\r | |
68 | EFIAPI\r | |
69 | PciRead8 (\r | |
70 | IN UINTN Address\r | |
71 | )\r | |
72 | {\r | |
73 | return PciExpressRead8 (Address);\r | |
74 | }\r | |
75 | \r | |
76 | /**\r | |
77 | Writes an 8-bit PCI configuration register.\r | |
78 | \r | |
79 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
80 | value specified by Value. Value is returned. This function must guarantee\r | |
81 | that all PCI read and write operations are serialized.\r | |
82 | \r | |
83 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
84 | \r | |
85 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
86 | Register.\r | |
7612cbf0 | 87 | @param Value The value to write.\r |
e1f414b6 | 88 | \r |
89 | @return The value written to the PCI configuration register.\r | |
90 | \r | |
91 | **/\r | |
92 | UINT8\r | |
93 | EFIAPI\r | |
94 | PciWrite8 (\r | |
95 | IN UINTN Address,\r | |
94646ec0 | 96 | IN UINT8 Value\r |
e1f414b6 | 97 | )\r |
98 | {\r | |
94646ec0 | 99 | return PciExpressWrite8 (Address, Value);\r |
e1f414b6 | 100 | }\r |
101 | \r | |
102 | /**\r | |
62991af2 | 103 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
e1f414b6 | 104 | an 8-bit value.\r |
105 | \r | |
106 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 107 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 108 | OrData, and writes the result to the 8-bit PCI configuration register\r |
109 | specified by Address. The value written to the PCI configuration register is\r | |
110 | returned. This function must guarantee that all PCI read and write operations\r | |
111 | are serialized.\r | |
112 | \r | |
113 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
114 | \r | |
115 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
116 | Register.\r | |
117 | @param OrData The value to OR with the PCI configuration register.\r | |
118 | \r | |
119 | @return The value written back to the PCI configuration register.\r | |
120 | \r | |
121 | **/\r | |
122 | UINT8\r | |
123 | EFIAPI\r | |
124 | PciOr8 (\r | |
125 | IN UINTN Address,\r | |
126 | IN UINT8 OrData\r | |
127 | )\r | |
128 | {\r | |
129 | return PciExpressOr8 (Address, OrData);\r | |
130 | }\r | |
131 | \r | |
132 | /**\r | |
133 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
134 | value.\r | |
135 | \r | |
136 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
137 | bitwise AND between the read result and the value specified by AndData, and\r | |
138 | writes the result to the 8-bit PCI configuration register specified by\r | |
139 | Address. The value written to the PCI configuration register is returned.\r | |
140 | This function must guarantee that all PCI read and write operations are\r | |
141 | serialized.\r | |
142 | \r | |
143 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
144 | \r | |
145 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
146 | Register.\r | |
147 | @param AndData The value to AND with the PCI configuration register.\r | |
148 | \r | |
149 | @return The value written back to the PCI configuration register.\r | |
150 | \r | |
151 | **/\r | |
152 | UINT8\r | |
153 | EFIAPI\r | |
154 | PciAnd8 (\r | |
155 | IN UINTN Address,\r | |
156 | IN UINT8 AndData\r | |
157 | )\r | |
158 | {\r | |
159 | return PciExpressAnd8 (Address, AndData);\r | |
160 | }\r | |
161 | \r | |
162 | /**\r | |
163 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
62991af2 | 164 | value, followed a bitwise OR with another 8-bit value.\r |
e1f414b6 | 165 | \r |
166 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
167 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 168 | performs a bitwise OR between the result of the AND operation and\r |
e1f414b6 | 169 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
170 | configuration register specified by Address. The value written to the PCI\r | |
171 | configuration register is returned. This function must guarantee that all PCI\r | |
172 | read and write operations are serialized.\r | |
173 | \r | |
174 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
175 | \r | |
176 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
177 | Register.\r | |
178 | @param AndData The value to AND with the PCI configuration register.\r | |
179 | @param OrData The value to OR with the result of the AND operation.\r | |
180 | \r | |
181 | @return The value written back to the PCI configuration register.\r | |
182 | \r | |
183 | **/\r | |
184 | UINT8\r | |
185 | EFIAPI\r | |
186 | PciAndThenOr8 (\r | |
187 | IN UINTN Address,\r | |
188 | IN UINT8 AndData,\r | |
189 | IN UINT8 OrData\r | |
190 | )\r | |
191 | {\r | |
192 | return PciExpressAndThenOr8 (Address, AndData, OrData);\r | |
193 | }\r | |
194 | \r | |
195 | /**\r | |
196 | Reads a bit field of a PCI configuration register.\r | |
197 | \r | |
198 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
199 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
200 | returned.\r | |
201 | \r | |
202 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
203 | If StartBit is greater than 7, then ASSERT().\r | |
204 | If EndBit is greater than 7, then ASSERT().\r | |
205 | If EndBit is less than StartBit, then ASSERT().\r | |
206 | \r | |
207 | @param Address PCI configuration register to read.\r | |
208 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
209 | Range 0..7.\r | |
210 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
211 | Range 0..7.\r | |
212 | \r | |
213 | @return The value of the bit field read from the PCI configuration register.\r | |
214 | \r | |
215 | **/\r | |
216 | UINT8\r | |
217 | EFIAPI\r | |
218 | PciBitFieldRead8 (\r | |
219 | IN UINTN Address,\r | |
220 | IN UINTN StartBit,\r | |
221 | IN UINTN EndBit\r | |
222 | )\r | |
223 | {\r | |
224 | return PciExpressBitFieldRead8 (Address, StartBit, EndBit);\r | |
225 | }\r | |
226 | \r | |
227 | /**\r | |
228 | Writes a bit field to a PCI configuration register.\r | |
229 | \r | |
230 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
231 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
232 | destination PCI configuration register are preserved. The new value of the\r | |
233 | 8-bit register is returned.\r | |
234 | \r | |
235 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
236 | If StartBit is greater than 7, then ASSERT().\r | |
237 | If EndBit is greater than 7, then ASSERT().\r | |
238 | If EndBit is less than StartBit, then ASSERT().\r | |
239 | \r | |
240 | @param Address PCI configuration register to write.\r | |
241 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
242 | Range 0..7.\r | |
243 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
244 | Range 0..7.\r | |
245 | @param Value New value of the bit field.\r | |
246 | \r | |
247 | @return The value written back to the PCI configuration register.\r | |
248 | \r | |
249 | **/\r | |
250 | UINT8\r | |
251 | EFIAPI\r | |
252 | PciBitFieldWrite8 (\r | |
253 | IN UINTN Address,\r | |
254 | IN UINTN StartBit,\r | |
255 | IN UINTN EndBit,\r | |
256 | IN UINT8 Value\r | |
257 | )\r | |
258 | {\r | |
259 | return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value);\r | |
260 | }\r | |
261 | \r | |
262 | /**\r | |
263 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
264 | writes the result back to the bit field in the 8-bit port.\r | |
265 | \r | |
266 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 267 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 268 | OrData, and writes the result to the 8-bit PCI configuration register\r |
269 | specified by Address. The value written to the PCI configuration register is\r | |
270 | returned. This function must guarantee that all PCI read and write operations\r | |
271 | are serialized. Extra left bits in OrData are stripped.\r | |
272 | \r | |
273 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
274 | If StartBit is greater than 7, then ASSERT().\r | |
275 | If EndBit is greater than 7, then ASSERT().\r | |
276 | If EndBit is less than StartBit, then ASSERT().\r | |
277 | \r | |
278 | @param Address PCI configuration register to write.\r | |
279 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
280 | Range 0..7.\r | |
281 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
282 | Range 0..7.\r | |
283 | @param OrData The value to OR with the PCI configuration register.\r | |
284 | \r | |
285 | @return The value written back to the PCI configuration register.\r | |
286 | \r | |
287 | **/\r | |
288 | UINT8\r | |
289 | EFIAPI\r | |
290 | PciBitFieldOr8 (\r | |
291 | IN UINTN Address,\r | |
292 | IN UINTN StartBit,\r | |
293 | IN UINTN EndBit,\r | |
294 | IN UINT8 OrData\r | |
295 | )\r | |
296 | {\r | |
297 | return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData);\r | |
298 | }\r | |
299 | \r | |
300 | /**\r | |
301 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
302 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
303 | \r | |
304 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
305 | bitwise AND between the read result and the value specified by AndData, and\r | |
306 | writes the result to the 8-bit PCI configuration register specified by\r | |
307 | Address. The value written to the PCI configuration register is returned.\r | |
308 | This function must guarantee that all PCI read and write operations are\r | |
309 | serialized. Extra left bits in AndData are stripped.\r | |
310 | \r | |
311 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
312 | If StartBit is greater than 7, then ASSERT().\r | |
313 | If EndBit is greater than 7, then ASSERT().\r | |
314 | If EndBit is less than StartBit, then ASSERT().\r | |
315 | \r | |
316 | @param Address PCI configuration register to write.\r | |
317 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
318 | Range 0..7.\r | |
319 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
320 | Range 0..7.\r | |
321 | @param AndData The value to AND with the PCI configuration register.\r | |
322 | \r | |
323 | @return The value written back to the PCI configuration register.\r | |
324 | \r | |
325 | **/\r | |
326 | UINT8\r | |
327 | EFIAPI\r | |
328 | PciBitFieldAnd8 (\r | |
329 | IN UINTN Address,\r | |
330 | IN UINTN StartBit,\r | |
331 | IN UINTN EndBit,\r | |
332 | IN UINT8 AndData\r | |
333 | )\r | |
334 | {\r | |
335 | return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData);\r | |
336 | }\r | |
337 | \r | |
338 | /**\r | |
339 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 340 | bitwise OR, and writes the result back to the bit field in the\r |
e1f414b6 | 341 | 8-bit port.\r |
342 | \r | |
343 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 344 | bitwise AND followed by a bitwise OR between the read result and\r |
e1f414b6 | 345 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
346 | configuration register specified by Address. The value written to the PCI\r | |
347 | configuration register is returned. This function must guarantee that all PCI\r | |
348 | read and write operations are serialized. Extra left bits in both AndData and\r | |
349 | OrData are stripped.\r | |
350 | \r | |
351 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
352 | If StartBit is greater than 7, then ASSERT().\r | |
353 | If EndBit is greater than 7, then ASSERT().\r | |
354 | If EndBit is less than StartBit, then ASSERT().\r | |
355 | \r | |
356 | @param Address PCI configuration register to write.\r | |
357 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
358 | Range 0..7.\r | |
359 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
360 | Range 0..7.\r | |
361 | @param AndData The value to AND with the PCI configuration register.\r | |
362 | @param OrData The value to OR with the result of the AND operation.\r | |
363 | \r | |
364 | @return The value written back to the PCI configuration register.\r | |
365 | \r | |
366 | **/\r | |
367 | UINT8\r | |
368 | EFIAPI\r | |
369 | PciBitFieldAndThenOr8 (\r | |
370 | IN UINTN Address,\r | |
371 | IN UINTN StartBit,\r | |
372 | IN UINTN EndBit,\r | |
373 | IN UINT8 AndData,\r | |
374 | IN UINT8 OrData\r | |
375 | )\r | |
376 | {\r | |
377 | return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);\r | |
378 | }\r | |
379 | \r | |
380 | /**\r | |
381 | Reads a 16-bit PCI configuration register.\r | |
382 | \r | |
383 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
384 | This function must guarantee that all PCI read and write operations are\r | |
385 | serialized.\r | |
386 | \r | |
387 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 388 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 389 | \r |
390 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
391 | Register.\r | |
392 | \r | |
393 | @return The read value from the PCI configuration register.\r | |
394 | \r | |
395 | **/\r | |
396 | UINT16\r | |
397 | EFIAPI\r | |
398 | PciRead16 (\r | |
399 | IN UINTN Address\r | |
400 | )\r | |
401 | {\r | |
402 | return PciExpressRead16 (Address);\r | |
403 | }\r | |
404 | \r | |
405 | /**\r | |
406 | Writes a 16-bit PCI configuration register.\r | |
407 | \r | |
408 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
409 | value specified by Value. Value is returned. This function must guarantee\r | |
410 | that all PCI read and write operations are serialized.\r | |
411 | \r | |
412 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 413 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 414 | \r |
415 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
416 | Register.\r | |
9638ba6d | 417 | @param Value The value to write.\r |
e1f414b6 | 418 | \r |
419 | @return The value written to the PCI configuration register.\r | |
420 | \r | |
421 | **/\r | |
422 | UINT16\r | |
423 | EFIAPI\r | |
424 | PciWrite16 (\r | |
425 | IN UINTN Address,\r | |
94646ec0 | 426 | IN UINT16 Value\r |
e1f414b6 | 427 | )\r |
428 | {\r | |
94646ec0 | 429 | return PciExpressWrite16 (Address, Value);\r |
e1f414b6 | 430 | }\r |
431 | \r | |
432 | /**\r | |
62991af2 | 433 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
e1f414b6 | 434 | a 16-bit value.\r |
435 | \r | |
436 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 437 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 438 | OrData, and writes the result to the 16-bit PCI configuration register\r |
439 | specified by Address. The value written to the PCI configuration register is\r | |
440 | returned. This function must guarantee that all PCI read and write operations\r | |
441 | are serialized.\r | |
442 | \r | |
443 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 444 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 445 | \r |
446 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
447 | Register.\r | |
448 | @param OrData The value to OR with the PCI configuration register.\r | |
449 | \r | |
450 | @return The value written back to the PCI configuration register.\r | |
451 | \r | |
452 | **/\r | |
453 | UINT16\r | |
454 | EFIAPI\r | |
455 | PciOr16 (\r | |
456 | IN UINTN Address,\r | |
457 | IN UINT16 OrData\r | |
458 | )\r | |
459 | {\r | |
460 | return PciExpressOr16 (Address, OrData);\r | |
461 | }\r | |
462 | \r | |
463 | /**\r | |
464 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
465 | value.\r | |
466 | \r | |
467 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
468 | bitwise AND between the read result and the value specified by AndData, and\r | |
469 | writes the result to the 16-bit PCI configuration register specified by\r | |
470 | Address. The value written to the PCI configuration register is returned.\r | |
471 | This function must guarantee that all PCI read and write operations are\r | |
472 | serialized.\r | |
473 | \r | |
474 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 475 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 476 | \r |
477 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
478 | Register.\r | |
479 | @param AndData The value to AND with the PCI configuration register.\r | |
480 | \r | |
481 | @return The value written back to the PCI configuration register.\r | |
482 | \r | |
483 | **/\r | |
484 | UINT16\r | |
485 | EFIAPI\r | |
486 | PciAnd16 (\r | |
487 | IN UINTN Address,\r | |
488 | IN UINT16 AndData\r | |
489 | )\r | |
490 | {\r | |
491 | return PciExpressAnd16 (Address, AndData);\r | |
492 | }\r | |
493 | \r | |
494 | /**\r | |
495 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
62991af2 | 496 | value, followed a bitwise OR with another 16-bit value.\r |
e1f414b6 | 497 | \r |
498 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
499 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 500 | performs a bitwise OR between the result of the AND operation and\r |
e1f414b6 | 501 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
502 | configuration register specified by Address. The value written to the PCI\r | |
503 | configuration register is returned. This function must guarantee that all PCI\r | |
504 | read and write operations are serialized.\r | |
505 | \r | |
506 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 507 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 508 | \r |
509 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
510 | Register.\r | |
511 | @param AndData The value to AND with the PCI configuration register.\r | |
512 | @param OrData The value to OR with the result of the AND operation.\r | |
513 | \r | |
514 | @return The value written back to the PCI configuration register.\r | |
515 | \r | |
516 | **/\r | |
517 | UINT16\r | |
518 | EFIAPI\r | |
519 | PciAndThenOr16 (\r | |
520 | IN UINTN Address,\r | |
521 | IN UINT16 AndData,\r | |
522 | IN UINT16 OrData\r | |
523 | )\r | |
524 | {\r | |
525 | return PciExpressAndThenOr16 (Address, AndData, OrData);\r | |
526 | }\r | |
527 | \r | |
528 | /**\r | |
529 | Reads a bit field of a PCI configuration register.\r | |
530 | \r | |
531 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
532 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
533 | returned.\r | |
534 | \r | |
535 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 536 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 537 | If StartBit is greater than 15, then ASSERT().\r |
538 | If EndBit is greater than 15, then ASSERT().\r | |
539 | If EndBit is less than StartBit, then ASSERT().\r | |
540 | \r | |
541 | @param Address PCI configuration register to read.\r | |
542 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
543 | Range 0..15.\r | |
544 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
545 | Range 0..15.\r | |
546 | \r | |
547 | @return The value of the bit field read from the PCI configuration register.\r | |
548 | \r | |
549 | **/\r | |
550 | UINT16\r | |
551 | EFIAPI\r | |
552 | PciBitFieldRead16 (\r | |
553 | IN UINTN Address,\r | |
554 | IN UINTN StartBit,\r | |
555 | IN UINTN EndBit\r | |
556 | )\r | |
557 | {\r | |
558 | return PciExpressBitFieldRead16 (Address, StartBit, EndBit);\r | |
559 | }\r | |
560 | \r | |
561 | /**\r | |
562 | Writes a bit field to a PCI configuration register.\r | |
563 | \r | |
564 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
565 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
566 | destination PCI configuration register are preserved. The new value of the\r | |
567 | 16-bit register is returned.\r | |
568 | \r | |
569 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 570 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 571 | If StartBit is greater than 15, then ASSERT().\r |
572 | If EndBit is greater than 15, then ASSERT().\r | |
573 | If EndBit is less than StartBit, then ASSERT().\r | |
574 | \r | |
575 | @param Address PCI configuration register to write.\r | |
576 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
577 | Range 0..15.\r | |
578 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
579 | Range 0..15.\r | |
580 | @param Value New value of the bit field.\r | |
581 | \r | |
582 | @return The value written back to the PCI configuration register.\r | |
583 | \r | |
584 | **/\r | |
585 | UINT16\r | |
586 | EFIAPI\r | |
587 | PciBitFieldWrite16 (\r | |
588 | IN UINTN Address,\r | |
589 | IN UINTN StartBit,\r | |
590 | IN UINTN EndBit,\r | |
591 | IN UINT16 Value\r | |
592 | )\r | |
593 | {\r | |
594 | return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value);\r | |
595 | }\r | |
596 | \r | |
597 | /**\r | |
598 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
599 | writes the result back to the bit field in the 16-bit port.\r | |
600 | \r | |
601 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 602 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 603 | OrData, and writes the result to the 16-bit PCI configuration register\r |
604 | specified by Address. The value written to the PCI configuration register is\r | |
605 | returned. This function must guarantee that all PCI read and write operations\r | |
606 | are serialized. Extra left bits in OrData are stripped.\r | |
607 | \r | |
608 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 609 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 610 | If StartBit is greater than 15, then ASSERT().\r |
611 | If EndBit is greater than 15, then ASSERT().\r | |
612 | If EndBit is less than StartBit, then ASSERT().\r | |
613 | \r | |
614 | @param Address PCI configuration register to write.\r | |
615 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
616 | Range 0..15.\r | |
617 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
618 | Range 0..15.\r | |
619 | @param OrData The value to OR with the PCI configuration register.\r | |
620 | \r | |
621 | @return The value written back to the PCI configuration register.\r | |
622 | \r | |
623 | **/\r | |
624 | UINT16\r | |
625 | EFIAPI\r | |
626 | PciBitFieldOr16 (\r | |
627 | IN UINTN Address,\r | |
628 | IN UINTN StartBit,\r | |
629 | IN UINTN EndBit,\r | |
630 | IN UINT16 OrData\r | |
631 | )\r | |
632 | {\r | |
633 | return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData);\r | |
634 | }\r | |
635 | \r | |
636 | /**\r | |
637 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
638 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
639 | \r | |
640 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
641 | bitwise AND between the read result and the value specified by AndData, and\r | |
642 | writes the result to the 16-bit PCI configuration register specified by\r | |
643 | Address. The value written to the PCI configuration register is returned.\r | |
644 | This function must guarantee that all PCI read and write operations are\r | |
645 | serialized. Extra left bits in AndData are stripped.\r | |
646 | \r | |
647 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 648 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 649 | If StartBit is greater than 15, then ASSERT().\r |
650 | If EndBit is greater than 15, then ASSERT().\r | |
651 | If EndBit is less than StartBit, then ASSERT().\r | |
652 | \r | |
653 | @param Address PCI configuration register to write.\r | |
654 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
655 | Range 0..15.\r | |
656 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
657 | Range 0..15.\r | |
658 | @param AndData The value to AND with the PCI configuration register.\r | |
659 | \r | |
660 | @return The value written back to the PCI configuration register.\r | |
661 | \r | |
662 | **/\r | |
663 | UINT16\r | |
664 | EFIAPI\r | |
665 | PciBitFieldAnd16 (\r | |
666 | IN UINTN Address,\r | |
667 | IN UINTN StartBit,\r | |
668 | IN UINTN EndBit,\r | |
669 | IN UINT16 AndData\r | |
670 | )\r | |
671 | {\r | |
672 | return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData);\r | |
673 | }\r | |
674 | \r | |
675 | /**\r | |
676 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 677 | bitwise OR, and writes the result back to the bit field in the\r |
e1f414b6 | 678 | 16-bit port.\r |
679 | \r | |
680 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 681 | bitwise AND followed by a bitwise OR between the read result and\r |
e1f414b6 | 682 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
683 | configuration register specified by Address. The value written to the PCI\r | |
684 | configuration register is returned. This function must guarantee that all PCI\r | |
685 | read and write operations are serialized. Extra left bits in both AndData and\r | |
686 | OrData are stripped.\r | |
687 | \r | |
688 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 689 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 690 | If StartBit is greater than 15, then ASSERT().\r |
691 | If EndBit is greater than 15, then ASSERT().\r | |
692 | If EndBit is less than StartBit, then ASSERT().\r | |
693 | \r | |
694 | @param Address PCI configuration register to write.\r | |
695 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
696 | Range 0..15.\r | |
697 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
698 | Range 0..15.\r | |
699 | @param AndData The value to AND with the PCI configuration register.\r | |
700 | @param OrData The value to OR with the result of the AND operation.\r | |
701 | \r | |
702 | @return The value written back to the PCI configuration register.\r | |
703 | \r | |
704 | **/\r | |
705 | UINT16\r | |
706 | EFIAPI\r | |
707 | PciBitFieldAndThenOr16 (\r | |
708 | IN UINTN Address,\r | |
709 | IN UINTN StartBit,\r | |
710 | IN UINTN EndBit,\r | |
711 | IN UINT16 AndData,\r | |
712 | IN UINT16 OrData\r | |
713 | )\r | |
714 | {\r | |
715 | return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);\r | |
716 | }\r | |
717 | \r | |
718 | /**\r | |
719 | Reads a 32-bit PCI configuration register.\r | |
720 | \r | |
721 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
722 | This function must guarantee that all PCI read and write operations are\r | |
723 | serialized.\r | |
724 | \r | |
725 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 726 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 727 | \r |
728 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
729 | Register.\r | |
730 | \r | |
731 | @return The read value from the PCI configuration register.\r | |
732 | \r | |
733 | **/\r | |
734 | UINT32\r | |
735 | EFIAPI\r | |
736 | PciRead32 (\r | |
737 | IN UINTN Address\r | |
738 | )\r | |
739 | {\r | |
740 | return PciExpressRead32 (Address);\r | |
741 | }\r | |
742 | \r | |
743 | /**\r | |
744 | Writes a 32-bit PCI configuration register.\r | |
745 | \r | |
746 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
747 | value specified by Value. Value is returned. This function must guarantee\r | |
748 | that all PCI read and write operations are serialized.\r | |
749 | \r | |
750 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 751 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 752 | \r |
753 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
754 | Register.\r | |
7612cbf0 | 755 | @param Value The value to write.\r |
e1f414b6 | 756 | \r |
757 | @return The value written to the PCI configuration register.\r | |
758 | \r | |
759 | **/\r | |
760 | UINT32\r | |
761 | EFIAPI\r | |
762 | PciWrite32 (\r | |
763 | IN UINTN Address,\r | |
94646ec0 | 764 | IN UINT32 Value\r |
e1f414b6 | 765 | )\r |
766 | {\r | |
94646ec0 | 767 | return PciExpressWrite32 (Address, Value);\r |
e1f414b6 | 768 | }\r |
769 | \r | |
770 | /**\r | |
62991af2 | 771 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
e1f414b6 | 772 | a 32-bit value.\r |
773 | \r | |
774 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 775 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 776 | OrData, and writes the result to the 32-bit PCI configuration register\r |
777 | specified by Address. The value written to the PCI configuration register is\r | |
778 | returned. This function must guarantee that all PCI read and write operations\r | |
779 | are serialized.\r | |
780 | \r | |
781 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 782 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 783 | \r |
784 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
785 | Register.\r | |
786 | @param OrData The value to OR with the PCI configuration register.\r | |
787 | \r | |
788 | @return The value written back to the PCI configuration register.\r | |
789 | \r | |
790 | **/\r | |
791 | UINT32\r | |
792 | EFIAPI\r | |
793 | PciOr32 (\r | |
794 | IN UINTN Address,\r | |
795 | IN UINT32 OrData\r | |
796 | )\r | |
797 | {\r | |
798 | return PciExpressOr32 (Address, OrData);\r | |
799 | }\r | |
800 | \r | |
801 | /**\r | |
802 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
803 | value.\r | |
804 | \r | |
805 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
806 | bitwise AND between the read result and the value specified by AndData, and\r | |
807 | writes the result to the 32-bit PCI configuration register specified by\r | |
808 | Address. The value written to the PCI configuration register is returned.\r | |
809 | This function must guarantee that all PCI read and write operations are\r | |
810 | serialized.\r | |
811 | \r | |
812 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 813 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 814 | \r |
815 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
816 | Register.\r | |
817 | @param AndData The value to AND with the PCI configuration register.\r | |
818 | \r | |
819 | @return The value written back to the PCI configuration register.\r | |
820 | \r | |
821 | **/\r | |
822 | UINT32\r | |
823 | EFIAPI\r | |
824 | PciAnd32 (\r | |
825 | IN UINTN Address,\r | |
826 | IN UINT32 AndData\r | |
827 | )\r | |
828 | {\r | |
829 | return PciExpressAnd32 (Address, AndData);\r | |
830 | }\r | |
831 | \r | |
832 | /**\r | |
833 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
62991af2 | 834 | value, followed a bitwise OR with another 32-bit value.\r |
e1f414b6 | 835 | \r |
836 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
837 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 838 | performs a bitwise OR between the result of the AND operation and\r |
e1f414b6 | 839 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
840 | configuration register specified by Address. The value written to the PCI\r | |
841 | configuration register is returned. This function must guarantee that all PCI\r | |
842 | read and write operations are serialized.\r | |
843 | \r | |
844 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 845 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 846 | \r |
847 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
848 | Register.\r | |
849 | @param AndData The value to AND with the PCI configuration register.\r | |
850 | @param OrData The value to OR with the result of the AND operation.\r | |
851 | \r | |
852 | @return The value written back to the PCI configuration register.\r | |
853 | \r | |
854 | **/\r | |
855 | UINT32\r | |
856 | EFIAPI\r | |
857 | PciAndThenOr32 (\r | |
858 | IN UINTN Address,\r | |
859 | IN UINT32 AndData,\r | |
860 | IN UINT32 OrData\r | |
861 | )\r | |
862 | {\r | |
863 | return PciExpressAndThenOr32 (Address, AndData, OrData);\r | |
864 | }\r | |
865 | \r | |
866 | /**\r | |
867 | Reads a bit field of a PCI configuration register.\r | |
868 | \r | |
869 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
870 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
871 | returned.\r | |
872 | \r | |
873 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 874 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 875 | If StartBit is greater than 31, then ASSERT().\r |
876 | If EndBit is greater than 31, then ASSERT().\r | |
877 | If EndBit is less than StartBit, then ASSERT().\r | |
878 | \r | |
879 | @param Address PCI configuration register to read.\r | |
880 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
881 | Range 0..31.\r | |
882 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
883 | Range 0..31.\r | |
884 | \r | |
885 | @return The value of the bit field read from the PCI configuration register.\r | |
886 | \r | |
887 | **/\r | |
888 | UINT32\r | |
889 | EFIAPI\r | |
890 | PciBitFieldRead32 (\r | |
891 | IN UINTN Address,\r | |
892 | IN UINTN StartBit,\r | |
893 | IN UINTN EndBit\r | |
894 | )\r | |
895 | {\r | |
896 | return PciExpressBitFieldRead32 (Address, StartBit, EndBit);\r | |
897 | }\r | |
898 | \r | |
899 | /**\r | |
900 | Writes a bit field to a PCI configuration register.\r | |
901 | \r | |
902 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
903 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
904 | destination PCI configuration register are preserved. The new value of the\r | |
905 | 32-bit register is returned.\r | |
906 | \r | |
907 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 908 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 909 | If StartBit is greater than 31, then ASSERT().\r |
910 | If EndBit is greater than 31, then ASSERT().\r | |
911 | If EndBit is less than StartBit, then ASSERT().\r | |
912 | \r | |
913 | @param Address PCI configuration register to write.\r | |
914 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
915 | Range 0..31.\r | |
916 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
917 | Range 0..31.\r | |
918 | @param Value New value of the bit field.\r | |
919 | \r | |
920 | @return The value written back to the PCI configuration register.\r | |
921 | \r | |
922 | **/\r | |
923 | UINT32\r | |
924 | EFIAPI\r | |
925 | PciBitFieldWrite32 (\r | |
926 | IN UINTN Address,\r | |
927 | IN UINTN StartBit,\r | |
928 | IN UINTN EndBit,\r | |
929 | IN UINT32 Value\r | |
930 | )\r | |
931 | {\r | |
932 | return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value);\r | |
933 | }\r | |
934 | \r | |
935 | /**\r | |
936 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
937 | writes the result back to the bit field in the 32-bit port.\r | |
938 | \r | |
939 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 940 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 941 | OrData, and writes the result to the 32-bit PCI configuration register\r |
942 | specified by Address. The value written to the PCI configuration register is\r | |
943 | returned. This function must guarantee that all PCI read and write operations\r | |
944 | are serialized. Extra left bits in OrData are stripped.\r | |
945 | \r | |
946 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 947 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 948 | If StartBit is greater than 31, then ASSERT().\r |
949 | If EndBit is greater than 31, then ASSERT().\r | |
950 | If EndBit is less than StartBit, then ASSERT().\r | |
951 | \r | |
952 | @param Address PCI configuration register to write.\r | |
953 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
954 | Range 0..31.\r | |
955 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
956 | Range 0..31.\r | |
957 | @param OrData The value to OR with the PCI configuration register.\r | |
958 | \r | |
959 | @return The value written back to the PCI configuration register.\r | |
960 | \r | |
961 | **/\r | |
962 | UINT32\r | |
963 | EFIAPI\r | |
964 | PciBitFieldOr32 (\r | |
965 | IN UINTN Address,\r | |
966 | IN UINTN StartBit,\r | |
967 | IN UINTN EndBit,\r | |
968 | IN UINT32 OrData\r | |
969 | )\r | |
970 | {\r | |
971 | return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData);\r | |
972 | }\r | |
973 | \r | |
974 | /**\r | |
975 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
976 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
977 | \r | |
978 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
979 | bitwise AND between the read result and the value specified by AndData, and\r | |
980 | writes the result to the 32-bit PCI configuration register specified by\r | |
981 | Address. The value written to the PCI configuration register is returned.\r | |
982 | This function must guarantee that all PCI read and write operations are\r | |
983 | serialized. Extra left bits in AndData are stripped.\r | |
984 | \r | |
985 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 986 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 987 | If StartBit is greater than 31, then ASSERT().\r |
988 | If EndBit is greater than 31, then ASSERT().\r | |
989 | If EndBit is less than StartBit, then ASSERT().\r | |
990 | \r | |
991 | @param Address PCI configuration register to write.\r | |
992 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
993 | Range 0..31.\r | |
994 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
995 | Range 0..31.\r | |
996 | @param AndData The value to AND with the PCI configuration register.\r | |
997 | \r | |
998 | @return The value written back to the PCI configuration register.\r | |
999 | \r | |
1000 | **/\r | |
1001 | UINT32\r | |
1002 | EFIAPI\r | |
1003 | PciBitFieldAnd32 (\r | |
1004 | IN UINTN Address,\r | |
1005 | IN UINTN StartBit,\r | |
1006 | IN UINTN EndBit,\r | |
1007 | IN UINT32 AndData\r | |
1008 | )\r | |
1009 | {\r | |
1010 | return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData);\r | |
1011 | }\r | |
1012 | \r | |
1013 | /**\r | |
1014 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 1015 | bitwise OR, and writes the result back to the bit field in the\r |
e1f414b6 | 1016 | 32-bit port.\r |
1017 | \r | |
1018 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1019 | bitwise AND followed by a bitwise OR between the read result and\r |
e1f414b6 | 1020 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
1021 | configuration register specified by Address. The value written to the PCI\r | |
1022 | configuration register is returned. This function must guarantee that all PCI\r | |
1023 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1024 | OrData are stripped.\r | |
1025 | \r | |
1026 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 1027 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 1028 | If StartBit is greater than 31, then ASSERT().\r |
1029 | If EndBit is greater than 31, then ASSERT().\r | |
1030 | If EndBit is less than StartBit, then ASSERT().\r | |
1031 | \r | |
1032 | @param Address PCI configuration register to write.\r | |
1033 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1034 | Range 0..31.\r | |
1035 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1036 | Range 0..31.\r | |
1037 | @param AndData The value to AND with the PCI configuration register.\r | |
1038 | @param OrData The value to OR with the result of the AND operation.\r | |
1039 | \r | |
1040 | @return The value written back to the PCI configuration register.\r | |
1041 | \r | |
1042 | **/\r | |
1043 | UINT32\r | |
1044 | EFIAPI\r | |
1045 | PciBitFieldAndThenOr32 (\r | |
1046 | IN UINTN Address,\r | |
1047 | IN UINTN StartBit,\r | |
1048 | IN UINTN EndBit,\r | |
1049 | IN UINT32 AndData,\r | |
1050 | IN UINT32 OrData\r | |
1051 | )\r | |
1052 | {\r | |
1053 | return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);\r | |
1054 | }\r | |
1055 | \r | |
1056 | /**\r | |
1057 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1058 | \r | |
1059 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1060 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1061 | configuration registers from a single PCI function to be read. Size is\r | |
1062 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1063 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1064 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1065 | end of the range.\r | |
1066 | \r | |
1067 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1068 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1069 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1070 | \r | |
1071 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1072 | Function and Register.\r | |
1073 | @param Size Size in bytes of the transfer.\r | |
1074 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1075 | \r | |
1076 | @return Size\r | |
1077 | \r | |
1078 | **/\r | |
1079 | UINTN\r | |
1080 | EFIAPI\r | |
1081 | PciReadBuffer (\r | |
1082 | IN UINTN StartAddress,\r | |
1083 | IN UINTN Size,\r | |
1084 | OUT VOID *Buffer\r | |
1085 | )\r | |
1086 | {\r | |
1087 | return PciExpressReadBuffer (StartAddress, Size, Buffer);\r | |
1088 | }\r | |
1089 | \r | |
1090 | /**\r | |
1091 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1092 | configuration space.\r | |
1093 | \r | |
1094 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1095 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1096 | configuration registers from a single PCI function to be written. Size is\r | |
1097 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1098 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1099 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1100 | and the end of the range.\r | |
1101 | \r | |
1102 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1103 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1104 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1105 | \r | |
1106 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1107 | Function and Register.\r | |
1108 | @param Size Size in bytes of the transfer.\r | |
1109 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1110 | \r | |
efb23117 | 1111 | @return Size written to StartAddress.\r |
e1f414b6 | 1112 | \r |
1113 | **/\r | |
1114 | UINTN\r | |
1115 | EFIAPI\r | |
1116 | PciWriteBuffer (\r | |
1117 | IN UINTN StartAddress,\r | |
1118 | IN UINTN Size,\r | |
1119 | IN VOID *Buffer\r | |
1120 | )\r | |
1121 | {\r | |
1122 | return PciExpressWriteBuffer (StartAddress, Size, Buffer);\r | |
1123 | }\r |