| e1f414b6 |
1 | /** @file\r |
| 2 | PCI Library using PC Express access.\r |
| 3 | \r |
| 4 | Copyright (c) 2006, Intel Corporation<BR>\r |
| 5 | All rights reserved. This program and the accompanying materials\r |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r |
| 7 | which accompanies this distribution. The full text of the license may be found at\r |
| 8 | http://opensource.org/licenses/bsd-license.php\r |
| 9 | \r |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 12 | \r |
| e1f414b6 |
13 | **/\r |
| 14 | \r |
| 15 | //\r |
| c7d265a9 |
16 | // The package level header files this module uses\r |
| e1f414b6 |
17 | //\r |
| c7d265a9 |
18 | #include <Base.h>\r |
| 19 | //\r |
| 20 | // The protocols, PPI and GUID defintions for this module\r |
| 21 | //\r |
| 22 | //\r |
| 23 | // The Library classes this module consumes\r |
| 24 | //\r |
| 25 | #include <Library/PciLib.h>\r |
| 26 | #include <Library/PciExpressLib.h>\r |
| e1f414b6 |
27 | \r |
| 28 | /**\r |
| 29 | Reads an 8-bit PCI configuration register.\r |
| 30 | \r |
| 31 | Reads and returns the 8-bit PCI configuration register specified by Address.\r |
| 32 | This function must guarantee that all PCI read and write operations are\r |
| 33 | serialized.\r |
| 34 | \r |
| 35 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 36 | \r |
| 37 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 38 | Register.\r |
| 39 | \r |
| 40 | @return The read value from the PCI configuration register.\r |
| 41 | \r |
| 42 | **/\r |
| 43 | UINT8\r |
| 44 | EFIAPI\r |
| 45 | PciRead8 (\r |
| 46 | IN UINTN Address\r |
| 47 | )\r |
| 48 | {\r |
| 49 | return PciExpressRead8 (Address);\r |
| 50 | }\r |
| 51 | \r |
| 52 | /**\r |
| 53 | Writes an 8-bit PCI configuration register.\r |
| 54 | \r |
| 55 | Writes the 8-bit PCI configuration register specified by Address with the\r |
| 56 | value specified by Value. Value is returned. This function must guarantee\r |
| 57 | that all PCI read and write operations are serialized.\r |
| 58 | \r |
| 59 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 60 | \r |
| 61 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 62 | Register.\r |
| 63 | @param Value The value to write.\r |
| 64 | \r |
| 65 | @return The value written to the PCI configuration register.\r |
| 66 | \r |
| 67 | **/\r |
| 68 | UINT8\r |
| 69 | EFIAPI\r |
| 70 | PciWrite8 (\r |
| 71 | IN UINTN Address,\r |
| 72 | IN UINT8 Data\r |
| 73 | )\r |
| 74 | {\r |
| 75 | return PciExpressWrite8 (Address, Data);\r |
| 76 | }\r |
| 77 | \r |
| 78 | /**\r |
| 79 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r |
| 80 | an 8-bit value.\r |
| 81 | \r |
| 82 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 83 | bitwise inclusive OR between the read result and the value specified by\r |
| 84 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 85 | specified by Address. The value written to the PCI configuration register is\r |
| 86 | returned. This function must guarantee that all PCI read and write operations\r |
| 87 | are serialized.\r |
| 88 | \r |
| 89 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 90 | \r |
| 91 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 92 | Register.\r |
| 93 | @param OrData The value to OR with the PCI configuration register.\r |
| 94 | \r |
| 95 | @return The value written back to the PCI configuration register.\r |
| 96 | \r |
| 97 | **/\r |
| 98 | UINT8\r |
| 99 | EFIAPI\r |
| 100 | PciOr8 (\r |
| 101 | IN UINTN Address,\r |
| 102 | IN UINT8 OrData\r |
| 103 | )\r |
| 104 | {\r |
| 105 | return PciExpressOr8 (Address, OrData);\r |
| 106 | }\r |
| 107 | \r |
| 108 | /**\r |
| 109 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 110 | value.\r |
| 111 | \r |
| 112 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 113 | bitwise AND between the read result and the value specified by AndData, and\r |
| 114 | writes the result to the 8-bit PCI configuration register specified by\r |
| 115 | Address. The value written to the PCI configuration register is returned.\r |
| 116 | This function must guarantee that all PCI read and write operations are\r |
| 117 | serialized.\r |
| 118 | \r |
| 119 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 120 | \r |
| 121 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 122 | Register.\r |
| 123 | @param AndData The value to AND with the PCI configuration register.\r |
| 124 | \r |
| 125 | @return The value written back to the PCI configuration register.\r |
| 126 | \r |
| 127 | **/\r |
| 128 | UINT8\r |
| 129 | EFIAPI\r |
| 130 | PciAnd8 (\r |
| 131 | IN UINTN Address,\r |
| 132 | IN UINT8 AndData\r |
| 133 | )\r |
| 134 | {\r |
| 135 | return PciExpressAnd8 (Address, AndData);\r |
| 136 | }\r |
| 137 | \r |
| 138 | /**\r |
| 139 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 140 | value, followed a bitwise inclusive OR with another 8-bit value.\r |
| 141 | \r |
| 142 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 143 | bitwise AND between the read result and the value specified by AndData,\r |
| 144 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 145 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
| 146 | configuration register specified by Address. The value written to the PCI\r |
| 147 | configuration register is returned. This function must guarantee that all PCI\r |
| 148 | read and write operations are serialized.\r |
| 149 | \r |
| 150 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 151 | \r |
| 152 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 153 | Register.\r |
| 154 | @param AndData The value to AND with the PCI configuration register.\r |
| 155 | @param OrData The value to OR with the result of the AND operation.\r |
| 156 | \r |
| 157 | @return The value written back to the PCI configuration register.\r |
| 158 | \r |
| 159 | **/\r |
| 160 | UINT8\r |
| 161 | EFIAPI\r |
| 162 | PciAndThenOr8 (\r |
| 163 | IN UINTN Address,\r |
| 164 | IN UINT8 AndData,\r |
| 165 | IN UINT8 OrData\r |
| 166 | )\r |
| 167 | {\r |
| 168 | return PciExpressAndThenOr8 (Address, AndData, OrData);\r |
| 169 | }\r |
| 170 | \r |
| 171 | /**\r |
| 172 | Reads a bit field of a PCI configuration register.\r |
| 173 | \r |
| 174 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r |
| 175 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 176 | returned.\r |
| 177 | \r |
| 178 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 179 | If StartBit is greater than 7, then ASSERT().\r |
| 180 | If EndBit is greater than 7, then ASSERT().\r |
| 181 | If EndBit is less than StartBit, then ASSERT().\r |
| 182 | \r |
| 183 | @param Address PCI configuration register to read.\r |
| 184 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 185 | Range 0..7.\r |
| 186 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 187 | Range 0..7.\r |
| 188 | \r |
| 189 | @return The value of the bit field read from the PCI configuration register.\r |
| 190 | \r |
| 191 | **/\r |
| 192 | UINT8\r |
| 193 | EFIAPI\r |
| 194 | PciBitFieldRead8 (\r |
| 195 | IN UINTN Address,\r |
| 196 | IN UINTN StartBit,\r |
| 197 | IN UINTN EndBit\r |
| 198 | )\r |
| 199 | {\r |
| 200 | return PciExpressBitFieldRead8 (Address, StartBit, EndBit);\r |
| 201 | }\r |
| 202 | \r |
| 203 | /**\r |
| 204 | Writes a bit field to a PCI configuration register.\r |
| 205 | \r |
| 206 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 207 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 208 | destination PCI configuration register are preserved. The new value of the\r |
| 209 | 8-bit register is returned.\r |
| 210 | \r |
| 211 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 212 | If StartBit is greater than 7, then ASSERT().\r |
| 213 | If EndBit is greater than 7, then ASSERT().\r |
| 214 | If EndBit is less than StartBit, then ASSERT().\r |
| 215 | \r |
| 216 | @param Address PCI configuration register to write.\r |
| 217 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 218 | Range 0..7.\r |
| 219 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 220 | Range 0..7.\r |
| 221 | @param Value New value of the bit field.\r |
| 222 | \r |
| 223 | @return The value written back to the PCI configuration register.\r |
| 224 | \r |
| 225 | **/\r |
| 226 | UINT8\r |
| 227 | EFIAPI\r |
| 228 | PciBitFieldWrite8 (\r |
| 229 | IN UINTN Address,\r |
| 230 | IN UINTN StartBit,\r |
| 231 | IN UINTN EndBit,\r |
| 232 | IN UINT8 Value\r |
| 233 | )\r |
| 234 | {\r |
| 235 | return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value);\r |
| 236 | }\r |
| 237 | \r |
| 238 | /**\r |
| 239 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r |
| 240 | writes the result back to the bit field in the 8-bit port.\r |
| 241 | \r |
| 242 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 243 | bitwise inclusive OR between the read result and the value specified by\r |
| 244 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 245 | specified by Address. The value written to the PCI configuration register is\r |
| 246 | returned. This function must guarantee that all PCI read and write operations\r |
| 247 | are serialized. Extra left bits in OrData are stripped.\r |
| 248 | \r |
| 249 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 250 | If StartBit is greater than 7, then ASSERT().\r |
| 251 | If EndBit is greater than 7, then ASSERT().\r |
| 252 | If EndBit is less than StartBit, then ASSERT().\r |
| 253 | \r |
| 254 | @param Address PCI configuration register to write.\r |
| 255 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 256 | Range 0..7.\r |
| 257 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 258 | Range 0..7.\r |
| 259 | @param OrData The value to OR with the PCI configuration register.\r |
| 260 | \r |
| 261 | @return The value written back to the PCI configuration register.\r |
| 262 | \r |
| 263 | **/\r |
| 264 | UINT8\r |
| 265 | EFIAPI\r |
| 266 | PciBitFieldOr8 (\r |
| 267 | IN UINTN Address,\r |
| 268 | IN UINTN StartBit,\r |
| 269 | IN UINTN EndBit,\r |
| 270 | IN UINT8 OrData\r |
| 271 | )\r |
| 272 | {\r |
| 273 | return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData);\r |
| 274 | }\r |
| 275 | \r |
| 276 | /**\r |
| 277 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r |
| 278 | AND, and writes the result back to the bit field in the 8-bit register.\r |
| 279 | \r |
| 280 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 281 | bitwise AND between the read result and the value specified by AndData, and\r |
| 282 | writes the result to the 8-bit PCI configuration register specified by\r |
| 283 | Address. The value written to the PCI configuration register is returned.\r |
| 284 | This function must guarantee that all PCI read and write operations are\r |
| 285 | serialized. Extra left bits in AndData are stripped.\r |
| 286 | \r |
| 287 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 288 | If StartBit is greater than 7, then ASSERT().\r |
| 289 | If EndBit is greater than 7, then ASSERT().\r |
| 290 | If EndBit is less than StartBit, then ASSERT().\r |
| 291 | \r |
| 292 | @param Address PCI configuration register to write.\r |
| 293 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 294 | Range 0..7.\r |
| 295 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 296 | Range 0..7.\r |
| 297 | @param AndData The value to AND with the PCI configuration register.\r |
| 298 | \r |
| 299 | @return The value written back to the PCI configuration register.\r |
| 300 | \r |
| 301 | **/\r |
| 302 | UINT8\r |
| 303 | EFIAPI\r |
| 304 | PciBitFieldAnd8 (\r |
| 305 | IN UINTN Address,\r |
| 306 | IN UINTN StartBit,\r |
| 307 | IN UINTN EndBit,\r |
| 308 | IN UINT8 AndData\r |
| 309 | )\r |
| 310 | {\r |
| 311 | return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData);\r |
| 312 | }\r |
| 313 | \r |
| 314 | /**\r |
| 315 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r |
| 316 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 317 | 8-bit port.\r |
| 318 | \r |
| 319 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 320 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 321 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
| 322 | configuration register specified by Address. The value written to the PCI\r |
| 323 | configuration register is returned. This function must guarantee that all PCI\r |
| 324 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 325 | OrData are stripped.\r |
| 326 | \r |
| 327 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 328 | If StartBit is greater than 7, then ASSERT().\r |
| 329 | If EndBit is greater than 7, then ASSERT().\r |
| 330 | If EndBit is less than StartBit, then ASSERT().\r |
| 331 | \r |
| 332 | @param Address PCI configuration register to write.\r |
| 333 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 334 | Range 0..7.\r |
| 335 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 336 | Range 0..7.\r |
| 337 | @param AndData The value to AND with the PCI configuration register.\r |
| 338 | @param OrData The value to OR with the result of the AND operation.\r |
| 339 | \r |
| 340 | @return The value written back to the PCI configuration register.\r |
| 341 | \r |
| 342 | **/\r |
| 343 | UINT8\r |
| 344 | EFIAPI\r |
| 345 | PciBitFieldAndThenOr8 (\r |
| 346 | IN UINTN Address,\r |
| 347 | IN UINTN StartBit,\r |
| 348 | IN UINTN EndBit,\r |
| 349 | IN UINT8 AndData,\r |
| 350 | IN UINT8 OrData\r |
| 351 | )\r |
| 352 | {\r |
| 353 | return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);\r |
| 354 | }\r |
| 355 | \r |
| 356 | /**\r |
| 357 | Reads a 16-bit PCI configuration register.\r |
| 358 | \r |
| 359 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
| 360 | This function must guarantee that all PCI read and write operations are\r |
| 361 | serialized.\r |
| 362 | \r |
| 363 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 364 | \r |
| 365 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 366 | Register.\r |
| 367 | \r |
| 368 | @return The read value from the PCI configuration register.\r |
| 369 | \r |
| 370 | **/\r |
| 371 | UINT16\r |
| 372 | EFIAPI\r |
| 373 | PciRead16 (\r |
| 374 | IN UINTN Address\r |
| 375 | )\r |
| 376 | {\r |
| 377 | return PciExpressRead16 (Address);\r |
| 378 | }\r |
| 379 | \r |
| 380 | /**\r |
| 381 | Writes a 16-bit PCI configuration register.\r |
| 382 | \r |
| 383 | Writes the 16-bit PCI configuration register specified by Address with the\r |
| 384 | value specified by Value. Value is returned. This function must guarantee\r |
| 385 | that all PCI read and write operations are serialized.\r |
| 386 | \r |
| 387 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 388 | \r |
| 389 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 390 | Register.\r |
| 391 | @param Value The value to write.\r |
| 392 | \r |
| 393 | @return The value written to the PCI configuration register.\r |
| 394 | \r |
| 395 | **/\r |
| 396 | UINT16\r |
| 397 | EFIAPI\r |
| 398 | PciWrite16 (\r |
| 399 | IN UINTN Address,\r |
| 400 | IN UINT16 Data\r |
| 401 | )\r |
| 402 | {\r |
| 403 | return PciExpressWrite16 (Address, Data);\r |
| 404 | }\r |
| 405 | \r |
| 406 | /**\r |
| 407 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r |
| 408 | a 16-bit value.\r |
| 409 | \r |
| 410 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 411 | bitwise inclusive OR between the read result and the value specified by\r |
| 412 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 413 | specified by Address. The value written to the PCI configuration register is\r |
| 414 | returned. This function must guarantee that all PCI read and write operations\r |
| 415 | are serialized.\r |
| 416 | \r |
| 417 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 418 | \r |
| 419 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 420 | Register.\r |
| 421 | @param OrData The value to OR with the PCI configuration register.\r |
| 422 | \r |
| 423 | @return The value written back to the PCI configuration register.\r |
| 424 | \r |
| 425 | **/\r |
| 426 | UINT16\r |
| 427 | EFIAPI\r |
| 428 | PciOr16 (\r |
| 429 | IN UINTN Address,\r |
| 430 | IN UINT16 OrData\r |
| 431 | )\r |
| 432 | {\r |
| 433 | return PciExpressOr16 (Address, OrData);\r |
| 434 | }\r |
| 435 | \r |
| 436 | /**\r |
| 437 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 438 | value.\r |
| 439 | \r |
| 440 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 441 | bitwise AND between the read result and the value specified by AndData, and\r |
| 442 | writes the result to the 16-bit PCI configuration register specified by\r |
| 443 | Address. The value written to the PCI configuration register is returned.\r |
| 444 | This function must guarantee that all PCI read and write operations are\r |
| 445 | serialized.\r |
| 446 | \r |
| 447 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 448 | \r |
| 449 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 450 | Register.\r |
| 451 | @param AndData The value to AND with the PCI configuration register.\r |
| 452 | \r |
| 453 | @return The value written back to the PCI configuration register.\r |
| 454 | \r |
| 455 | **/\r |
| 456 | UINT16\r |
| 457 | EFIAPI\r |
| 458 | PciAnd16 (\r |
| 459 | IN UINTN Address,\r |
| 460 | IN UINT16 AndData\r |
| 461 | )\r |
| 462 | {\r |
| 463 | return PciExpressAnd16 (Address, AndData);\r |
| 464 | }\r |
| 465 | \r |
| 466 | /**\r |
| 467 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 468 | value, followed a bitwise inclusive OR with another 16-bit value.\r |
| 469 | \r |
| 470 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 471 | bitwise AND between the read result and the value specified by AndData,\r |
| 472 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 473 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
| 474 | configuration register specified by Address. The value written to the PCI\r |
| 475 | configuration register is returned. This function must guarantee that all PCI\r |
| 476 | read and write operations are serialized.\r |
| 477 | \r |
| 478 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 479 | \r |
| 480 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 481 | Register.\r |
| 482 | @param AndData The value to AND with the PCI configuration register.\r |
| 483 | @param OrData The value to OR with the result of the AND operation.\r |
| 484 | \r |
| 485 | @return The value written back to the PCI configuration register.\r |
| 486 | \r |
| 487 | **/\r |
| 488 | UINT16\r |
| 489 | EFIAPI\r |
| 490 | PciAndThenOr16 (\r |
| 491 | IN UINTN Address,\r |
| 492 | IN UINT16 AndData,\r |
| 493 | IN UINT16 OrData\r |
| 494 | )\r |
| 495 | {\r |
| 496 | return PciExpressAndThenOr16 (Address, AndData, OrData);\r |
| 497 | }\r |
| 498 | \r |
| 499 | /**\r |
| 500 | Reads a bit field of a PCI configuration register.\r |
| 501 | \r |
| 502 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r |
| 503 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 504 | returned.\r |
| 505 | \r |
| 506 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 507 | If StartBit is greater than 15, then ASSERT().\r |
| 508 | If EndBit is greater than 15, then ASSERT().\r |
| 509 | If EndBit is less than StartBit, then ASSERT().\r |
| 510 | \r |
| 511 | @param Address PCI configuration register to read.\r |
| 512 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 513 | Range 0..15.\r |
| 514 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 515 | Range 0..15.\r |
| 516 | \r |
| 517 | @return The value of the bit field read from the PCI configuration register.\r |
| 518 | \r |
| 519 | **/\r |
| 520 | UINT16\r |
| 521 | EFIAPI\r |
| 522 | PciBitFieldRead16 (\r |
| 523 | IN UINTN Address,\r |
| 524 | IN UINTN StartBit,\r |
| 525 | IN UINTN EndBit\r |
| 526 | )\r |
| 527 | {\r |
| 528 | return PciExpressBitFieldRead16 (Address, StartBit, EndBit);\r |
| 529 | }\r |
| 530 | \r |
| 531 | /**\r |
| 532 | Writes a bit field to a PCI configuration register.\r |
| 533 | \r |
| 534 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 535 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 536 | destination PCI configuration register are preserved. The new value of the\r |
| 537 | 16-bit register is returned.\r |
| 538 | \r |
| 539 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 540 | If StartBit is greater than 15, then ASSERT().\r |
| 541 | If EndBit is greater than 15, then ASSERT().\r |
| 542 | If EndBit is less than StartBit, then ASSERT().\r |
| 543 | \r |
| 544 | @param Address PCI configuration register to write.\r |
| 545 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 546 | Range 0..15.\r |
| 547 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 548 | Range 0..15.\r |
| 549 | @param Value New value of the bit field.\r |
| 550 | \r |
| 551 | @return The value written back to the PCI configuration register.\r |
| 552 | \r |
| 553 | **/\r |
| 554 | UINT16\r |
| 555 | EFIAPI\r |
| 556 | PciBitFieldWrite16 (\r |
| 557 | IN UINTN Address,\r |
| 558 | IN UINTN StartBit,\r |
| 559 | IN UINTN EndBit,\r |
| 560 | IN UINT16 Value\r |
| 561 | )\r |
| 562 | {\r |
| 563 | return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value);\r |
| 564 | }\r |
| 565 | \r |
| 566 | /**\r |
| 567 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r |
| 568 | writes the result back to the bit field in the 16-bit port.\r |
| 569 | \r |
| 570 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 571 | bitwise inclusive OR between the read result and the value specified by\r |
| 572 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 573 | specified by Address. The value written to the PCI configuration register is\r |
| 574 | returned. This function must guarantee that all PCI read and write operations\r |
| 575 | are serialized. Extra left bits in OrData are stripped.\r |
| 576 | \r |
| 577 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 578 | If StartBit is greater than 15, then ASSERT().\r |
| 579 | If EndBit is greater than 15, then ASSERT().\r |
| 580 | If EndBit is less than StartBit, then ASSERT().\r |
| 581 | \r |
| 582 | @param Address PCI configuration register to write.\r |
| 583 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 584 | Range 0..15.\r |
| 585 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 586 | Range 0..15.\r |
| 587 | @param OrData The value to OR with the PCI configuration register.\r |
| 588 | \r |
| 589 | @return The value written back to the PCI configuration register.\r |
| 590 | \r |
| 591 | **/\r |
| 592 | UINT16\r |
| 593 | EFIAPI\r |
| 594 | PciBitFieldOr16 (\r |
| 595 | IN UINTN Address,\r |
| 596 | IN UINTN StartBit,\r |
| 597 | IN UINTN EndBit,\r |
| 598 | IN UINT16 OrData\r |
| 599 | )\r |
| 600 | {\r |
| 601 | return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData);\r |
| 602 | }\r |
| 603 | \r |
| 604 | /**\r |
| 605 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r |
| 606 | AND, and writes the result back to the bit field in the 16-bit register.\r |
| 607 | \r |
| 608 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 609 | bitwise AND between the read result and the value specified by AndData, and\r |
| 610 | writes the result to the 16-bit PCI configuration register specified by\r |
| 611 | Address. The value written to the PCI configuration register is returned.\r |
| 612 | This function must guarantee that all PCI read and write operations are\r |
| 613 | serialized. Extra left bits in AndData are stripped.\r |
| 614 | \r |
| 615 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 616 | If StartBit is greater than 15, then ASSERT().\r |
| 617 | If EndBit is greater than 15, then ASSERT().\r |
| 618 | If EndBit is less than StartBit, then ASSERT().\r |
| 619 | \r |
| 620 | @param Address PCI configuration register to write.\r |
| 621 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 622 | Range 0..15.\r |
| 623 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 624 | Range 0..15.\r |
| 625 | @param AndData The value to AND with the PCI configuration register.\r |
| 626 | \r |
| 627 | @return The value written back to the PCI configuration register.\r |
| 628 | \r |
| 629 | **/\r |
| 630 | UINT16\r |
| 631 | EFIAPI\r |
| 632 | PciBitFieldAnd16 (\r |
| 633 | IN UINTN Address,\r |
| 634 | IN UINTN StartBit,\r |
| 635 | IN UINTN EndBit,\r |
| 636 | IN UINT16 AndData\r |
| 637 | )\r |
| 638 | {\r |
| 639 | return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData);\r |
| 640 | }\r |
| 641 | \r |
| 642 | /**\r |
| 643 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r |
| 644 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 645 | 16-bit port.\r |
| 646 | \r |
| 647 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 648 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 649 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
| 650 | configuration register specified by Address. The value written to the PCI\r |
| 651 | configuration register is returned. This function must guarantee that all PCI\r |
| 652 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 653 | OrData are stripped.\r |
| 654 | \r |
| 655 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 656 | If StartBit is greater than 15, then ASSERT().\r |
| 657 | If EndBit is greater than 15, then ASSERT().\r |
| 658 | If EndBit is less than StartBit, then ASSERT().\r |
| 659 | \r |
| 660 | @param Address PCI configuration register to write.\r |
| 661 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 662 | Range 0..15.\r |
| 663 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 664 | Range 0..15.\r |
| 665 | @param AndData The value to AND with the PCI configuration register.\r |
| 666 | @param OrData The value to OR with the result of the AND operation.\r |
| 667 | \r |
| 668 | @return The value written back to the PCI configuration register.\r |
| 669 | \r |
| 670 | **/\r |
| 671 | UINT16\r |
| 672 | EFIAPI\r |
| 673 | PciBitFieldAndThenOr16 (\r |
| 674 | IN UINTN Address,\r |
| 675 | IN UINTN StartBit,\r |
| 676 | IN UINTN EndBit,\r |
| 677 | IN UINT16 AndData,\r |
| 678 | IN UINT16 OrData\r |
| 679 | )\r |
| 680 | {\r |
| 681 | return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);\r |
| 682 | }\r |
| 683 | \r |
| 684 | /**\r |
| 685 | Reads a 32-bit PCI configuration register.\r |
| 686 | \r |
| 687 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
| 688 | This function must guarantee that all PCI read and write operations are\r |
| 689 | serialized.\r |
| 690 | \r |
| 691 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 692 | \r |
| 693 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 694 | Register.\r |
| 695 | \r |
| 696 | @return The read value from the PCI configuration register.\r |
| 697 | \r |
| 698 | **/\r |
| 699 | UINT32\r |
| 700 | EFIAPI\r |
| 701 | PciRead32 (\r |
| 702 | IN UINTN Address\r |
| 703 | )\r |
| 704 | {\r |
| 705 | return PciExpressRead32 (Address);\r |
| 706 | }\r |
| 707 | \r |
| 708 | /**\r |
| 709 | Writes a 32-bit PCI configuration register.\r |
| 710 | \r |
| 711 | Writes the 32-bit PCI configuration register specified by Address with the\r |
| 712 | value specified by Value. Value is returned. This function must guarantee\r |
| 713 | that all PCI read and write operations are serialized.\r |
| 714 | \r |
| 715 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 716 | \r |
| 717 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 718 | Register.\r |
| 719 | @param Value The value to write.\r |
| 720 | \r |
| 721 | @return The value written to the PCI configuration register.\r |
| 722 | \r |
| 723 | **/\r |
| 724 | UINT32\r |
| 725 | EFIAPI\r |
| 726 | PciWrite32 (\r |
| 727 | IN UINTN Address,\r |
| 728 | IN UINT32 Data\r |
| 729 | )\r |
| 730 | {\r |
| 731 | return PciExpressWrite32 (Address, Data);\r |
| 732 | }\r |
| 733 | \r |
| 734 | /**\r |
| 735 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r |
| 736 | a 32-bit value.\r |
| 737 | \r |
| 738 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 739 | bitwise inclusive OR between the read result and the value specified by\r |
| 740 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 741 | specified by Address. The value written to the PCI configuration register is\r |
| 742 | returned. This function must guarantee that all PCI read and write operations\r |
| 743 | are serialized.\r |
| 744 | \r |
| 745 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 746 | \r |
| 747 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 748 | Register.\r |
| 749 | @param OrData The value to OR with the PCI configuration register.\r |
| 750 | \r |
| 751 | @return The value written back to the PCI configuration register.\r |
| 752 | \r |
| 753 | **/\r |
| 754 | UINT32\r |
| 755 | EFIAPI\r |
| 756 | PciOr32 (\r |
| 757 | IN UINTN Address,\r |
| 758 | IN UINT32 OrData\r |
| 759 | )\r |
| 760 | {\r |
| 761 | return PciExpressOr32 (Address, OrData);\r |
| 762 | }\r |
| 763 | \r |
| 764 | /**\r |
| 765 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 766 | value.\r |
| 767 | \r |
| 768 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 769 | bitwise AND between the read result and the value specified by AndData, and\r |
| 770 | writes the result to the 32-bit PCI configuration register specified by\r |
| 771 | Address. The value written to the PCI configuration register is returned.\r |
| 772 | This function must guarantee that all PCI read and write operations are\r |
| 773 | serialized.\r |
| 774 | \r |
| 775 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 776 | \r |
| 777 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 778 | Register.\r |
| 779 | @param AndData The value to AND with the PCI configuration register.\r |
| 780 | \r |
| 781 | @return The value written back to the PCI configuration register.\r |
| 782 | \r |
| 783 | **/\r |
| 784 | UINT32\r |
| 785 | EFIAPI\r |
| 786 | PciAnd32 (\r |
| 787 | IN UINTN Address,\r |
| 788 | IN UINT32 AndData\r |
| 789 | )\r |
| 790 | {\r |
| 791 | return PciExpressAnd32 (Address, AndData);\r |
| 792 | }\r |
| 793 | \r |
| 794 | /**\r |
| 795 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 796 | value, followed a bitwise inclusive OR with another 32-bit value.\r |
| 797 | \r |
| 798 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 799 | bitwise AND between the read result and the value specified by AndData,\r |
| 800 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 801 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
| 802 | configuration register specified by Address. The value written to the PCI\r |
| 803 | configuration register is returned. This function must guarantee that all PCI\r |
| 804 | read and write operations are serialized.\r |
| 805 | \r |
| 806 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 807 | \r |
| 808 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 809 | Register.\r |
| 810 | @param AndData The value to AND with the PCI configuration register.\r |
| 811 | @param OrData The value to OR with the result of the AND operation.\r |
| 812 | \r |
| 813 | @return The value written back to the PCI configuration register.\r |
| 814 | \r |
| 815 | **/\r |
| 816 | UINT32\r |
| 817 | EFIAPI\r |
| 818 | PciAndThenOr32 (\r |
| 819 | IN UINTN Address,\r |
| 820 | IN UINT32 AndData,\r |
| 821 | IN UINT32 OrData\r |
| 822 | )\r |
| 823 | {\r |
| 824 | return PciExpressAndThenOr32 (Address, AndData, OrData);\r |
| 825 | }\r |
| 826 | \r |
| 827 | /**\r |
| 828 | Reads a bit field of a PCI configuration register.\r |
| 829 | \r |
| 830 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r |
| 831 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 832 | returned.\r |
| 833 | \r |
| 834 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 835 | If StartBit is greater than 31, then ASSERT().\r |
| 836 | If EndBit is greater than 31, then ASSERT().\r |
| 837 | If EndBit is less than StartBit, then ASSERT().\r |
| 838 | \r |
| 839 | @param Address PCI configuration register to read.\r |
| 840 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 841 | Range 0..31.\r |
| 842 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 843 | Range 0..31.\r |
| 844 | \r |
| 845 | @return The value of the bit field read from the PCI configuration register.\r |
| 846 | \r |
| 847 | **/\r |
| 848 | UINT32\r |
| 849 | EFIAPI\r |
| 850 | PciBitFieldRead32 (\r |
| 851 | IN UINTN Address,\r |
| 852 | IN UINTN StartBit,\r |
| 853 | IN UINTN EndBit\r |
| 854 | )\r |
| 855 | {\r |
| 856 | return PciExpressBitFieldRead32 (Address, StartBit, EndBit);\r |
| 857 | }\r |
| 858 | \r |
| 859 | /**\r |
| 860 | Writes a bit field to a PCI configuration register.\r |
| 861 | \r |
| 862 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 863 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 864 | destination PCI configuration register are preserved. The new value of the\r |
| 865 | 32-bit register is returned.\r |
| 866 | \r |
| 867 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 868 | If StartBit is greater than 31, then ASSERT().\r |
| 869 | If EndBit is greater than 31, then ASSERT().\r |
| 870 | If EndBit is less than StartBit, then ASSERT().\r |
| 871 | \r |
| 872 | @param Address PCI configuration register to write.\r |
| 873 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 874 | Range 0..31.\r |
| 875 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 876 | Range 0..31.\r |
| 877 | @param Value New value of the bit field.\r |
| 878 | \r |
| 879 | @return The value written back to the PCI configuration register.\r |
| 880 | \r |
| 881 | **/\r |
| 882 | UINT32\r |
| 883 | EFIAPI\r |
| 884 | PciBitFieldWrite32 (\r |
| 885 | IN UINTN Address,\r |
| 886 | IN UINTN StartBit,\r |
| 887 | IN UINTN EndBit,\r |
| 888 | IN UINT32 Value\r |
| 889 | )\r |
| 890 | {\r |
| 891 | return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value);\r |
| 892 | }\r |
| 893 | \r |
| 894 | /**\r |
| 895 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r |
| 896 | writes the result back to the bit field in the 32-bit port.\r |
| 897 | \r |
| 898 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 899 | bitwise inclusive OR between the read result and the value specified by\r |
| 900 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 901 | specified by Address. The value written to the PCI configuration register is\r |
| 902 | returned. This function must guarantee that all PCI read and write operations\r |
| 903 | are serialized. Extra left bits in OrData are stripped.\r |
| 904 | \r |
| 905 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 906 | If StartBit is greater than 31, then ASSERT().\r |
| 907 | If EndBit is greater than 31, then ASSERT().\r |
| 908 | If EndBit is less than StartBit, then ASSERT().\r |
| 909 | \r |
| 910 | @param Address PCI configuration register to write.\r |
| 911 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 912 | Range 0..31.\r |
| 913 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 914 | Range 0..31.\r |
| 915 | @param OrData The value to OR with the PCI configuration register.\r |
| 916 | \r |
| 917 | @return The value written back to the PCI configuration register.\r |
| 918 | \r |
| 919 | **/\r |
| 920 | UINT32\r |
| 921 | EFIAPI\r |
| 922 | PciBitFieldOr32 (\r |
| 923 | IN UINTN Address,\r |
| 924 | IN UINTN StartBit,\r |
| 925 | IN UINTN EndBit,\r |
| 926 | IN UINT32 OrData\r |
| 927 | )\r |
| 928 | {\r |
| 929 | return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData);\r |
| 930 | }\r |
| 931 | \r |
| 932 | /**\r |
| 933 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r |
| 934 | AND, and writes the result back to the bit field in the 32-bit register.\r |
| 935 | \r |
| 936 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 937 | bitwise AND between the read result and the value specified by AndData, and\r |
| 938 | writes the result to the 32-bit PCI configuration register specified by\r |
| 939 | Address. The value written to the PCI configuration register is returned.\r |
| 940 | This function must guarantee that all PCI read and write operations are\r |
| 941 | serialized. Extra left bits in AndData are stripped.\r |
| 942 | \r |
| 943 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 944 | If StartBit is greater than 31, then ASSERT().\r |
| 945 | If EndBit is greater than 31, then ASSERT().\r |
| 946 | If EndBit is less than StartBit, then ASSERT().\r |
| 947 | \r |
| 948 | @param Address PCI configuration register to write.\r |
| 949 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 950 | Range 0..31.\r |
| 951 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 952 | Range 0..31.\r |
| 953 | @param AndData The value to AND with the PCI configuration register.\r |
| 954 | \r |
| 955 | @return The value written back to the PCI configuration register.\r |
| 956 | \r |
| 957 | **/\r |
| 958 | UINT32\r |
| 959 | EFIAPI\r |
| 960 | PciBitFieldAnd32 (\r |
| 961 | IN UINTN Address,\r |
| 962 | IN UINTN StartBit,\r |
| 963 | IN UINTN EndBit,\r |
| 964 | IN UINT32 AndData\r |
| 965 | )\r |
| 966 | {\r |
| 967 | return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData);\r |
| 968 | }\r |
| 969 | \r |
| 970 | /**\r |
| 971 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r |
| 972 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 973 | 32-bit port.\r |
| 974 | \r |
| 975 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 976 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 977 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
| 978 | configuration register specified by Address. The value written to the PCI\r |
| 979 | configuration register is returned. This function must guarantee that all PCI\r |
| 980 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 981 | OrData are stripped.\r |
| 982 | \r |
| 983 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 984 | If StartBit is greater than 31, then ASSERT().\r |
| 985 | If EndBit is greater than 31, then ASSERT().\r |
| 986 | If EndBit is less than StartBit, then ASSERT().\r |
| 987 | \r |
| 988 | @param Address PCI configuration register to write.\r |
| 989 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 990 | Range 0..31.\r |
| 991 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 992 | Range 0..31.\r |
| 993 | @param AndData The value to AND with the PCI configuration register.\r |
| 994 | @param OrData The value to OR with the result of the AND operation.\r |
| 995 | \r |
| 996 | @return The value written back to the PCI configuration register.\r |
| 997 | \r |
| 998 | **/\r |
| 999 | UINT32\r |
| 1000 | EFIAPI\r |
| 1001 | PciBitFieldAndThenOr32 (\r |
| 1002 | IN UINTN Address,\r |
| 1003 | IN UINTN StartBit,\r |
| 1004 | IN UINTN EndBit,\r |
| 1005 | IN UINT32 AndData,\r |
| 1006 | IN UINT32 OrData\r |
| 1007 | )\r |
| 1008 | {\r |
| 1009 | return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);\r |
| 1010 | }\r |
| 1011 | \r |
| 1012 | /**\r |
| 1013 | Reads a range of PCI configuration registers into a caller supplied buffer.\r |
| 1014 | \r |
| 1015 | Reads the range of PCI configuration registers specified by StartAddress and\r |
| 1016 | Size into the buffer specified by Buffer. This function only allows the PCI\r |
| 1017 | configuration registers from a single PCI function to be read. Size is\r |
| 1018 | returned. When possible 32-bit PCI configuration read cycles are used to read\r |
| 1019 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
| 1020 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
| 1021 | end of the range.\r |
| 1022 | \r |
| 1023 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1024 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 1025 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1026 | \r |
| 1027 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1028 | Function and Register.\r |
| 1029 | @param Size Size in bytes of the transfer.\r |
| 1030 | @param Buffer Pointer to a buffer receiving the data read.\r |
| 1031 | \r |
| 1032 | @return Size\r |
| 1033 | \r |
| 1034 | **/\r |
| 1035 | UINTN\r |
| 1036 | EFIAPI\r |
| 1037 | PciReadBuffer (\r |
| 1038 | IN UINTN StartAddress,\r |
| 1039 | IN UINTN Size,\r |
| 1040 | OUT VOID *Buffer\r |
| 1041 | )\r |
| 1042 | {\r |
| 1043 | return PciExpressReadBuffer (StartAddress, Size, Buffer);\r |
| 1044 | }\r |
| 1045 | \r |
| 1046 | /**\r |
| 1047 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
| 1048 | configuration space.\r |
| 1049 | \r |
| 1050 | Writes the range of PCI configuration registers specified by StartAddress and\r |
| 1051 | Size from the buffer specified by Buffer. This function only allows the PCI\r |
| 1052 | configuration registers from a single PCI function to be written. Size is\r |
| 1053 | returned. When possible 32-bit PCI configuration write cycles are used to\r |
| 1054 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r |
| 1055 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
| 1056 | and the end of the range.\r |
| 1057 | \r |
| 1058 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1059 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 1060 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1061 | \r |
| 1062 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1063 | Function and Register.\r |
| 1064 | @param Size Size in bytes of the transfer.\r |
| 1065 | @param Buffer Pointer to a buffer containing the data to write.\r |
| 1066 | \r |
| 1067 | @return Size\r |
| 1068 | \r |
| 1069 | **/\r |
| 1070 | UINTN\r |
| 1071 | EFIAPI\r |
| 1072 | PciWriteBuffer (\r |
| 1073 | IN UINTN StartAddress,\r |
| 1074 | IN UINTN Size,\r |
| 1075 | IN VOID *Buffer\r |
| 1076 | )\r |
| 1077 | {\r |
| 1078 | return PciExpressWriteBuffer (StartAddress, Size, Buffer);\r |
| 1079 | }\r |
projects / mirror_edk2.git / blame