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[mirror_edk2.git] / OldMdePkg / Include / Ipf / IpfDefines.h
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878ddf1f 1///** @file\r
2// IPF Processor Defines for assembly code\r
3//\r
4// @note\r
5// This file is included by assembly files as well. The assmber can NOT deal\r
6// with /* */ commnets this is why this file is commented not following the\r
7// coding standard\r
8//\r
9//Copyright (c) 2006, Intel Corporation\r
10//All rights reserved. This program and the accompanying materials\r
11//are licensed and made available under the terms and conditions of the BSD License\r
12//which accompanies this distribution. The full text of the license may be found at\r
13//http://opensource.org/licenses/bsd-license.php\r
14//\r
15//THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16//WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17//\r
18//Module Name: IpfDefines.h\r
19//\r
20//**/\r
21\r
22#ifndef _IPFDEFINES_H\r
23#define _IPFDEFINES_H\r
24\r
25//\r
26// IPI DElivery Methods\r
27//\r
28#define IPI_INT_DELIVERY 0x0\r
29#define IPI_PMI_DELIVERY 0x2\r
30#define IPI_NMI_DELIVERY 0x4\r
31#define IPI_INIT_DELIVERY 0x5\r
32#define IPI_ExtINT_DELIVERY 0x7\r
33\r
34//\r
35// Define Itanium-based system registers.\r
36//\r
37// Define Itanium-based system register bit field offsets.\r
38//\r
39// Processor Status Register (PSR) Bit positions\r
40//\r
41// User / System mask\r
42//\r
43#define PSR_RV0 0\r
44#define PSR_BE 1\r
45#define PSR_UP 2\r
46#define PSR_AC 3\r
47#define PSR_MFL 4\r
48#define PSR_MFH 5\r
49\r
50//\r
51// PSR bits 6-12 reserved (must be zero)\r
52//\r
53#define PSR_MBZ0 6\r
54#define PSR_MBZ0_V 0x1ffUL L\r
55\r
56//\r
57// System only mask\r
58//\r
59#define PSR_IC 13\r
60#define PSR_IC_MASK (1 << 13)\r
61#define PSR_I 14\r
62#define PSR_PK 15\r
63#define PSR_MBZ1 16\r
64#define PSR_MBZ1_V 0x1UL L\r
65#define PSR_DT 17\r
66#define PSR_DFL 18\r
67#define PSR_DFH 19\r
68#define PSR_SP 20\r
69#define PSR_PP 21\r
70#define PSR_DI 22\r
71#define PSR_SI 23\r
72#define PSR_DB 24\r
73#define PSR_LP 25\r
74#define PSR_TB 26\r
75#define PSR_RT 27\r
76\r
77//\r
78// PSR bits 28-31 reserved (must be zero)\r
79//\r
80#define PSR_MBZ2 28\r
81#define PSR_MBZ2_V 0xfUL L\r
82\r
83//\r
84// Neither mask\r
85//\r
86#define PSR_CPL 32\r
87#define PSR_CPL_LEN 2\r
88#define PSR_IS 34\r
89#define PSR_MC 35\r
90#define PSR_IT 36\r
91#define PSR_IT_MASK 0x1000000000\r
92#define PSR_ID 37\r
93#define PSR_DA 38\r
94#define PSR_DD 39\r
95#define PSR_SS 40\r
96#define PSR_RI 41\r
97#define PSR_RI_LEN 2\r
98#define PSR_ED 43\r
99#define PSR_BN 44\r
100\r
101//\r
102// PSR bits 45-63 reserved (must be zero)\r
103//\r
104#define PSR_MBZ3 45\r
105#define PSR_MBZ3_V 0xfffffUL L\r
106\r
107//\r
108// Floating Point Status Register (FPSR) Bit positions\r
109//\r
110//\r
111// Traps\r
112//\r
113#define FPSR_VD 0\r
114#define FPSR_DD 1\r
115#define FPSR_ZD 2\r
116#define FPSR_OD 3\r
117#define FPSR_UD 4\r
118#define FPSR_ID 5\r
119\r
120//\r
121// Status Field 0 - Controls\r
122//\r
123#define FPSR0_FTZ0 6\r
124#define FPSR0_WRE0 7\r
125#define FPSR0_PC0 8\r
126#define FPSR0_RC0 10\r
127#define FPSR0_TD0 12\r
128\r
129//\r
130// Status Field 0 - Flags\r
131//\r
132#define FPSR0_V0 13\r
133#define FPSR0_D0 14\r
134#define FPSR0_Z0 15\r
135#define FPSR0_O0 16\r
136#define FPSR0_U0 17\r
137#define FPSR0_I0 18\r
138\r
139//\r
140// Status Field 1 - Controls\r
141//\r
142#define FPSR1_FTZ0 19\r
143#define FPSR1_WRE0 20\r
144#define FPSR1_PC0 21\r
145#define FPSR1_RC0 23\r
146#define FPSR1_TD0 25\r
147\r
148//\r
149// Status Field 1 - Flags\r
150//\r
151#define FPSR1_V0 26\r
152#define FPSR1_D0 27\r
153#define FPSR1_Z0 28\r
154#define FPSR1_O0 29\r
155#define FPSR1_U0 30\r
156#define FPSR1_I0 31\r
157\r
158//\r
159// Status Field 2 - Controls\r
160//\r
161#define FPSR2_FTZ0 32\r
162#define FPSR2_WRE0 33\r
163#define FPSR2_PC0 34\r
164#define FPSR2_RC0 36\r
165#define FPSR2_TD0 38\r
166\r
167//\r
168// Status Field 2 - Flags\r
169//\r
170#define FPSR2_V0 39\r
171#define FPSR2_D0 40\r
172#define FPSR2_Z0 41\r
173#define FPSR2_O0 42\r
174#define FPSR2_U0 43\r
175#define FPSR2_I0 44\r
176\r
177//\r
178// Status Field 3 - Controls\r
179//\r
180#define FPSR3_FTZ0 45\r
181#define FPSR3_WRE0 46\r
182#define FPSR3_PC0 47\r
183#define FPSR3_RC0 49\r
184#define FPSR3_TD0 51\r
185\r
186//\r
187// Status Field 0 - Flags\r
188//\r
189#define FPSR3_V0 52\r
190#define FPSR3_D0 53\r
191#define FPSR3_Z0 54\r
192#define FPSR3_O0 55\r
193#define FPSR3_U0 56\r
194#define FPSR3_I0 57\r
195\r
196//\r
197// FPSR bits 58-63 Reserved -- Must be zero\r
198//\r
199#define FPSR_MBZ0 58\r
200#define FPSR_MBZ0_V 0x3fUL L\r
201\r
202//\r
203// For setting up FPSR on kernel entry\r
204// All traps are disabled.\r
205//\r
206#define FPSR_FOR_KERNEL 0x3f\r
207\r
208#define FP_REG_SIZE 16 // 16 byte spill size\r
209#define HIGHFP_REGS_LENGTH (96 * 16)\r
210\r
211//\r
212// Define hardware Task Priority Register (TPR)\r
213//\r
214//\r
215// TPR bit positions\r
216//\r
217#define TPR_MIC 4 // Bits 0 - 3 ignored\r
218#define TPR_MIC_LEN 4\r
219#define TPR_MMI 16 // Mask Maskable Interrupt\r
220//\r
221// Define hardware Interrupt Status Register (ISR)\r
222//\r
223//\r
224// ISR bit positions\r
225//\r
226#define ISR_CODE 0\r
227#define ISR_CODE_LEN 16\r
228#define ISR_CODE_MASK 0xFFFF\r
229#define ISR_IA_VECTOR 16\r
230#define ISR_IA_VECTOR_LEN 8\r
231#define ISR_MBZ0 24\r
232#define ISR_MBZ0_V 0xff\r
233#define ISR_X 32\r
234#define ISR_W 33\r
235#define ISR_R 34\r
236#define ISR_NA 35\r
237#define ISR_SP 36\r
238#define ISR_RS 37\r
239#define ISR_IR 38\r
240#define ISR_NI 39\r
241#define ISR_MBZ1 40\r
242#define ISR_EI 41\r
243#define ISR_ED 43\r
244#define ISR_MBZ2 44\r
245#define ISR_MBZ2_V 0xfffff\r
246\r
247//\r
248// ISR codes\r
249//\r
250// For General exceptions: ISR{3:0}\r
251//\r
252#define ISR_ILLEGAL_OP 0 // Illegal operation fault\r
253#define ISR_PRIV_OP 1 // Privileged operation fault\r
254#define ISR_PRIV_REG 2 // Privileged register fauls\r
255#define ISR_RESVD_REG 3 // Reserved register/field flt\r
256#define ISR_ILLEGAL_ISA 4 // Disabled instruction set transition fault\r
257//\r
258// Define hardware Default Control Register (DCR)\r
259//\r
260//\r
261// DCR bit positions\r
262//\r
263#define DCR_PP 0\r
264#define DCR_BE 1\r
265#define DCR_LC 2\r
266#define DCR_MBZ0 4\r
267#define DCR_MBZ0_V 0xf\r
268#define DCR_DM 8\r
269#define DCR_DP 9\r
270#define DCR_DK 10\r
271#define DCR_DX 11\r
272#define DCR_DR 12\r
273#define DCR_DA 13\r
274#define DCR_DD 14\r
275#define DCR_DEFER_ALL 0x7f00\r
276#define DCR_MBZ1 2\r
277#define DCR_MBZ1_V 0xffffffffffffUL L\r
278\r
279//\r
280// Define hardware RSE Configuration Register\r
281//\r
282// RS Configuration (RSC) bit field positions\r
283//\r
284#define RSC_MODE 0\r
285#define RSC_PL 2\r
286#define RSC_BE 4\r
287#define RSC_MBZ0 5\r
288#define RSC_MBZ0_V 0x3ff\r
289#define RSC_LOADRS 16\r
290#define RSC_LOADRS_LEN 14\r
291#define RSC_MBZ1 30\r
292#define RSC_MBZ1_V 0x3ffffffffUL L\r
293\r
294//\r
295// RSC modes\r
296//\r
297#define RSC_MODE_LY (0x0) // Lazy\r
298#define RSC_MODE_SI (0x1) // Store intensive\r
299#define RSC_MODE_LI (0x2) // Load intensive\r
300#define RSC_MODE_EA (0x3) // Eager\r
301//\r
302// RSC Endian bit values\r
303//\r
304#define RSC_BE_LITTLE 0\r
305#define RSC_BE_BIG 1\r
306\r
307//\r
308// Define Interruption Function State (IFS) Register\r
309//\r
310// IFS bit field positions\r
311//\r
312#define IFS_IFM 0\r
313#define IFS_IFM_LEN 38\r
314#define IFS_MBZ0 38\r
315#define IFS_MBZ0_V 0x1ffffff\r
316#define IFS_V 63\r
317#define IFS_V_LEN 1\r
318\r
319//\r
320// IFS is valid when IFS_V = IFS_VALID\r
321//\r
322#define IFS_VALID 1\r
323\r
324//\r
325// Define Page Table Address (PTA)\r
326//\r
327#define PTA_VE 0\r
328#define PTA_VF 8\r
329#define PTA_SIZE 2\r
330#define PTA_SIZE_LEN 6\r
331#define PTA_BASE 15\r
332\r
333//\r
334// Define Region Register (RR)\r
335//\r
336//\r
337// RR bit field positions\r
338//\r
339#define RR_VE 0\r
340#define RR_MBZ0 1\r
341#define RR_PS 2\r
342#define RR_PS_LEN 6\r
343#define RR_RID 8\r
344#define RR_RID_LEN 24\r
345#define RR_MBZ1 32\r
346\r
347//\r
348// SAL uses region register 0 and RID of 1000\r
349//\r
350#define SAL_RID 0x1000\r
351#define SAL_RR_REG 0x0\r
352#define SAL_TR 0x0\r
353\r
354//\r
355// Total number of region registers\r
356//\r
357#define RR_SIZE 8\r
358\r
359//\r
360// Define Protection Key Register (PKR)\r
361//\r
362// PKR bit field positions\r
363//\r
364#define PKR_V 0\r
365#define PKR_WD 1\r
366#define PKR_RD 2\r
367#define PKR_XD 3\r
368#define PKR_MBZ0 4\r
369#define PKR_KEY 8\r
370#define PKR_KEY_LEN 24\r
371#define PKR_MBZ1 32\r
372\r
373#define PKR_VALID (1 << PKR_V)\r
374\r
375//\r
376// Number of protection key registers\r
377//\r
378#define PKRNUM 8\r
379\r
380//\r
381// Define Interruption TLB Insertion register (ITIR)\r
382//\r
383//\r
384// Define Translation Insertion Format (TR)\r
385//\r
386// PTE0 bit field positions\r
387//\r
388#define PTE0_P 0\r
389#define PTE0_MBZ0 1\r
390#define PTE0_MA 2\r
391#define PTE0_A 5\r
392#define PTE0_D 6\r
393#define PTE0_PL 7\r
394#define PTE0_AR 9\r
395#define PTE0_PPN 12\r
396#define PTE0_MBZ1 48\r
397#define PTE0_ED 52\r
398#define PTE0_IGN0 53\r
399\r
400//\r
401// ITIR bit field positions\r
402//\r
403#define ITIR_MBZ0 0\r
404#define ITIR_PS 2\r
405#define ITIR_PS_LEN 6\r
406#define ITIR_KEY 8\r
407#define ITIR_KEY_LEN 24\r
408#define ITIR_MBZ1 32\r
409#define ITIR_MBZ1_LEN 16\r
410#define ITIR_PPN 48\r
411#define ITIR_PPN_LEN 15\r
412#define ITIR_MBZ2 63\r
413\r
414#define ATTR_IPAGE 0x661 // Access Rights = RWX (bits 11-9=011), PL 0(8-7=0)\r
415#define ATTR_DEF_BITS 0x661 // Access Rights = RWX (bits 11-9=010), PL 0(8-7=0)\r
416// Dirty (bit 6=1), Accessed (bit 5=1),\r
417// MA WB (bits 4-2=000), Present (bit 0=1)\r
418//\r
419// Memory access rights\r
420//\r
421#define AR_UR_KR 0x0 // user/kernel read\r
422#define AR_URX_KRX 0x1 // user/kernel read and execute\r
423#define AR_URW_KRW 0x2 // user/kernel read & write\r
424#define AR_URWX_KRWX 0x3 // user/kernel read,write&execute\r
425#define AR_UR_KRW 0x4 // user read/kernel read,write\r
426#define AR_URX_KRWX 0x5 // user read/execute, kernel all\r
427#define AR_URWX_KRW 0x6 // user all, kernel read & write\r
428#define AR_UX_KRX 0x7 // user execute only, kernel read and execute\r
429//\r
430// Memory attribute values\r
431//\r
432//\r
433// The next 4 are all cached, non-sequential & speculative, coherent\r
434//\r
435#define MA_WBU 0x0 // Write back, unordered\r
436//\r
437// The next 3 are all non-cached, sequential & non-speculative\r
438//\r
439#define MA_UC 0x4 // Non-coalescing, sequential & non-speculative\r
440#define MA_UCE 0x5 // Non-coalescing, sequential, non-speculative\r
441// & fetchadd exported\r
442//\r
443#define MA_WC 0x6 // Non-cached, Coalescing, non-seq., spec.\r
444#define MA_NAT 0xf // NaT page\r
445//\r
446// Definition of the offset of TRAP/INTERRUPT/FAULT handlers from the\r
447// base of IVA (Interruption Vector Address)\r
448//\r
449#define IVT_SIZE 0x8000\r
450#define EXTRA_ALIGNMENT 0x1000\r
451\r
452#define OFF_VHPTFLT 0x0000 // VHPT Translation fault\r
453#define OFF_ITLBFLT 0x0400 // Instruction TLB fault\r
454#define OFF_DTLBFLT 0x0800 // Data TLB fault\r
455#define OFF_ALTITLBFLT 0x0C00 // Alternate ITLB fault\r
456#define OFF_ALTDTLBFLT 0x1000 // Alternate DTLB fault\r
457#define OFF_NESTEDTLBFLT 0x1400 // Nested TLB fault\r
458#define OFF_IKEYMISSFLT 0x1800 // Inst Key Miss fault\r
459#define OFF_DKEYMISSFLT 0x1C00 // Data Key Miss fault\r
460#define OFF_DIRTYBITFLT 0x2000 // Dirty-Bit fault\r
461#define OFF_IACCESSBITFLT 0x2400 // Inst Access-Bit fault\r
462#define OFF_DACCESSBITFLT 0x2800 // Data Access-Bit fault\r
463#define OFF_BREAKFLT 0x2C00 // Break Inst fault\r
464#define OFF_EXTINT 0x3000 // External Interrupt\r
465//\r
466// Offset 0x3400 to 0x0x4C00 are reserved\r
467//\r
468#define OFF_PAGENOTPFLT 0x5000 // Page Not Present fault\r
469#define OFF_KEYPERMFLT 0x5100 // Key Permission fault\r
470#define OFF_IACCESSRTFLT 0x5200 // Inst Access-Rights flt\r
471#define OFF_DACCESSRTFLT 0x5300 // Data Access-Rights fault\r
472#define OFF_GPFLT 0x5400 // General Exception fault\r
473#define OFF_FPDISFLT 0x5500 // Disable-FP fault\r
474#define OFF_NATFLT 0x5600 // NAT Consumption fault\r
475#define OFF_SPECLNFLT 0x5700 // Speculation fault\r
476#define OFF_DBGFLT 0x5900 // Debug fault\r
477#define OFF_ALIGNFLT 0x5A00 // Unaligned Reference fault\r
478#define OFF_LOCKDREFFLT 0x5B00 // Locked Data Reference fault\r
479#define OFF_FPFLT 0x5C00 // Floating Point fault\r
480#define OFF_FPTRAP 0x5D00 // Floating Point Trap\r
481#define OFF_LOPRIVTRAP 0x5E00 // Lower-Privilege Transfer Trap\r
482#define OFF_TAKENBRTRAP 0x5F00 // Taken Branch Trap\r
483#define OFF_SSTEPTRAP 0x6000 // Single Step Trap\r
484//\r
485// Offset 0x6100 to 0x6800 are reserved\r
486//\r
487#define OFF_IA32EXCEPTN 0x6900 // iA32 Exception\r
488#define OFF_IA32INTERCEPT 0x6A00 // iA32 Intercept\r
489#define OFF_IA32INT 0x6B00 // iA32 Interrupt\r
490#define NUMBER_OF_VECTORS 0x100\r
491//\r
492// Privilege levels\r
493//\r
494#define PL_KERNEL 0\r
495#define PL_USER 3\r
496\r
497//\r
498// Instruction set (IS) bits\r
499//\r
500#define IS_IA64 0\r
501#define IS_IA 1\r
502\r
503//\r
504// RSC while in kernel: enabled, little endian, PL = 0, eager mode\r
505//\r
506#define RSC_KERNEL ((RSC_MODE_EA << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))\r
507\r
508//\r
509// Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode\r
510//\r
511#define RSC_KERNEL_LAZ ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))\r
512\r
513//\r
514// RSE disabled: disabled, PL = 0, little endian, eager mode\r
515//\r
516#define RSC_KERNEL_DISABLED ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))\r
517\r
518#define NAT_BITS_PER_RNAT_REG 63\r
519\r
520//\r
521// Macros for generating PTE0 and PTE1 value\r
522//\r
523#define PTE0(ed, ppn12_47, ar, pl, d, a, ma, p) \\r
524 ( ( ed << PTE0_ED ) | \\r
525 ( ppn12_47 << PTE0_PPN ) | \\r
526 ( ar << PTE0_AR ) | \\r
527 ( pl << PTE0_PL ) | \\r
528 ( d << PTE0_D ) | \\r
529 ( a << PTE0_A ) | \\r
530 ( ma << PTE0_MA ) | \\r
531 ( p << PTE0_P ) \\r
532 )\r
533\r
534#define ITIR(ppn48_63, key, ps) \\r
535 ( ( ps << ITIR_PS ) | \\r
536 ( key << ITIR_KEY ) | \\r
537 ( ppn48_63 << ITIR_PPN ) \\r
538 )\r
539\r
540//\r
541// Macro to generate mask value from bit position. The result is a\r
542// 64-bit.\r
543//\r
544#define BITMASK(bp, value) (value << bp)\r
545\r
546#define BUNDLE_SIZE 16\r
547#define SPURIOUS_INT 0xF\r
548\r
549#define FAST_DISABLE_INTERRUPTS rsm BITMASK (PSR_I, 1);;\r
550\r
551#define FAST_ENABLE_INTERRUPTS ssm BITMASK (PSR_I, 1);;\r
552\r
553#endif\r