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Check in library class declaration for SAL Lib, together with related definition.
[mirror_edk2.git] / OldMdePkg / Include / Ipf / SalApi.h
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878ddf1f 1/** @file\r
2 Main SAL API's defined in SAL 3.0 specification. \r
3\r
4 Copyright (c) 2006, Intel Corporation \r
5 All rights reserved. This program and the accompanying materials \r
6 are licensed and made available under the terms and conditions of the BSD License \r
7 which accompanies this distribution. The full text of the license may be found at \r
8 http://opensource.org/licenses/bsd-license.php \r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
12\r
13 Module Name: SalApi.h\r
14\r
15**/\r
16\r
17#ifndef __SAL_API_H__\r
18#define __SAL_API_H__\r
19\r
4e3f1861 20//\r
21// FIT Types \r
22// Table 2-2 of Intel Itanium Processor Family System Abstraction Layer Specification December 2003\r
23//\r
24#define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00\r
25#define EFI_SAL_FIT_PAL_B_TYPE 0x01\r
26//\r
27// type from 0x02 to 0x0E is reserved.\r
28//\r
29#define EFI_SAL_FIT_PAL_A_TYPE 0x0F\r
30//\r
31// OEM-defined type range is from 0x10 to 0x7E. Here we defined the PEI_CORE type as 0x10\r
32//\r
33#define EFI_SAL_FIT_PEI_CORE_TYPE 0x10\r
34#define EFI_SAL_FIT_UNUSED_TYPE 0x7F\r
878ddf1f 35\r
36//\r
4e3f1861 37// EFI_SAL_STATUS \r
878ddf1f 38//\r
4e3f1861 39typedef UINTN EFI_SAL_STATUS;\r
40\r
878ddf1f 41#define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)\r
42#define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)\r
43#define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)\r
44#define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)\r
45#define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)\r
46#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)\r
47#define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)\r
48#define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)\r
49\r
9c89ec98 50//\r
51// Return values from SAL\r
52//\r
53typedef struct {\r
54 EFI_SAL_STATUS Status; // register r8\r
55 UINTN r9;\r
56 UINTN r10;\r
57 UINTN r11;\r
58} SAL_RETURN_REGS;\r
59\r
7ac2bbc1 60//\r
61// Delivery Mode of IPF CPU.\r
62//\r
63typedef enum {\r
64 EFI_DELIVERY_MODE_INT,\r
65 EFI_DELIVERY_MODE_MPreserved1,\r
66 EFI_DELIVERY_MODE_PMI,\r
67 EFI_DELIVERY_MODE_MPreserved2,\r
68 EFI_DELIVERY_MODE_NMI,\r
69 EFI_DELIVERY_MODE_INIT,\r
70 EFI_DELIVERY_MODE_MPreserved3,\r
71 EFI_DELIVERY_MODE_ExtINT\r
72} EFI_DELIVERY_MODE;\r
73\r
878ddf1f 74typedef SAL_RETURN_REGS (EFIAPI *SAL_PROC)\r
75 (\r
76 IN UINT64 FunctionId,\r
77 IN UINT64 Arg2,\r
78 IN UINT64 Arg3,\r
79 IN UINT64 Arg4,\r
80 IN UINT64 Arg5,\r
81 IN UINT64 Arg6,\r
82 IN UINT64 Arg7,\r
83 IN UINT64 Arg8\r
84 );\r
85\r
86//\r
87// SAL Procedure FunctionId definition\r
88//\r
89#define EFI_SAL_SET_VECTORS 0x01000000\r
90#define EFI_SAL_GET_STATE_INFO 0x01000001\r
91#define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002\r
92#define EFI_SAL_CLEAR_STATE_INFO 0x01000003\r
93#define EFI_SAL_MC_RENDEZ 0x01000004\r
94#define EFI_SAL_MC_SET_PARAMS 0x01000005\r
95#define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006\r
96#define EFI_SAL_CACHE_FLUSH 0x01000008\r
97#define EFI_SAL_CACHE_INIT 0x01000009\r
98#define EFI_SAL_PCI_CONFIG_READ 0x01000010\r
99#define EFI_SAL_PCI_CONFIG_WRITE 0x01000011\r
100#define EFI_SAL_FREQ_BASE 0x01000012\r
a197b1ad 101#define EFI_SAL_PHYSICAL_ID_INFO 0x01000013\r
878ddf1f 102#define EFI_SAL_UPDATE_PAL 0x01000020\r
103\r
104#define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff\r
105#define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021\r
106\r
107//\r
108// SAL Procedure parameter definitions\r
109// Not much point in using typedefs or enums because all params\r
110// are UINT64 and the entry point is common\r
111//\r
112// EFI_SAL_SET_VECTORS\r
113//\r
114#define EFI_SAL_SET_MCA_VECTOR 0x0\r
115#define EFI_SAL_SET_INIT_VECTOR 0x1\r
116#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2\r
117\r
118typedef struct {\r
119 UINT64 Length : 32;\r
120 UINT64 ChecksumValid : 1;\r
121 UINT64 Reserved1 : 7;\r
122 UINT64 ByteChecksum : 8;\r
123 UINT64 Reserved2 : 16;\r
124} SAL_SET_VECTORS_CS_N;\r
125\r
126//\r
127// EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,\r
128// EFI_SAL_CLEAR_STATE_INFO\r
129//\r
130#define EFI_SAL_MCA_STATE_INFO 0x0\r
131#define EFI_SAL_INIT_STATE_INFO 0x1\r
132#define EFI_SAL_CMC_STATE_INFO 0x2\r
133#define EFI_SAL_CP_STATE_INFO 0x3\r
134\r
135//\r
136// EFI_SAL_MC_SET_PARAMS\r
137//\r
138#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1\r
139#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2\r
140#define EFI_SAL_MC_SET_CPE_PARAM 0x3\r
141\r
142#define EFI_SAL_MC_SET_INTR_PARAM 0x1\r
143#define EFI_SAL_MC_SET_MEM_PARAM 0x2\r
144\r
145//\r
146// EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR\r
147//\r
148#define EFI_SAL_REGISTER_PAL_ADDR 0x0\r
149\r
150//\r
151// EFI_SAL_CACHE_FLUSH\r
152//\r
153#define EFI_SAL_FLUSH_I_CACHE 0x01\r
154#define EFI_SAL_FLUSH_D_CACHE 0x02\r
155#define EFI_SAL_FLUSH_BOTH_CACHE 0x03\r
156#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04\r
157\r
158//\r
159// EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE\r
160//\r
161#define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1\r
162#define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2\r
163#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4\r
164\r
165typedef struct {\r
166 UINT64 Register : 8;\r
167 UINT64 Function : 3;\r
168 UINT64 Device : 5;\r
169 UINT64 Bus : 8;\r
170 UINT64 Segment : 8;\r
171 UINT64 Reserved : 32;\r
172} SAL_PCI_ADDRESS;\r
173\r
174//\r
175// EFI_SAL_FREQ_BASE\r
176//\r
177#define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0\r
178#define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1\r
179#define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2\r
180\r
181//\r
182// EFI_SAL_UPDATE_PAL\r
183//\r
184#define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)\r
185#define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)\r
186#define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)\r
187#define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)\r
188#define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)\r
189#define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)\r
190#define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)\r
191#define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)\r
192\r
193typedef struct {\r
194 UINT32 Size;\r
195 UINT32 MmddyyyyDate;\r
196 UINT16 Version;\r
197 UINT8 Type;\r
198 UINT8 Reserved[5];\r
199 UINT64 FwVendorId;\r
200} SAL_UPDATE_PAL_DATA_BLOCK;\r
201\r
202typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {\r
203 struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;\r
204 struct SAL_UPDATE_PAL_DATA_BLOCK *DataBlock;\r
205 UINT8 StoreChecksum;\r
206 UINT8 Reserved[15];\r
207} SAL_UPDATE_PAL_INFO_BLOCK;\r
208\r
209//\r
210// SAL System Table Definitions\r
211//\r
212#pragma pack(1)\r
213typedef struct {\r
214 UINT32 Signature;\r
215 UINT32 Length;\r
216 UINT16 SalRevision;\r
217 UINT16 EntryCount;\r
218 UINT8 CheckSum;\r
219 UINT8 Reserved[7];\r
220 UINT16 SalAVersion;\r
221 UINT16 SalBVersion;\r
222 UINT8 OemId[32];\r
223 UINT8 ProductId[32];\r
224 UINT8 Reserved2[8];\r
225} SAL_SYSTEM_TABLE_HEADER;\r
226#pragma pack()\r
227\r
228#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"\r
229#define EFI_SAL_REVISION 0x0300\r
230//\r
231// SAL System Types\r
232//\r
233#define EFI_SAL_ST_ENTRY_POINT 0\r
234#define EFI_SAL_ST_MEMORY_DESCRIPTOR 1\r
235#define EFI_SAL_ST_PLATFORM_FEATURES 2\r
236#define EFI_SAL_ST_TR_USAGE 3\r
237#define EFI_SAL_ST_PTC 4\r
238#define EFI_SAL_ST_AP_WAKEUP 5\r
239\r
240#pragma pack(1)\r
241typedef struct {\r
242 UINT8 Type; // Type == 0\r
243 UINT8 Reserved[7];\r
244 UINT64 PalProcEntry;\r
245 UINT64 SalProcEntry;\r
246 UINT64 SalGlobalDataPointer;\r
247 UINT64 Reserved2[2];\r
248} SAL_ST_ENTRY_POINT_DESCRIPTOR;\r
249\r
250//\r
251// Not needed for Itanium-based OS boot\r
252//\r
253typedef struct {\r
254 UINT8 Type; // Type == 1\r
255 UINT8 NeedVirtualRegistration;\r
256 UINT8 MemoryAttributes;\r
257 UINT8 PageAccessRights;\r
258 UINT8 SupportedAttributes;\r
259 UINT8 Reserved;\r
260 UINT8 MemoryType;\r
261 UINT8 MemoryUsage;\r
262 UINT64 PhysicalMemoryAddress;\r
263 UINT32 Length;\r
264 UINT32 Reserved1;\r
265 UINT64 OemReserved;\r
266} SAL_ST_MEMORY_DESCRIPTOR_ENTRY;\r
267\r
268#pragma pack()\r
269//\r
270// Memory Attributes\r
271//\r
272#define SAL_MDT_ATTRIB_WB 0x00\r
273//\r
274// #define SAL_MDT_ATTRIB_UC 0x02\r
275//\r
276#define SAL_MDT_ATTRIB_UC 0x04\r
277#define SAL_MDT_ATTRIB_UCE 0x05\r
278#define SAL_MDT_ATTRIB_WC 0x06\r
279\r
280//\r
281// Supported memory Attributes\r
282//\r
283#define SAL_MDT_SUPPORT_WB 0x1\r
284#define SAL_MDT_SUPPORT_UC 0x2\r
285#define SAL_MDT_SUPPORT_UCE 0x4\r
286#define SAL_MDT_SUPPORT_WC 0x8\r
287\r
288//\r
289// Virtual address registration\r
290//\r
291#define SAL_MDT_NO_VA 0x00\r
292#define SAL_MDT_NEED_VA 0x01\r
293//\r
294// MemoryType info\r
295//\r
296#define SAL_REGULAR_MEMORY 0x0000\r
297#define SAL_MMIO_MAPPING 0x0001\r
298#define SAL_SAPIC_IPI_BLOCK 0x0002\r
299#define SAL_IO_PORT_MAPPING 0x0003\r
300#define SAL_FIRMWARE_MEMORY 0x0004\r
301#define SAL_BLACK_HOLE 0x000A\r
302//\r
303// Memory Usage info\r
304//\r
305#define SAL_MDT_USAGE_UNSPECIFIED 0x00\r
306#define SAL_PAL_CODE 0x01\r
307#define SAL_BOOTSERVICE_CODE 0x02\r
308#define SAL_BOOTSERVICE_DATA 0x03\r
309#define SAL_RUNTIMESERVICE_CODE 0x04\r
310#define SAL_RUNTIMESERVICE_DATA 0x05\r
311#define SAL_IA32_OPTIONROM 0x06\r
312#define SAL_IA32_SYSTEMROM 0x07\r
313#define SAL_PMI_CODE 0x0a\r
314#define SAL_PMI_DATA 0x0b\r
315\r
316#pragma pack(1)\r
317typedef struct {\r
318 UINT8 Type; // Type == 2\r
319 UINT8 PlatformFeatures;\r
320 UINT8 Reserved[14];\r
321} SAL_ST_PLATFORM_FEATURES;\r
322#pragma pack()\r
323\r
324#define SAL_PLAT_FEAT_BUS_LOCK 0x01\r
325#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02\r
326#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04\r
327\r
328#pragma pack(1)\r
329typedef struct {\r
330 UINT8 Type; // Type == 3\r
331 UINT8 TRType;\r
332 UINT8 TRNumber;\r
333 UINT8 Reserved[5];\r
334 UINT64 VirtualAddress;\r
335 UINT64 EncodedPageSize;\r
336 UINT64 Reserved1;\r
337} SAL_ST_TR_DECRIPTOR;\r
338#pragma pack()\r
339\r
340#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00\r
341#define EFI_SAL_ST_TR_USAGE_DATA 01\r
342\r
343#pragma pack(1)\r
344typedef struct {\r
345 UINT64 NumberOfProcessors;\r
346 UINT64 LocalIDRegister;\r
347} SAL_COHERENCE_DOMAIN_INFO;\r
348#pragma pack()\r
349\r
350#pragma pack(1)\r
351typedef struct {\r
352 UINT8 Type; // Type == 4\r
353 UINT8 Reserved[3];\r
354 UINT32 NumberOfDomains;\r
355 SAL_COHERENCE_DOMAIN_INFO *DomainInformation;\r
356} SAL_ST_CACHE_COHERENCE_DECRIPTOR;\r
357#pragma pack()\r
358\r
359#pragma pack(1)\r
360typedef struct {\r
361 UINT8 Type; // Type == 5\r
362 UINT8 WakeUpType;\r
363 UINT8 Reserved[6];\r
364 UINT64 ExternalInterruptVector;\r
365} SAL_ST_AP_WAKEUP_DECRIPTOR;\r
366#pragma pack()\r
367//\r
368// FIT Entry\r
369//\r
370#define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24\r
371#define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32\r
372#define EFI_SAL_FIT_PALB_TYPE 01\r
373\r
374typedef struct {\r
375 UINT64 Address;\r
376 UINT8 Size[3];\r
377 UINT8 Reserved;\r
378 UINT16 Revision;\r
379 UINT8 Type : 7;\r
380 UINT8 CheckSumValid : 1;\r
381 UINT8 CheckSum;\r
382} EFI_SAL_FIT_ENTRY;\r
383\r
384//\r
385// SAL Common Record Header\r
386//\r
387typedef struct {\r
388 UINT16 Length;\r
389 UINT8 Data[1024];\r
390} SAL_OEM_DATA;\r
391\r
392typedef struct {\r
393 UINT8 Seconds;\r
394 UINT8 Minutes;\r
395 UINT8 Hours;\r
396 UINT8 Reserved;\r
397 UINT8 Day;\r
398 UINT8 Month;\r
399 UINT8 Year;\r
400 UINT8 Century;\r
401} SAL_TIME_STAMP;\r
402\r
403typedef struct {\r
404 UINT64 RecordId;\r
405 UINT16 Revision;\r
406 UINT8 ErrorSeverity;\r
407 UINT8 ValidationBits;\r
408 UINT32 RecordLength;\r
409 SAL_TIME_STAMP TimeStamp;\r
410 UINT8 OemPlatformId[16];\r
411} SAL_RECORD_HEADER;\r
412\r
413typedef struct {\r
414 EFI_GUID Guid;\r
415 UINT16 Revision;\r
416 UINT8 ErrorRecoveryInfo;\r
417 UINT8 Reserved;\r
418 UINT32 SectionLength;\r
419} SAL_SEC_HEADER;\r
420\r
421//\r
422// SAL Processor Record\r
423//\r
424#define SAL_PROCESSOR_ERROR_RECORD_INFO \\r
425 { \\r
426 0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
427 }\r
428\r
429#define CHECK_INFO_VALID_BIT_MASK 0x1\r
430#define REQUESTOR_ID_VALID_BIT_MASK 0x2\r
431#define RESPONDER_ID_VALID_BIT_MASK 0x4\r
432#define TARGER_ID_VALID_BIT_MASK 0x8\r
433#define PRECISE_IP_VALID_BIT_MASK 0x10\r
434\r
435typedef struct {\r
436 UINT64 InfoValid : 1;\r
437 UINT64 ReqValid : 1;\r
438 UINT64 RespValid : 1;\r
439 UINT64 TargetValid : 1;\r
440 UINT64 IpValid : 1;\r
441 UINT64 Reserved : 59;\r
442 UINT64 Info;\r
443 UINT64 Req;\r
444 UINT64 Resp;\r
445 UINT64 Target;\r
446 UINT64 Ip;\r
447} MOD_ERROR_INFO;\r
448\r
449typedef struct {\r
450 UINT8 CpuidInfo[40];\r
451 UINT8 Reserved;\r
452} CPUID_INFO;\r
453\r
454typedef struct {\r
455 UINT64 FrLow;\r
456 UINT64 FrHigh;\r
457} FR_STRUCT;\r
458\r
459#define MIN_STATE_VALID_BIT_MASK 0x1\r
460#define BR_VALID_BIT_MASK 0x2\r
461#define CR_VALID_BIT_MASK 0x4\r
462#define AR_VALID_BIT_MASK 0x8\r
463#define RR_VALID_BIT_MASK 0x10\r
464#define FR_VALID_BIT_MASK 0x20\r
465\r
466typedef struct {\r
467 UINT64 ValidFieldBits;\r
468 UINT8 MinStateInfo[1024];\r
469 UINT64 Br[8];\r
470 UINT64 Cr[128];\r
471 UINT64 Ar[128];\r
472 UINT64 Rr[8];\r
473 FR_STRUCT Fr[128];\r
474} PSI_STATIC_STRUCT;\r
475\r
476#define PROC_ERROR_MAP_VALID_BIT_MASK 0x1\r
477#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2\r
478#define PROC_CR_LID_VALID_BIT_MASK 0x4\r
479#define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8\r
480#define CPU_INFO_VALID_BIT_MASK 0x1000000\r
481\r
482typedef struct {\r
483 SAL_SEC_HEADER SectionHeader;\r
484 UINT64 ValidationBits;\r
485 UINT64 ProcErrorMap;\r
486 UINT64 ProcStateParameter;\r
487 UINT64 ProcCrLid;\r
488 MOD_ERROR_INFO CacheError[15];\r
489 MOD_ERROR_INFO TlbError[15];\r
490 MOD_ERROR_INFO BusError[15];\r
491 MOD_ERROR_INFO RegFileCheck[15];\r
492 MOD_ERROR_INFO MsCheck[15];\r
493 CPUID_INFO CpuInfo;\r
494 PSI_STATIC_STRUCT PsiValidData;\r
495} SAL_PROCESSOR_ERROR_RECORD;\r
496\r
497//\r
498// Sal Platform memory Error Record\r
499//\r
500#define SAL_MEMORY_ERROR_RECORD_INFO \\r
501 { \\r
502 0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
503 }\r
504\r
505#define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1\r
506#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2\r
507#define MEMORY_ADDR_BIT_MASK 0x4\r
508#define MEMORY_NODE_VALID_BIT_MASK 0x8\r
509#define MEMORY_CARD_VALID_BIT_MASK 0x10\r
510#define MEMORY_MODULE_VALID_BIT_MASK 0x20\r
511#define MEMORY_BANK_VALID_BIT_MASK 0x40\r
512#define MEMORY_DEVICE_VALID_BIT_MASK 0x80\r
513#define MEMORY_ROW_VALID_BIT_MASK 0x100\r
514#define MEMORY_COLUMN_VALID_BIT_MASK 0x200\r
515#define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400\r
516#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800\r
517#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000\r
518#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000\r
519#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000\r
520#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000\r
521#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000\r
522\r
523typedef struct {\r
524 SAL_SEC_HEADER SectionHeader;\r
525 UINT64 ValidationBits;\r
526 UINT64 MemErrorStatus;\r
527 UINT64 MemPhysicalAddress;\r
528 UINT64 MemPhysicalAddressMask;\r
529 UINT16 MemNode;\r
530 UINT16 MemCard;\r
531 UINT16 MemModule;\r
532 UINT16 MemBank;\r
533 UINT16 MemDevice;\r
534 UINT16 MemRow;\r
535 UINT16 MemColumn;\r
536 UINT16 MemBitPosition;\r
537 UINT64 ModRequestorId;\r
538 UINT64 ModResponderId;\r
539 UINT64 ModTargetId;\r
540 UINT64 BusSpecificData;\r
541 UINT8 MemPlatformOemId[16];\r
542} SAL_MEMORY_ERROR_RECORD;\r
543\r
544//\r
545// PCI BUS Errors\r
546//\r
547#define SAL_PCI_BUS_ERROR_RECORD_INFO \\r
548 { \\r
549 0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
550 }\r
551\r
552#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1\r
553#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2\r
554#define PCI_BUS_ID_VALID_BIT_MASK 0x4\r
555#define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8\r
556#define PCI_BUS_DATA_VALID_BIT_MASK 0x10\r
557#define PCI_BUS_CMD_VALID_BIT_MASK 0x20\r
558#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40\r
559#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80\r
560#define PCI_BUS_TARGET_VALID_BIT_MASK 0x100\r
561#define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200\r
562#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400\r
563\r
564typedef struct {\r
565 UINT8 BusNumber;\r
566 UINT8 SegmentNumber;\r
567} PCI_BUS_ID;\r
568\r
569typedef struct {\r
570 SAL_SEC_HEADER SectionHeader;\r
571 UINT64 ValidationBits;\r
572 UINT64 PciBusErrorStatus;\r
573 UINT16 PciBusErrorType;\r
574 PCI_BUS_ID PciBusId;\r
575 UINT32 Reserved;\r
576 UINT64 PciBusAddress;\r
577 UINT64 PciBusData;\r
578 UINT64 PciBusCommand;\r
579 UINT64 PciBusRequestorId;\r
580 UINT64 PciBusResponderId;\r
581 UINT64 PciBusTargetId;\r
582 UINT8 PciBusOemId[16];\r
583} SAL_PCI_BUS_ERROR_RECORD;\r
584\r
585//\r
586// PCI Component Errors\r
587//\r
588#define SAL_PCI_COMP_ERROR_RECORD_INFO \\r
589 { \\r
590 0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
591 }\r
592\r
593#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1\r
594#define PCI_COMP_INFO_VALID_BIT_MASK 0x2\r
595#define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4\r
596#define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8\r
597#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10\r
598#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20\r
599\r
600typedef struct {\r
601 UINT16 VendorId;\r
602 UINT16 DeviceId;\r
603 UINT8 ClassCode[3];\r
604 UINT8 FunctionNumber;\r
605 UINT8 DeviceNumber;\r
606 UINT8 BusNumber;\r
607 UINT8 SegmentNumber;\r
608 UINT8 Reserved[5];\r
609} PCI_COMP_INFO;\r
610\r
611typedef struct {\r
612 SAL_SEC_HEADER SectionHeader;\r
613 UINT64 ValidationBits;\r
614 UINT64 PciComponentErrorStatus;\r
615 PCI_COMP_INFO PciComponentInfo;\r
616 UINT32 PciComponentMemNum;\r
617 UINT32 PciComponentIoNum;\r
618 UINT8 PciBusOemId[16];\r
619} SAL_PCI_COMPONENT_ERROR_RECORD;\r
620\r
621//\r
622// Sal Device Errors Info.\r
623//\r
624#define SAL_DEVICE_ERROR_RECORD_INFO \\r
625 { \\r
626 0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
627 }\r
628\r
629#define SEL_RECORD_ID_VALID_BIT_MASK 0x1;\r
630#define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;\r
631#define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;\r
632#define SEL_EVM_REV_VALID_BIT_MASK 0x8;\r
633#define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;\r
634#define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;\r
635#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;\r
636#define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;\r
637#define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;\r
638#define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;\r
639\r
640typedef struct {\r
641 SAL_SEC_HEADER SectionHeader;\r
642 UINT64 ValidationBits;\r
643 UINT16 SelRecordId;\r
644 UINT8 SelRecordType;\r
645 UINT32 TimeStamp;\r
646 UINT16 GeneratorId;\r
647 UINT8 EvmRevision;\r
648 UINT8 SensorType;\r
649 UINT8 SensorNum;\r
650 UINT8 EventDirType;\r
651 UINT8 Data1;\r
652 UINT8 Data2;\r
653 UINT8 Data3;\r
654} SAL_DEVICE_ERROR_RECORD;\r
655\r
656//\r
657// Sal SMBIOS Device Errors Info.\r
658//\r
659#define SAL_SMBIOS_ERROR_RECORD_INFO \\r
660 { \\r
661 0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
662 }\r
663\r
664#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1\r
665#define SMBIOS_LENGTH_VALID_BIT_MASK 0x2\r
666#define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4\r
667#define SMBIOS_DATA_VALID_BIT_MASK 0x8\r
668\r
669typedef struct {\r
670 SAL_SEC_HEADER SectionHeader;\r
671 UINT64 ValidationBits;\r
672 UINT8 SmbiosEventType;\r
673 UINT8 SmbiosLength;\r
674 UINT8 SmbiosBcdTimeStamp[6];\r
675} SAL_SMBIOS_DEVICE_ERROR_RECORD;\r
676\r
677//\r
678// Sal Platform Specific Errors Info.\r
679//\r
680#define SAL_PLATFORM_ERROR_RECORD_INFO \\r
681 { \\r
682 0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
683 }\r
684\r
685#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1\r
686#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2\r
687#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4\r
688#define PLATFORM_TARGET_VALID_BIT_MASK 0x8\r
689#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10\r
690#define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20\r
691#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40\r
692#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80\r
693\r
694typedef struct {\r
695 SAL_SEC_HEADER SectionHeader;\r
696 UINT64 ValidationBits;\r
697 UINT64 PlatformErrorStatus;\r
698 UINT64 PlatformRequestorId;\r
699 UINT64 PlatformResponderId;\r
700 UINT64 PlatformTargetId;\r
701 UINT64 PlatformBusSpecificData;\r
702 UINT8 OemComponentId[16];\r
703} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;\r
704\r
705//\r
706// Union of all the possible Sal Record Types\r
707//\r
708typedef union {\r
709 SAL_RECORD_HEADER *RecordHeader;\r
710 SAL_PROCESSOR_ERROR_RECORD *SalProcessorRecord;\r
711 SAL_PCI_BUS_ERROR_RECORD *SalPciBusRecord;\r
712 SAL_PCI_COMPONENT_ERROR_RECORD *SalPciComponentRecord;\r
713 SAL_DEVICE_ERROR_RECORD *ImpiRecord;\r
714 SAL_SMBIOS_DEVICE_ERROR_RECORD *SmbiosRecord;\r
715 SAL_PLATFORM_SPECIFIC_ERROR_RECORD *PlatformRecord;\r
716 SAL_MEMORY_ERROR_RECORD *MemoryRecord;\r
717 UINT8 *Raw;\r
718} SAL_ERROR_RECORDS_POINTERS;\r
719\r
720#pragma pack()\r
721\r
722#endif\r
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