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1e57a462 | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
209b8f3c | 4 | Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>\r |
1e57a462 | 5 | \r |
538311f7 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
1e57a462 | 7 | \r |
8 | **/\r | |
9 | \r | |
10 | #ifndef __OMAP3530INTERRUPT_H__\r | |
11 | #define __OMAP3530INTERRUPT_H__\r | |
12 | \r | |
209b8f3c LL |
13 | #include <Library/PcdLib.h>\r |
14 | \r | |
15 | #define INTERRUPT_BASE (PcdGet32 (PcdInterruptBaseAddress))\r | |
1e57a462 | 16 | \r |
17 | #define INT_NROF_VECTORS (96)\r | |
18 | #define MAX_VECTOR (INT_NROF_VECTORS - 1)\r | |
19 | #define INTCPS_SYSCONFIG (INTERRUPT_BASE + 0x0010)\r | |
20 | #define INTCPS_SYSSTATUS (INTERRUPT_BASE + 0x0014)\r | |
21 | #define INTCPS_SIR_IRQ (INTERRUPT_BASE + 0x0040)\r | |
22 | #define INTCPS_SIR_IFQ (INTERRUPT_BASE + 0x0044)\r | |
23 | #define INTCPS_CONTROL (INTERRUPT_BASE + 0x0048)\r | |
24 | #define INTCPS_PROTECTION (INTERRUPT_BASE + 0x004C)\r | |
25 | #define INTCPS_IDLE (INTERRUPT_BASE + 0x0050)\r | |
26 | #define INTCPS_IRQ_PRIORITY (INTERRUPT_BASE + 0x0060)\r | |
27 | #define INTCPS_FIQ_PRIORITY (INTERRUPT_BASE + 0x0064)\r | |
28 | #define INTCPS_THRESHOLD (INTERRUPT_BASE + 0x0068)\r | |
29 | #define INTCPS_ITR(n) (INTERRUPT_BASE + 0x0080 + (0x20 * (n)))\r | |
30 | #define INTCPS_MIR(n) (INTERRUPT_BASE + 0x0084 + (0x20 * (n)))\r | |
31 | #define INTCPS_MIR_CLEAR(n) (INTERRUPT_BASE + 0x0088 + (0x20 * (n)))\r | |
32 | #define INTCPS_MIR_SET(n) (INTERRUPT_BASE + 0x008C + (0x20 * (n)))\r | |
33 | #define INTCPS_ISR_SET(n) (INTERRUPT_BASE + 0x0090 + (0x20 * (n)))\r | |
34 | #define INTCPS_ISR_CLEAR(n) (INTERRUPT_BASE + 0x0094 + (0x20 * (n)))\r | |
35 | #define INTCPS_PENDING_IRQ(n) (INTERRUPT_BASE + 0x0098 + (0x20 * (n)))\r | |
36 | #define INTCPS_PENDING_FIQ(n) (INTERRUPT_BASE + 0x009C + (0x20 * (n)))\r | |
37 | #define INTCPS_ILR(m) (INTERRUPT_BASE + 0x0100 + (0x04 * (m)))\r | |
38 | \r | |
39 | #define INTCPS_ILR_FIQ BIT0\r | |
40 | #define INTCPS_SIR_IRQ_MASK (0x7F)\r | |
41 | #define INTCPS_CONTROL_NEWIRQAGR BIT0\r | |
42 | #define INTCPS_CONTROL_NEWFIQAGR BIT1\r | |
43 | \r | |
44 | #endif // __OMAP3530INTERRUPT_H__\r | |
45 | \r |