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a3f98646 | 1 | /** @file\r |
2 | \r | |
3d70643b | 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
3402aac7 | 4 | \r |
3d70643b | 5 | This program and the accompanying materials\r |
a3f98646 | 6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
570d030a | 15 | #include <Uefi.h>\r |
a3f98646 | 16 | \r |
17 | #include <Library/BaseLib.h>\r | |
18 | #include <Library/TimerLib.h>\r | |
19 | #include <Library/DebugLib.h>\r | |
20 | #include <Library/PcdLib.h>\r | |
21 | #include <Library/IoLib.h>\r | |
22 | #include <Library/OmapLib.h>\r | |
23 | \r | |
24 | #include <Omap3530/Omap3530.h>\r | |
25 | \r | |
570d030a | 26 | RETURN_STATUS\r |
27 | EFIAPI\r | |
28 | TimerConstructor (\r | |
29 | VOID\r | |
30 | )\r | |
31 | {\r | |
32 | UINTN Timer = PcdGet32(PcdOmap35xxFreeTimer);\r | |
33 | UINT32 TimerBaseAddress = TimerBase(Timer);\r | |
34 | \r | |
35 | if ((MmioRead32 (TimerBaseAddress + GPTIMER_TCLR) & TCLR_ST_ON) == 0) {\r | |
36 | // Set source clock for GPT3 & GPT4 to SYS_CLK\r | |
37 | MmioOr32 (CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);\r | |
38 | \r | |
39 | // Set count & reload registers\r | |
40 | MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000);\r | |
41 | MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000);\r | |
42 | \r | |
43 | // Disable interrupts\r | |
44 | MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);\r | |
45 | \r | |
46 | // Start Timer\r | |
47 | MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);\r | |
48 | \r | |
49 | // Disable OMAP Watchdog timer (WDT2)\r | |
50 | MmioWrite32 (WDTIMER2_BASE + WSPR, 0xAAAA);\r | |
51 | DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n"));\r | |
52 | MmioWrite32 (WDTIMER2_BASE + WSPR, 0x5555);\r | |
53 | }\r | |
54 | return EFI_SUCCESS;\r | |
55 | }\r | |
56 | \r | |
a3f98646 | 57 | UINTN\r |
58 | EFIAPI\r | |
59 | MicroSecondDelay (\r | |
60 | IN UINTN MicroSeconds\r | |
61 | )\r | |
62 | {\r | |
63 | UINT64 NanoSeconds;\r | |
3402aac7 | 64 | \r |
a3f98646 | 65 | NanoSeconds = MultU64x32(MicroSeconds, 1000);\r |
66 | \r | |
3402aac7 | 67 | while (NanoSeconds > (UINTN)-1) {\r |
a3f98646 | 68 | NanoSecondDelay((UINTN)-1);\r |
69 | NanoSeconds -= (UINTN)-1;\r | |
70 | }\r | |
71 | \r | |
72 | NanoSecondDelay(NanoSeconds);\r | |
73 | \r | |
74 | return MicroSeconds;\r | |
75 | }\r | |
76 | \r | |
77 | UINTN\r | |
78 | EFIAPI\r | |
79 | NanoSecondDelay (\r | |
80 | IN UINTN NanoSeconds\r | |
81 | )\r | |
82 | {\r | |
83 | UINT32 Delay;\r | |
84 | UINT32 StartTime;\r | |
85 | UINT32 CurrentTime;\r | |
86 | UINT32 ElapsedTime;\r | |
87 | UINT32 TimerCountRegister;\r | |
88 | \r | |
55bff42e | 89 | Delay = (NanoSeconds / PcdGet32(PcdEmbeddedPerformanceCounterPeriodInNanoseconds)) + 1;\r |
3402aac7 | 90 | \r |
43263288 | 91 | TimerCountRegister = TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TCRR;\r |
a3f98646 | 92 | \r |
43263288 | 93 | StartTime = MmioRead32 (TimerCountRegister);\r |
a3f98646 | 94 | \r |
3402aac7 | 95 | do\r |
a3f98646 | 96 | {\r |
43263288 | 97 | CurrentTime = MmioRead32 (TimerCountRegister);\r |
a3f98646 | 98 | ElapsedTime = CurrentTime - StartTime;\r |
99 | } while (ElapsedTime < Delay);\r | |
100 | \r | |
55bff42e | 101 | NanoSeconds = ElapsedTime * PcdGet32(PcdEmbeddedPerformanceCounterPeriodInNanoseconds);\r |
a3f98646 | 102 | \r |
103 | return NanoSeconds;\r | |
104 | }\r | |
105 | \r | |
106 | UINT64\r | |
107 | EFIAPI\r | |
108 | GetPerformanceCounter (\r | |
109 | VOID\r | |
110 | )\r | |
3402aac7 | 111 | {\r |
43263288 | 112 | return (UINT64)MmioRead32 (TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TCRR);\r |
a3f98646 | 113 | }\r |
114 | \r | |
115 | UINT64\r | |
116 | EFIAPI\r | |
117 | GetPerformanceCounterProperties (\r | |
118 | OUT UINT64 *StartValue, OPTIONAL\r | |
119 | OUT UINT64 *EndValue OPTIONAL\r | |
120 | )\r | |
121 | {\r | |
122 | if (StartValue != NULL) {\r | |
123 | // Timer starts with the reload value\r | |
43263288 | 124 | *StartValue = (UINT64)MmioRead32 (TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TLDR);\r |
a3f98646 | 125 | }\r |
3402aac7 | 126 | \r |
a3f98646 | 127 | if (EndValue != NULL) {\r |
128 | // Timer counts up to 0xFFFFFFFF\r | |
129 | *EndValue = 0xFFFFFFFF;\r | |
130 | }\r | |
3402aac7 | 131 | \r |
55bff42e | 132 | return PcdGet64(PcdEmbeddedPerformanceCounterFrequencyInHz);\r |
a3f98646 | 133 | }\r |