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OvmfPkg: _DIS and _SRS methods should have permanent effect
[mirror_edk2.git] / OvmfPkg / AcpiTables / Dsdt.asl
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49ba9447 1/** @file\r
2 Contains root level name space objects for the platform\r
0228e598 3\r
56d7640a
HT		 4 Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>\r
5 This program and the accompanying materials are\r
49ba9447 6 licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
0228e598 9\r
49ba9447 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
0228e598 13**/\r
49ba9447 14\r
15DefinitionBlock ("Dsdt.aml", "DSDT", 1, "INTEL ", "OVMF ", 3) {\r
16 //\r
17 // System Sleep States\r
18 //\r
19 Name (\_S0, Package () {5, 0, 0, 0})\r
20 Name (\_S4, Package () {1, 0, 0, 0})\r
21 Name (\_S5, Package () {0, 0, 0, 0})\r
22\r
23 //\r
24 // System Bus\r
25 //\r
26 Scope (\_SB) {\r
27 //\r
28 // PCI Root Bridge\r
29 //\r
30 Device (PCI0) {\r
31 Name (_HID, EISAID ("PNP0A03"))\r
32 Name (_ADR, 0x00000000)\r
33 Name (_BBN, 0x00)\r
34 Name (_UID, 0x00)\r
35\r
36 //\r
37 // BUS, I/O, and MMIO resources\r
38 //\r
cf98e61d 39 Name (CRES, ResourceTemplate () {\r
49ba9447 40 WORDBusNumber ( // Bus number resource (0); the bridge produces bus numbers for its subsequent buses\r
41 ResourceProducer, // bit 0 of general flags is 1\r
42 MinFixed, // Range is fixed\r
43 MaxFixed, // Range is fixed\r
44 PosDecode, // PosDecode\r
45 0x0000, // Granularity\r
46 0x0000, // Min\r
47 0x00FF, // Max\r
48 0x0000, // Translation\r
49 0x0100 // Range Length = Max-Min+1\r
50 )\r
51\r
52 IO (Decode16, 0xCF8, 0xCF8, 0x01, 0x08) //Consumed resource (0xCF8-0xCFF)\r
53\r
54 WORDIO ( // Consumed-and-produced resource (all I/O below CF8)\r
55 ResourceProducer, // bit 0 of general flags is 0\r
56 MinFixed, // Range is fixed\r
57 MaxFixed, // Range is fixed\r
0228e598 58 PosDecode,\r
49ba9447 59 EntireRange,\r
60 0x0000, // Granularity\r
61 0x0000, // Min\r
62 0x0CF7, // Max\r
63 0x0000, // Translation\r
64 0x0CF8 // Range Length\r
65 )\r
66\r
67 WORDIO ( // Consumed-and-produced resource (all I/O above CFF)\r
68 ResourceProducer, // bit 0 of general flags is 0\r
69 MinFixed, // Range is fixed\r
70 MaxFixed, // Range is fixed\r
0228e598 71 PosDecode,\r
49ba9447 72 EntireRange,\r
73 0x0000, // Granularity\r
74 0x0D00, // Min\r
75 0xFFFF, // Max\r
76 0x0000, // Translation\r
77 0xF300 // Range Length\r
78 )\r
79\r
80 DWORDMEMORY ( // Descriptor for legacy VGA video RAM\r
81 ResourceProducer, // bit 0 of general flags is 0\r
82 PosDecode,\r
83 MinFixed, // Range is fixed\r
84 MaxFixed, // Range is Fixed\r
85 Cacheable,\r
86 ReadWrite,\r
87 0x00000000, // Granularity\r
88 0x000A0000, // Min\r
89 0x000BFFFF, // Max\r
90 0x00000000, // Translation\r
91 0x00020000 // Range Length\r
92 )\r
93\r
cf98e61d 94 DWORDMEMORY ( // Descriptor for 32-bit MMIO\r
49ba9447 95 ResourceProducer, // bit 0 of general flags is 0\r
96 PosDecode,\r
97 MinFixed, // Range is fixed\r
98 MaxFixed, // Range is Fixed\r
cf98e61d 99 NonCacheable,\r
49ba9447 100 ReadWrite,\r
101 0x00000000, // Granularity\r
102 0xF8000000, // Min\r
103 0xFFFBFFFF, // Max\r
104 0x00000000, // Translation\r
cf98e61d 105 0x07FC0000, // Range Length\r
106 , // ResourceSourceIndex\r
107 , // ResourceSource\r
108 PW32 // DescriptorName\r
49ba9447 109 )\r
110 })\r
111\r
cf98e61d 112 Name (CR64, ResourceTemplate () {\r
113 QWordMemory ( // Descriptor for 64-bit MMIO\r
114 ResourceProducer, // bit 0 of general flags is 0\r
115 PosDecode,\r
116 MinFixed, // Range is fixed\r
117 MaxFixed, // Range is Fixed\r
118 Cacheable,\r
119 ReadWrite,\r
120 0x00000000, // Granularity\r
121 0x8000000000, // Min\r
122 0xFFFFFFFFFF, // Max\r
123 0x00000000, // Translation\r
124 0x8000000000, // Range Length\r
125 , // ResourceSourceIndex\r
126 , // ResourceSource\r
127 PW64 // DescriptorName\r
128 )\r
129 })\r
130\r
131 Method (_CRS, 0) {\r
132 //\r
133 // see the FIRMWARE_DATA structure in "OvmfPkg/AcpiPlatformDxe/Qemu.c"\r
134 //\r
135 External (FWDT, OpRegionObj)\r
136 Field(FWDT, QWordAcc, NoLock, Preserve) {\r
137 P0S, 64, // PciWindow32.Base\r
138 P0E, 64, // PciWindow32.End\r
139 P0L, 64, // PciWindow32.Length\r
140 P1S, 64, // PciWindow64.Base\r
141 P1E, 64, // PciWindow64.End\r
142 P1L, 64 // PciWindow64.Length\r
143 }\r
144 Field(FWDT, DWordAcc, NoLock, Preserve) {\r
145 P0SL, 32, // PciWindow32.Base, low 32 bits\r
146 P0SH, 32, // PciWindow32.Base, high 32 bits\r
147 P0EL, 32, // PciWindow32.End, low 32 bits\r
148 P0EH, 32, // PciWindow32.End, high 32 bits\r
149 P0LL, 32, // PciWindow32.Length, low 32 bits\r
150 P0LH, 32, // PciWindow32.Length, high 32 bits\r
151 P1SL, 32, // PciWindow64.Base, low 32 bits\r
152 P1SH, 32, // PciWindow64.Base, high 32 bits\r
153 P1EL, 32, // PciWindow64.End, low 32 bits\r
154 P1EH, 32, // PciWindow64.End, high 32 bits\r
155 P1LL, 32, // PciWindow64.Length, low 32 bits\r
156 P1LH, 32 // PciWindow64.Length, high 32 bits\r
157 }\r
158\r
159 //\r
160 // fixup 32-bit PCI IO window\r
161 //\r
162 CreateDWordField (CRES, \_SB.PCI0.PW32._MIN, PS32)\r
163 CreateDWordField (CRES, \_SB.PCI0.PW32._MAX, PE32)\r
164 CreateDWordField (CRES, \_SB.PCI0.PW32._LEN, PL32)\r
165 Store (P0SL, PS32)\r
166 Store (P0EL, PE32)\r
167 Store (P0LL, PL32)\r
168\r
169 If (LAnd (LEqual (P1SL, 0x00), LEqual (P1SH, 0x00))) {\r
170 Return (CRES)\r
171 } Else {\r
172 //\r
173 // fixup 64-bit PCI IO window\r
174 //\r
175 CreateQWordField (CR64, \_SB.PCI0.PW64._MIN, PS64)\r
176 CreateQWordField (CR64, \_SB.PCI0.PW64._MAX, PE64)\r
177 CreateQWordField (CR64, \_SB.PCI0.PW64._LEN, PL64)\r
178 Store (P1S, PS64)\r
179 Store (P1E, PE64)\r
180 Store (P1L, PL64)\r
181\r
182 //\r
183 // add window and return result\r
184 //\r
185 ConcatenateResTemplate (CRES, CR64, Local0)\r
186 Return (Local0)\r
187 }\r
188 }\r
189\r
49ba9447 190 //\r
191 // PCI Interrupt Routing Table - PIC Mode Only\r
192 //\r
193 Method (_PRT, 0, NotSerialized) {\r
194 Return (\r
195 Package () {\r
196 //\r
197 // Bus 0, Device 1\r
198 //\r
199 Package () {0x0001FFFF, 0x00, \_SB.PCI0.LPC.LNKA, 0x00},\r
200 Package () {0x0001FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},\r
201 Package () {0x0001FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},\r
202 Package () {0x0001FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},\r
203 //\r
204 // Bus 0, Device 3\r
205 //\r
206 Package () {0x0003FFFF, 0x00, \_SB.PCI0.LPC.LNKA, 0x00},\r
207 Package () {0x0003FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},\r
208 Package () {0x0003FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},\r
209 Package () {0x0003FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},\r
210 }\r
211 )\r
212 }\r
213\r
214 //\r
215 // PCI to ISA Bridge (Bus 0, Device 1, Function 0)\r
216 //\r
217 Device (LPC) {\r
218 Name (_ADR, 0x00010000)\r
219\r
220 //\r
221 // PCI Interrupt Routing Configuration Registers\r
222 //\r
223 OperationRegion (PRR0, PCI_Config, 0x60, 0x04)\r
224 Field (PRR0, ANYACC, NOLOCK, PRESERVE) {\r
225 PIRA, 8,\r
226 PIRB, 8,\r
227 PIRC, 8,\r
228 PIRD, 8\r
229 }\r
230\r
231 //\r
232 // _STA method for LNKA, LNKB, LNKC, LNKD\r
233 //\r
234 Method (PSTA, 1, NotSerialized) {\r
235 If (And (Arg0, 0x80)) {\r
236 Return (0x9)\r
237 } Else {\r
238 Return (0xB)\r
239 }\r
240 }\r
241\r
49ba9447 242 //\r
243 // _CRS method for LNKA, LNKB, LNKC, LNKD\r
244 //\r
245 Method (PCRS, 1, NotSerialized) {\r
49ba9447 246 //\r
cc16a929 247 // create temporary buffer with an Extended Interrupt Descriptor\r
248 // whose single vector defaults to zero\r
49ba9447 249 //\r
cc16a929 250 Name (BUF0, ResourceTemplate () {\r
56daf8b9 251 Interrupt (ResourceConsumer, Level, ActiveHigh, Shared){0}\r
cc16a929 252 }\r
253 )\r
254\r
49ba9447 255 //\r
cc16a929 256 // define reference to first interrupt vector in buffer\r
49ba9447 257 //\r
cc16a929 258 CreateDWordField (BUF0, 0x05, IRQW)\r
259\r
49ba9447 260 //\r
cc16a929 261 // If the disable-bit is clear, overwrite the default zero vector\r
262 // with the value in Arg0 (ie. PIRQRC[A:D]). Reserved bits are read\r
263 // as 0.\r
49ba9447 264 //\r
cc16a929 265 If (LNot (And (Arg0, 0x80))) {\r
266 Store (Arg0, IRQW)\r
267 }\r
268 Return (BUF0)\r
49ba9447 269 }\r
270\r
271 //\r
272 // _PRS resource for LNKA, LNKB, LNKC, LNKD\r
273 //\r
274 Name (PPRS, ResourceTemplate () {\r
56daf8b9 275 Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) {\r
cc16a929 276 3, 4, 5, 7, 9, 10, 11, 12, 14, 15\r
277 }\r
49ba9447 278 })\r
279\r
49ba9447 280 //\r
281 // PCI IRQ Link A\r
282 //\r
283 Device (LNKA) {\r
284 Name (_HID, EISAID("PNP0C0F"))\r
285 Name (_UID, 1)\r
286\r
287 Method (_STA, 0, NotSerialized) { Return (PSTA (PIRA)) }\r
a42bdfcc 288 Method (_DIS, 0, NotSerialized) {\r
289 Or (PIRA, 0x80, PIRA) // set disable-bit\r
290 }\r
49ba9447 291 Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRA)) }\r
292 Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r
a42bdfcc 293 Method (_SRS, 1, NotSerialized) {\r
294 CreateDWordField (Arg0, 0x05, IRQW)\r
295 Store (IRQW, PIRA)\r
296 }\r
49ba9447 297 }\r
298\r
299 //\r
300 // PCI IRQ Link B\r
301 //\r
302 Device (LNKB) {\r
303 Name (_HID, EISAID("PNP0C0F"))\r
304 Name (_UID, 2)\r
305\r
306 Method (_STA, 0, NotSerialized) { Return (PSTA (PIRB)) }\r
a42bdfcc 307 Method (_DIS, 0, NotSerialized) {\r
308 Or (PIRB, 0x80, PIRB) // set disable-bit\r
309 }\r
49ba9447 310 Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRB)) }\r
311 Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r
a42bdfcc 312 Method (_SRS, 1, NotSerialized) {\r
313 CreateDWordField (Arg0, 0x05, IRQW)\r
314 Store (IRQW, PIRB)\r
315 }\r
49ba9447 316 }\r
317\r
318 //\r
319 // PCI IRQ Link C\r
320 //\r
321 Device (LNKC) {\r
322 Name (_HID, EISAID("PNP0C0F"))\r
323 Name (_UID, 3)\r
324\r
325 Method (_STA, 0, NotSerialized) { Return (PSTA (PIRC)) }\r
a42bdfcc 326 Method (_DIS, 0, NotSerialized) {\r
327 Or (PIRC, 0x80, PIRC) // set disable-bit\r
328 }\r
49ba9447 329 Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRC)) }\r
330 Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r
a42bdfcc 331 Method (_SRS, 1, NotSerialized) {\r
332 CreateDWordField (Arg0, 0x05, IRQW)\r
333 Store (IRQW, PIRC)\r
334 }\r
49ba9447 335 }\r
336\r
337 //\r
338 // PCI IRQ Link D\r
339 //\r
340 Device (LNKD) {\r
341 Name (_HID, EISAID("PNP0C0F"))\r
342 Name (_UID, 1)\r
343\r
344 Method (_STA, 0, NotSerialized) { Return (PSTA (PIRD)) }\r
a42bdfcc 345 Method (_DIS, 0, NotSerialized) {\r
346 Or (PIRD, 0x80, PIRD) // set disable-bit\r
347 }\r
49ba9447 348 Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRD)) }\r
349 Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r
a42bdfcc 350 Method (_SRS, 1, NotSerialized) {\r
351 CreateDWordField (Arg0, 0x05, IRQW)\r
352 Store (IRQW, PIRD)\r
353 }\r
49ba9447 354 }\r
0228e598 355\r
49ba9447 356 //\r
357 // Programmable Interrupt Controller (PIC)\r
358 //\r
359 Device(PIC) {\r
360 Name (_HID, EISAID ("PNP0000"))\r
361 Name (_CRS, ResourceTemplate () {\r
362 IO (Decode16, 0x020, 0x020, 0x00, 0x02)\r
363 IO (Decode16, 0x0A0, 0x0A0, 0x00, 0x02)\r
364 IO (Decode16, 0x4D0, 0x4D0, 0x00, 0x02)\r
365 IRQNoFlags () {2}\r
366 })\r
367 }\r
368\r
369 //\r
0228e598 370 // ISA DMA\r
49ba9447 371 //\r
372 Device (DMAC) {\r
0228e598 373 Name (_HID, EISAID ("PNP0200"))\r
49ba9447 374 Name (_CRS, ResourceTemplate () {\r
375 IO (Decode16, 0x00, 0x00, 0, 0x10)\r
376 IO (Decode16, 0x81, 0x81, 0, 0x03)\r
377 IO (Decode16, 0x87, 0x87, 0, 0x01)\r
378 IO (Decode16, 0x89, 0x89, 0, 0x03)\r
379 IO (Decode16, 0x8f, 0x8f, 0, 0x01)\r
380 IO (Decode16, 0xc0, 0xc0, 0, 0x20)\r
381 DMA (Compatibility, NotBusMaster, Transfer8) {4}\r
382 })\r
383 }\r
384\r
385 //\r
386 // 8254 Timer\r
387 //\r
388 Device(TMR) {\r
389 Name(_HID,EISAID("PNP0100"))\r
390 Name(_CRS, ResourceTemplate () {\r
391 IO (Decode16, 0x40, 0x40, 0x00, 0x04)\r
392 IRQNoFlags () {0}\r
393 })\r
394 }\r
395\r
396 //\r
397 // Real Time Clock\r
398 //\r
399 Device (RTC) {\r
400 Name (_HID, EISAID ("PNP0B00"))\r
401 Name (_CRS, ResourceTemplate () {\r
402 IO (Decode16, 0x70, 0x70, 0x00, 0x02)\r
403 IRQNoFlags () {8}\r
404 })\r
405 }\r
406\r
407 //\r
408 // PCAT Speaker\r
409 //\r
410 Device(SPKR) {\r
411 Name (_HID, EISAID("PNP0800"))\r
412 Name (_CRS, ResourceTemplate () {\r
413 IO (Decode16, 0x61, 0x61, 0x01, 0x01)\r
414 })\r
415 }\r
416\r
417 //\r
418 // Floating Point Coprocessor\r
419 //\r
420 Device(FPU) {\r
421 Name (_HID, EISAID("PNP0C04"))\r
422 Name (_CRS, ResourceTemplate () {\r
423 IO (Decode16, 0xF0, 0xF0, 0x00, 0x10)\r
424 IRQNoFlags () {13}\r
425 })\r
426 }\r
427\r
428 //\r
429 // Generic motherboard devices and pieces that don't fit anywhere else\r
430 //\r
431 Device(XTRA) {\r
432 Name (_HID, EISAID ("PNP0C02"))\r
433 Name (_UID, 0x01)\r
434 Name (_CRS, ResourceTemplate () {\r
435 IO (Decode16, 0x010, 0x010, 0x00, 0x10)\r
436 IO (Decode16, 0x022, 0x022, 0x00, 0x1E)\r
437 IO (Decode16, 0x044, 0x044, 0x00, 0x1C)\r
438 IO (Decode16, 0x062, 0x062, 0x00, 0x02)\r
439 IO (Decode16, 0x065, 0x065, 0x00, 0x0B)\r
440 IO (Decode16, 0x072, 0x072, 0x00, 0x0E)\r
441 IO (Decode16, 0x080, 0x080, 0x00, 0x01)\r
442 IO (Decode16, 0x084, 0x084, 0x00, 0x03)\r
443 IO (Decode16, 0x088, 0x088, 0x00, 0x01)\r
444 IO (Decode16, 0x08c, 0x08c, 0x00, 0x03)\r
445 IO (Decode16, 0x090, 0x090, 0x00, 0x10)\r
446 IO (Decode16, 0x0A2, 0x0A2, 0x00, 0x1E)\r
447 IO (Decode16, 0x0E0, 0x0E0, 0x00, 0x10)\r
448 IO (Decode16, 0x1E0, 0x1E0, 0x00, 0x10)\r
449 IO (Decode16, 0x160, 0x160, 0x00, 0x10)\r
450 IO (Decode16, 0x278, 0x278, 0x00, 0x08)\r
451 IO (Decode16, 0x370, 0x370, 0x00, 0x02)\r
452 IO (Decode16, 0x378, 0x378, 0x00, 0x08)\r
5e57fb75 453 IO (Decode16, 0x402, 0x402, 0x00, 0x01) // QEMU debug console, should use FixedPcdGet16 (PcdDebugIoPort)\r
49ba9447 454 IO (Decode16, 0x440, 0x440, 0x00, 0x10)\r
455 IO (Decode16, 0x678, 0x678, 0x00, 0x08)\r
456 IO (Decode16, 0x778, 0x778, 0x00, 0x08)\r
6d4f320d 457 IO (Decode16, 0xafe0, 0xafe0, 0x00, 0x04) // QEMU GPE0 BLK\r
458 IO (Decode16, 0xb000, 0xb000, 0x00, 0x40) // PMBLK1\r
459 Memory32Fixed (ReadOnly, 0xFEC00000, 0x1000) // IO APIC\r
460 Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) // LAPIC\r
49ba9447 461 })\r
462 }\r
463\r
464 //\r
465 // PS/2 Keyboard and PC/AT Enhanced Keyboard 101/102\r
466 //\r
0228e598 467 Device (PS2K) {\r
49ba9447 468 Name (_HID, EISAID ("PNP0303"))\r
469 Name (_CID, EISAID ("PNP030B"))\r
470 Name(_CRS,ResourceTemplate() {\r
471 IO (Decode16, 0x60, 0x60, 0x00, 0x01)\r
472 IO (Decode16, 0x64, 0x64, 0x00, 0x01)\r
473 IRQNoFlags () {1}\r
474 })\r
475 }\r
476\r
477 //\r
478 // PS/2 Mouse and Microsoft Mouse\r
479 //\r
480 Device (PS2M) { // PS/2 stype mouse port\r
481 Name (_HID, EISAID ("PNP0F03"))\r
482 Name (_CID, EISAID ("PNP0F13"))\r
483 Name (_CRS, ResourceTemplate() {\r
484 IRQNoFlags () {12}\r
485 })\r
486 }\r
487\r
488 //\r
489 // UART Serial Port - COM1\r
490 //\r
491 Device (UAR1) {\r
492 Name (_HID, EISAID ("PNP0501"))\r
493 Name (_DDN, "COM1")\r
494 Name (_UID, 0x01)\r
495 Name(_CRS,ResourceTemplate() {\r
496 IO (Decode16, 0x3F8, 0x3F8, 0x01, 0x08)\r
497 IRQ (Edge, ActiveHigh, Exclusive, ) {4}\r
498 })\r
499 }\r
500\r
501 //\r
502 // UART Serial Port - COM2\r
503 //\r
504 Device (UAR2) {\r
505 Name (_HID, EISAID ("PNP0501"))\r
506 Name (_DDN, "COM2")\r
507 Name (_UID, 0x02)\r
508 Name(_CRS,ResourceTemplate() {\r
509 IO (Decode16, 0x2F8, 0x2F8, 0x01, 0x08)\r
510 IRQ (Edge, ActiveHigh, Exclusive, ) {3}\r
511 })\r
512 }\r
513\r
514 //\r
515 // Floppy Disk Controller\r
516 //\r
517 Device (FDC) {\r
518 Name (_HID, EISAID ("PNP0700"))\r
519 Name (_CRS,ResourceTemplate() {\r
520 IO (Decode16, 0x3F0, 0x3F0, 0x01, 0x06)\r
521 IO (Decode16, 0x3F7, 0x3F7, 0x01, 0x01)\r
522 IRQNoFlags () {6}\r
523 DMA (Compatibility, NotBusMaster, Transfer8) {2}\r
524 })\r
525 }\r
526 }\r
527 }\r
528 }\r
529}\r
530\r
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