]> git.proxmox.com Git - mirror_edk2.git/blob - OvmfPkg/AcpiTables/Dsdt.asl
projects / mirror_edk2.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
OvmfPkg: _DIS and _SRS methods should have permanent effect
[mirror_edk2.git] / OvmfPkg / AcpiTables / Dsdt.asl
1 /** @file
2 Contains root level name space objects for the platform
3
4 Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are
6 licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 DefinitionBlock ("Dsdt.aml", "DSDT", 1, "INTEL ", "OVMF ", 3) {
16 //
17 // System Sleep States
18 //
19 Name (\_S0, Package () {5, 0, 0, 0})
20 Name (\_S4, Package () {1, 0, 0, 0})
21 Name (\_S5, Package () {0, 0, 0, 0})
22
23 //
24 // System Bus
25 //
26 Scope (\_SB) {
27 //
28 // PCI Root Bridge
29 //
30 Device (PCI0) {
31 Name (_HID, EISAID ("PNP0A03"))
32 Name (_ADR, 0x00000000)
33 Name (_BBN, 0x00)
34 Name (_UID, 0x00)
35
36 //
37 // BUS, I/O, and MMIO resources
38 //
39 Name (CRES, ResourceTemplate () {
40 WORDBusNumber ( // Bus number resource (0); the bridge produces bus numbers for its subsequent buses
41 ResourceProducer, // bit 0 of general flags is 1
42 MinFixed, // Range is fixed
43 MaxFixed, // Range is fixed
44 PosDecode, // PosDecode
45 0x0000, // Granularity
46 0x0000, // Min
47 0x00FF, // Max
48 0x0000, // Translation
49 0x0100 // Range Length = Max-Min+1
50 )
51
52 IO (Decode16, 0xCF8, 0xCF8, 0x01, 0x08) //Consumed resource (0xCF8-0xCFF)
53
54 WORDIO ( // Consumed-and-produced resource (all I/O below CF8)
55 ResourceProducer, // bit 0 of general flags is 0
56 MinFixed, // Range is fixed
57 MaxFixed, // Range is fixed
58 PosDecode,
59 EntireRange,
60 0x0000, // Granularity
61 0x0000, // Min
62 0x0CF7, // Max
63 0x0000, // Translation
64 0x0CF8 // Range Length
65 )
66
67 WORDIO ( // Consumed-and-produced resource (all I/O above CFF)
68 ResourceProducer, // bit 0 of general flags is 0
69 MinFixed, // Range is fixed
70 MaxFixed, // Range is fixed
71 PosDecode,
72 EntireRange,
73 0x0000, // Granularity
74 0x0D00, // Min
75 0xFFFF, // Max
76 0x0000, // Translation
77 0xF300 // Range Length
78 )
79
80 DWORDMEMORY ( // Descriptor for legacy VGA video RAM
81 ResourceProducer, // bit 0 of general flags is 0
82 PosDecode,
83 MinFixed, // Range is fixed
84 MaxFixed, // Range is Fixed
85 Cacheable,
86 ReadWrite,
87 0x00000000, // Granularity
88 0x000A0000, // Min
89 0x000BFFFF, // Max
90 0x00000000, // Translation
91 0x00020000 // Range Length
92 )
93
94 DWORDMEMORY ( // Descriptor for 32-bit MMIO
95 ResourceProducer, // bit 0 of general flags is 0
96 PosDecode,
97 MinFixed, // Range is fixed
98 MaxFixed, // Range is Fixed
99 NonCacheable,
100 ReadWrite,
101 0x00000000, // Granularity
102 0xF8000000, // Min
103 0xFFFBFFFF, // Max
104 0x00000000, // Translation
105 0x07FC0000, // Range Length
106 , // ResourceSourceIndex
107 , // ResourceSource
108 PW32 // DescriptorName
109 )
110 })
111
112 Name (CR64, ResourceTemplate () {
113 QWordMemory ( // Descriptor for 64-bit MMIO
114 ResourceProducer, // bit 0 of general flags is 0
115 PosDecode,
116 MinFixed, // Range is fixed
117 MaxFixed, // Range is Fixed
118 Cacheable,
119 ReadWrite,
120 0x00000000, // Granularity
121 0x8000000000, // Min
122 0xFFFFFFFFFF, // Max
123 0x00000000, // Translation
124 0x8000000000, // Range Length
125 , // ResourceSourceIndex
126 , // ResourceSource
127 PW64 // DescriptorName
128 )
129 })
130
131 Method (_CRS, 0) {
132 //
133 // see the FIRMWARE_DATA structure in "OvmfPkg/AcpiPlatformDxe/Qemu.c"
134 //
135 External (FWDT, OpRegionObj)
136 Field(FWDT, QWordAcc, NoLock, Preserve) {
137 P0S, 64, // PciWindow32.Base
138 P0E, 64, // PciWindow32.End
139 P0L, 64, // PciWindow32.Length
140 P1S, 64, // PciWindow64.Base
141 P1E, 64, // PciWindow64.End
142 P1L, 64 // PciWindow64.Length
143 }
144 Field(FWDT, DWordAcc, NoLock, Preserve) {
145 P0SL, 32, // PciWindow32.Base, low 32 bits
146 P0SH, 32, // PciWindow32.Base, high 32 bits
147 P0EL, 32, // PciWindow32.End, low 32 bits
148 P0EH, 32, // PciWindow32.End, high 32 bits
149 P0LL, 32, // PciWindow32.Length, low 32 bits
150 P0LH, 32, // PciWindow32.Length, high 32 bits
151 P1SL, 32, // PciWindow64.Base, low 32 bits
152 P1SH, 32, // PciWindow64.Base, high 32 bits
153 P1EL, 32, // PciWindow64.End, low 32 bits
154 P1EH, 32, // PciWindow64.End, high 32 bits
155 P1LL, 32, // PciWindow64.Length, low 32 bits
156 P1LH, 32 // PciWindow64.Length, high 32 bits
157 }
158
159 //
160 // fixup 32-bit PCI IO window
161 //
162 CreateDWordField (CRES, \_SB.PCI0.PW32._MIN, PS32)
163 CreateDWordField (CRES, \_SB.PCI0.PW32._MAX, PE32)
164 CreateDWordField (CRES, \_SB.PCI0.PW32._LEN, PL32)
165 Store (P0SL, PS32)
166 Store (P0EL, PE32)
167 Store (P0LL, PL32)
168
169 If (LAnd (LEqual (P1SL, 0x00), LEqual (P1SH, 0x00))) {
170 Return (CRES)
171 } Else {
172 //
173 // fixup 64-bit PCI IO window
174 //
175 CreateQWordField (CR64, \_SB.PCI0.PW64._MIN, PS64)
176 CreateQWordField (CR64, \_SB.PCI0.PW64._MAX, PE64)
177 CreateQWordField (CR64, \_SB.PCI0.PW64._LEN, PL64)
178 Store (P1S, PS64)
179 Store (P1E, PE64)
180 Store (P1L, PL64)
181
182 //
183 // add window and return result
184 //
185 ConcatenateResTemplate (CRES, CR64, Local0)
186 Return (Local0)
187 }
188 }
189
190 //
191 // PCI Interrupt Routing Table - PIC Mode Only
192 //
193 Method (_PRT, 0, NotSerialized) {
194 Return (
195 Package () {
196 //
197 // Bus 0, Device 1
198 //
199 Package () {0x0001FFFF, 0x00, \_SB.PCI0.LPC.LNKA, 0x00},
200 Package () {0x0001FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},
201 Package () {0x0001FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},
202 Package () {0x0001FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},
203 //
204 // Bus 0, Device 3
205 //
206 Package () {0x0003FFFF, 0x00, \_SB.PCI0.LPC.LNKA, 0x00},
207 Package () {0x0003FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},
208 Package () {0x0003FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},
209 Package () {0x0003FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},
210 }
211 )
212 }
213
214 //
215 // PCI to ISA Bridge (Bus 0, Device 1, Function 0)
216 //
217 Device (LPC) {
218 Name (_ADR, 0x00010000)
219
220 //
221 // PCI Interrupt Routing Configuration Registers
222 //
223 OperationRegion (PRR0, PCI_Config, 0x60, 0x04)
224 Field (PRR0, ANYACC, NOLOCK, PRESERVE) {
225 PIRA, 8,
226 PIRB, 8,
227 PIRC, 8,
228 PIRD, 8
229 }
230
231 //
232 // _STA method for LNKA, LNKB, LNKC, LNKD
233 //
234 Method (PSTA, 1, NotSerialized) {
235 If (And (Arg0, 0x80)) {
236 Return (0x9)
237 } Else {
238 Return (0xB)
239 }
240 }
241
242 //
243 // _CRS method for LNKA, LNKB, LNKC, LNKD
244 //
245 Method (PCRS, 1, NotSerialized) {
246 //
247 // create temporary buffer with an Extended Interrupt Descriptor
248 // whose single vector defaults to zero
249 //
250 Name (BUF0, ResourceTemplate () {
251 Interrupt (ResourceConsumer, Level, ActiveHigh, Shared){0}
252 }
253 )
254
255 //
256 // define reference to first interrupt vector in buffer
257 //
258 CreateDWordField (BUF0, 0x05, IRQW)
259
260 //
261 // If the disable-bit is clear, overwrite the default zero vector
262 // with the value in Arg0 (ie. PIRQRC[A:D]). Reserved bits are read
263 // as 0.
264 //
265 If (LNot (And (Arg0, 0x80))) {
266 Store (Arg0, IRQW)
267 }
268 Return (BUF0)
269 }
270
271 //
272 // _PRS resource for LNKA, LNKB, LNKC, LNKD
273 //
274 Name (PPRS, ResourceTemplate () {
275 Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) {
276 3, 4, 5, 7, 9, 10, 11, 12, 14, 15
277 }
278 })
279
280 //
281 // PCI IRQ Link A
282 //
283 Device (LNKA) {
284 Name (_HID, EISAID("PNP0C0F"))
285 Name (_UID, 1)
286
287 Method (_STA, 0, NotSerialized) { Return (PSTA (PIRA)) }
288 Method (_DIS, 0, NotSerialized) {
289 Or (PIRA, 0x80, PIRA) // set disable-bit
290 }
291 Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRA)) }
292 Method (_PRS, 0, NotSerialized) { Return (PPRS) }
293 Method (_SRS, 1, NotSerialized) {
294 CreateDWordField (Arg0, 0x05, IRQW)
295 Store (IRQW, PIRA)
296 }
297 }
298
299 //
300 // PCI IRQ Link B
301 //
302 Device (LNKB) {
303 Name (_HID, EISAID("PNP0C0F"))
304 Name (_UID, 2)
305
306 Method (_STA, 0, NotSerialized) { Return (PSTA (PIRB)) }
307 Method (_DIS, 0, NotSerialized) {
308 Or (PIRB, 0x80, PIRB) // set disable-bit
309 }
310 Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRB)) }
311 Method (_PRS, 0, NotSerialized) { Return (PPRS) }
312 Method (_SRS, 1, NotSerialized) {
313 CreateDWordField (Arg0, 0x05, IRQW)
314 Store (IRQW, PIRB)
315 }
316 }
317
318 //
319 // PCI IRQ Link C
320 //
321 Device (LNKC) {
322 Name (_HID, EISAID("PNP0C0F"))
323 Name (_UID, 3)
324
325 Method (_STA, 0, NotSerialized) { Return (PSTA (PIRC)) }
326 Method (_DIS, 0, NotSerialized) {
327 Or (PIRC, 0x80, PIRC) // set disable-bit
328 }
329 Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRC)) }
330 Method (_PRS, 0, NotSerialized) { Return (PPRS) }
331 Method (_SRS, 1, NotSerialized) {
332 CreateDWordField (Arg0, 0x05, IRQW)
333 Store (IRQW, PIRC)
334 }
335 }
336
337 //
338 // PCI IRQ Link D
339 //
340 Device (LNKD) {
341 Name (_HID, EISAID("PNP0C0F"))
342 Name (_UID, 1)
343
344 Method (_STA, 0, NotSerialized) { Return (PSTA (PIRD)) }
345 Method (_DIS, 0, NotSerialized) {
346 Or (PIRD, 0x80, PIRD) // set disable-bit
347 }
348 Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRD)) }
349 Method (_PRS, 0, NotSerialized) { Return (PPRS) }
350 Method (_SRS, 1, NotSerialized) {
351 CreateDWordField (Arg0, 0x05, IRQW)
352 Store (IRQW, PIRD)
353 }
354 }
355
356 //
357 // Programmable Interrupt Controller (PIC)
358 //
359 Device(PIC) {
360 Name (_HID, EISAID ("PNP0000"))
361 Name (_CRS, ResourceTemplate () {
362 IO (Decode16, 0x020, 0x020, 0x00, 0x02)
363 IO (Decode16, 0x0A0, 0x0A0, 0x00, 0x02)
364 IO (Decode16, 0x4D0, 0x4D0, 0x00, 0x02)
365 IRQNoFlags () {2}
366 })
367 }
368
369 //
370 // ISA DMA
371 //
372 Device (DMAC) {
373 Name (_HID, EISAID ("PNP0200"))
374 Name (_CRS, ResourceTemplate () {
375 IO (Decode16, 0x00, 0x00, 0, 0x10)
376 IO (Decode16, 0x81, 0x81, 0, 0x03)
377 IO (Decode16, 0x87, 0x87, 0, 0x01)
378 IO (Decode16, 0x89, 0x89, 0, 0x03)
379 IO (Decode16, 0x8f, 0x8f, 0, 0x01)
380 IO (Decode16, 0xc0, 0xc0, 0, 0x20)
381 DMA (Compatibility, NotBusMaster, Transfer8) {4}
382 })
383 }
384
385 //
386 // 8254 Timer
387 //
388 Device(TMR) {
389 Name(_HID,EISAID("PNP0100"))
390 Name(_CRS, ResourceTemplate () {
391 IO (Decode16, 0x40, 0x40, 0x00, 0x04)
392 IRQNoFlags () {0}
393 })
394 }
395
396 //
397 // Real Time Clock
398 //
399 Device (RTC) {
400 Name (_HID, EISAID ("PNP0B00"))
401 Name (_CRS, ResourceTemplate () {
402 IO (Decode16, 0x70, 0x70, 0x00, 0x02)
403 IRQNoFlags () {8}
404 })
405 }
406
407 //
408 // PCAT Speaker
409 //
410 Device(SPKR) {
411 Name (_HID, EISAID("PNP0800"))
412 Name (_CRS, ResourceTemplate () {
413 IO (Decode16, 0x61, 0x61, 0x01, 0x01)
414 })
415 }
416
417 //
418 // Floating Point Coprocessor
419 //
420 Device(FPU) {
421 Name (_HID, EISAID("PNP0C04"))
422 Name (_CRS, ResourceTemplate () {
423 IO (Decode16, 0xF0, 0xF0, 0x00, 0x10)
424 IRQNoFlags () {13}
425 })
426 }
427
428 //
429 // Generic motherboard devices and pieces that don't fit anywhere else
430 //
431 Device(XTRA) {
432 Name (_HID, EISAID ("PNP0C02"))
433 Name (_UID, 0x01)
434 Name (_CRS, ResourceTemplate () {
435 IO (Decode16, 0x010, 0x010, 0x00, 0x10)
436 IO (Decode16, 0x022, 0x022, 0x00, 0x1E)
437 IO (Decode16, 0x044, 0x044, 0x00, 0x1C)
438 IO (Decode16, 0x062, 0x062, 0x00, 0x02)
439 IO (Decode16, 0x065, 0x065, 0x00, 0x0B)
440 IO (Decode16, 0x072, 0x072, 0x00, 0x0E)
441 IO (Decode16, 0x080, 0x080, 0x00, 0x01)
442 IO (Decode16, 0x084, 0x084, 0x00, 0x03)
443 IO (Decode16, 0x088, 0x088, 0x00, 0x01)
444 IO (Decode16, 0x08c, 0x08c, 0x00, 0x03)
445 IO (Decode16, 0x090, 0x090, 0x00, 0x10)
446 IO (Decode16, 0x0A2, 0x0A2, 0x00, 0x1E)
447 IO (Decode16, 0x0E0, 0x0E0, 0x00, 0x10)
448 IO (Decode16, 0x1E0, 0x1E0, 0x00, 0x10)
449 IO (Decode16, 0x160, 0x160, 0x00, 0x10)
450 IO (Decode16, 0x278, 0x278, 0x00, 0x08)
451 IO (Decode16, 0x370, 0x370, 0x00, 0x02)
452 IO (Decode16, 0x378, 0x378, 0x00, 0x08)
453 IO (Decode16, 0x402, 0x402, 0x00, 0x01) // QEMU debug console, should use FixedPcdGet16 (PcdDebugIoPort)
454 IO (Decode16, 0x440, 0x440, 0x00, 0x10)
455 IO (Decode16, 0x678, 0x678, 0x00, 0x08)
456 IO (Decode16, 0x778, 0x778, 0x00, 0x08)
457 IO (Decode16, 0xafe0, 0xafe0, 0x00, 0x04) // QEMU GPE0 BLK
458 IO (Decode16, 0xb000, 0xb000, 0x00, 0x40) // PMBLK1
459 Memory32Fixed (ReadOnly, 0xFEC00000, 0x1000) // IO APIC
460 Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) // LAPIC
461 })
462 }
463
464 //
465 // PS/2 Keyboard and PC/AT Enhanced Keyboard 101/102
466 //
467 Device (PS2K) {
468 Name (_HID, EISAID ("PNP0303"))
469 Name (_CID, EISAID ("PNP030B"))
470 Name(_CRS,ResourceTemplate() {
471 IO (Decode16, 0x60, 0x60, 0x00, 0x01)
472 IO (Decode16, 0x64, 0x64, 0x00, 0x01)
473 IRQNoFlags () {1}
474 })
475 }
476
477 //
478 // PS/2 Mouse and Microsoft Mouse
479 //
480 Device (PS2M) { // PS/2 stype mouse port
481 Name (_HID, EISAID ("PNP0F03"))
482 Name (_CID, EISAID ("PNP0F13"))
483 Name (_CRS, ResourceTemplate() {
484 IRQNoFlags () {12}
485 })
486 }
487
488 //
489 // UART Serial Port - COM1
490 //
491 Device (UAR1) {
492 Name (_HID, EISAID ("PNP0501"))
493 Name (_DDN, "COM1")
494 Name (_UID, 0x01)
495 Name(_CRS,ResourceTemplate() {
496 IO (Decode16, 0x3F8, 0x3F8, 0x01, 0x08)
497 IRQ (Edge, ActiveHigh, Exclusive, ) {4}
498 })
499 }
500
501 //
502 // UART Serial Port - COM2
503 //
504 Device (UAR2) {
505 Name (_HID, EISAID ("PNP0501"))
506 Name (_DDN, "COM2")
507 Name (_UID, 0x02)
508 Name(_CRS,ResourceTemplate() {
509 IO (Decode16, 0x2F8, 0x2F8, 0x01, 0x08)
510 IRQ (Edge, ActiveHigh, Exclusive, ) {3}
511 })
512 }
513
514 //
515 // Floppy Disk Controller
516 //
517 Device (FDC) {
518 Name (_HID, EISAID ("PNP0700"))
519 Name (_CRS,ResourceTemplate() {
520 IO (Decode16, 0x3F0, 0x3F0, 0x01, 0x06)
521 IO (Decode16, 0x3F7, 0x3F7, 0x01, 0x01)
522 IRQNoFlags () {6}
523 DMA (Compatibility, NotBusMaster, Transfer8) {2}
524 })
525 }
526 }
527 }
528 }
529 }
530
EFI Development Kit II mirror for PVE