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[mirror_edk2.git] / OvmfPkg / AmdSevDxe / AmdSevDxe.c

/** @file\r
\r
  AMD Sev Dxe driver. This driver is dispatched early in DXE, due to being list\r
  in APRIORI. It clears C-bit from MMIO and NonExistent Memory space when SEV\r
  is enabled.\r
\r
  Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <IndustryStandard/Q35MchIch9.h>\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/DxeServicesTableLib.h>\r
#include <Library/MemEncryptSevLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Guid/ConfidentialComputingSevSnpBlob.h>\r
#include <Library/PcdLib.h>\r
#include <Pi/PrePiDxeCis.h>\r
#include <Protocol/SevMemoryAcceptance.h>\r
#include <Protocol/MemoryAccept.h>\r
\r
STATIC CONFIDENTIAL_COMPUTING_SNP_BLOB_LOCATION  mSnpBootDxeTable = {\r
  SIGNATURE_32 ('A',                                    'M', 'D', 'E'),\r
  1,\r
  0,\r
  (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfSnpSecretsBase),\r
  FixedPcdGet32 (PcdOvmfSnpSecretsSize),\r
  (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfCpuidBase),\r
  FixedPcdGet32 (PcdOvmfCpuidSize),\r
};\r
\r
STATIC EFI_HANDLE  mAmdSevDxeHandle = NULL;\r
\r
STATIC BOOLEAN  mAcceptAllMemoryAtEBS = TRUE;\r
\r
STATIC EFI_EVENT  mAcceptAllMemoryEvent = NULL;\r
\r
#define IS_ALIGNED(x, y)  ((((x) & ((y) - 1)) == 0))\r
\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
AmdSevMemoryAccept (\r
  IN EDKII_MEMORY_ACCEPT_PROTOCOL  *This,\r
  IN EFI_PHYSICAL_ADDRESS          StartAddress,\r
  IN UINTN                         Size\r
  )\r
{\r
  //\r
  // The StartAddress must be page-aligned, and the Size must be a positive\r
  // multiple of SIZE_4KB. Use an assert instead of returning an erros since\r
  // this is an EDK2-internal protocol.\r
  //\r
  ASSERT (IS_ALIGNED (StartAddress, SIZE_4KB));\r
  ASSERT (IS_ALIGNED (Size, SIZE_4KB));\r
  ASSERT (Size != 0);\r
\r
  MemEncryptSevSnpPreValidateSystemRam (\r
    StartAddress,\r
    EFI_SIZE_TO_PAGES (Size)\r
    );\r
\r
  return EFI_SUCCESS;\r
}\r
\r
STATIC\r
EFI_STATUS\r
AcceptAllMemory (\r
  VOID\r
  )\r
{\r
  EFI_GCD_MEMORY_SPACE_DESCRIPTOR  *AllDescMap;\r
  UINTN                            NumEntries;\r
  UINTN                            Index;\r
  EFI_STATUS                       Status;\r
\r
  DEBUG ((DEBUG_INFO, "Accepting all memory\n"));\r
\r
  /*\r
   * Get a copy of the memory space map to iterate over while\r
   * changing the map.\r
   */\r
  Status = gDS->GetMemorySpaceMap (&NumEntries, &AllDescMap);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  for (Index = 0; Index < NumEntries; Index++) {\r
    CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR  *Desc;\r
\r
    Desc = &AllDescMap[Index];\r
    if (Desc->GcdMemoryType != EFI_GCD_MEMORY_TYPE_UNACCEPTED) {\r
      continue;\r
    }\r
\r
    Status = AmdSevMemoryAccept (\r
               NULL,\r
               Desc->BaseAddress,\r
               Desc->Length\r
               );\r
    if (EFI_ERROR (Status)) {\r
      break;\r
    }\r
\r
    Status = gDS->RemoveMemorySpace (Desc->BaseAddress, Desc->Length);\r
    if (EFI_ERROR (Status)) {\r
      break;\r
    }\r
\r
    Status = gDS->AddMemorySpace (\r
                    EfiGcdMemoryTypeSystemMemory,\r
                    Desc->BaseAddress,\r
                    Desc->Length,\r
                    EFI_MEMORY_CPU_CRYPTO | EFI_MEMORY_XP | EFI_MEMORY_RO | EFI_MEMORY_RP\r
                    );\r
    if (EFI_ERROR (Status)) {\r
      break;\r
    }\r
  }\r
\r
  gBS->FreePool (AllDescMap);\r
  return Status;\r
}\r
\r
VOID\r
EFIAPI\r
ResolveUnacceptedMemory (\r
  IN EFI_EVENT  Event,\r
  IN VOID       *Context\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  if (!mAcceptAllMemoryAtEBS) {\r
    return;\r
  }\r
\r
  Status = AcceptAllMemory ();\r
  ASSERT_EFI_ERROR (Status);\r
}\r
\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
AllowUnacceptedMemory (\r
  IN  OVMF_SEV_MEMORY_ACCEPTANCE_PROTOCOL  *This\r
  )\r
{\r
  mAcceptAllMemoryAtEBS = FALSE;\r
  return EFI_SUCCESS;\r
}\r
\r
STATIC\r
OVMF_SEV_MEMORY_ACCEPTANCE_PROTOCOL\r
  mMemoryAcceptanceProtocol = { AllowUnacceptedMemory };\r
\r
STATIC EDKII_MEMORY_ACCEPT_PROTOCOL  mMemoryAcceptProtocol = {\r
  AmdSevMemoryAccept\r
};\r
\r
EFI_STATUS\r
EFIAPI\r
AmdSevDxeEntryPoint (\r
  IN EFI_HANDLE        ImageHandle,\r
  IN EFI_SYSTEM_TABLE  *SystemTable\r
  )\r
{\r
  EFI_STATUS                       Status;\r
  EFI_GCD_MEMORY_SPACE_DESCRIPTOR  *AllDescMap;\r
  UINTN                            NumEntries;\r
  UINTN                            Index;\r
\r
  //\r
  // Do nothing when SEV is not enabled\r
  //\r
  if (!MemEncryptSevIsEnabled ()) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  //\r
  // Iterate through the GCD map and clear the C-bit from MMIO and NonExistent\r
  // memory space. The NonExistent memory space will be used for mapping the\r
  // MMIO space added later (eg PciRootBridge). By clearing both known MMIO and\r
  // NonExistent memory space can gurantee that current and furture MMIO adds\r
  // will have C-bit cleared.\r
  //\r
  Status = gDS->GetMemorySpaceMap (&NumEntries, &AllDescMap);\r
  if (!EFI_ERROR (Status)) {\r
    for (Index = 0; Index < NumEntries; Index++) {\r
      CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR  *Desc;\r
\r
      Desc = &AllDescMap[Index];\r
      if ((Desc->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) ||\r
          (Desc->GcdMemoryType == EfiGcdMemoryTypeNonExistent))\r
      {\r
        Status = MemEncryptSevClearMmioPageEncMask (\r
                   0,\r
                   Desc->BaseAddress,\r
                   EFI_SIZE_TO_PAGES (Desc->Length)\r
                   );\r
        ASSERT_EFI_ERROR (Status);\r
      }\r
    }\r
\r
    FreePool (AllDescMap);\r
  }\r
\r
  //\r
  // If PCI Express is enabled, the MMCONFIG area has been reserved, rather\r
  // than marked as MMIO, and so the C-bit won't be cleared by the above walk\r
  // through the GCD map. Check for the MMCONFIG area and clear the C-bit for\r
  // the range.\r
  //\r
  if (PcdGet16 (PcdOvmfHostBridgePciDevId) == INTEL_Q35_MCH_DEVICE_ID) {\r
    Status = MemEncryptSevClearMmioPageEncMask (\r
               0,\r
               FixedPcdGet64 (PcdPciExpressBaseAddress),\r
               EFI_SIZE_TO_PAGES (SIZE_256MB)\r
               );\r
\r
    ASSERT_EFI_ERROR (Status);\r
  }\r
\r
  //\r
  // When SMM is enabled, clear the C-bit from SMM Saved State Area\r
  //\r
  // NOTES: The SavedStateArea address cleared here is before SMBASE\r
  // relocation. Currently, we do not clear the SavedStateArea address after\r
  // SMBASE is relocated due to the following reasons:\r
  //\r
  // 1) Guest BIOS never access the relocated SavedStateArea.\r
  //\r
  // 2) The C-bit works on page-aligned address, but the SavedStateArea\r
  // address is not a page-aligned. Theoretically, we could roundup the address\r
  // and clear the C-bit of aligned address but looking carefully we found\r
  // that some portion of the page contains code -- which will causes a bigger\r
  // issues for SEV guest. When SEV is enabled, all the code must be encrypted\r
  // otherwise hardware will cause trap.\r
  //\r
  // We restore the C-bit for this SMM Saved State Area after SMBASE relocation\r
  // is completed (See OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c).\r
  //\r
  if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
    UINTN  MapPagesBase;\r
    UINTN  MapPagesCount;\r
\r
    Status = MemEncryptSevLocateInitialSmramSaveStateMapPages (\r
               &MapPagesBase,\r
               &MapPagesCount\r
               );\r
    ASSERT_EFI_ERROR (Status);\r
\r
    //\r
    // Although these pages were set aside (i.e., allocated) by PlatformPei, we\r
    // could be after a warm reboot from the OS. Don't leak any stale OS data\r
    // to the hypervisor.\r
    //\r
    ZeroMem ((VOID *)MapPagesBase, EFI_PAGES_TO_SIZE (MapPagesCount));\r
\r
    Status = MemEncryptSevClearPageEncMask (\r
               0,             // Cr3BaseAddress -- use current CR3\r
               MapPagesBase,  // BaseAddress\r
               MapPagesCount  // NumPages\r
               );\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((\r
        DEBUG_ERROR,\r
        "%a: MemEncryptSevClearPageEncMask(): %r\n",\r
        __FUNCTION__,\r
        Status\r
        ));\r
      ASSERT (FALSE);\r
      CpuDeadLoop ();\r
    }\r
  }\r
\r
  if (MemEncryptSevSnpIsEnabled ()) {\r
    //\r
    // Memory acceptance began being required in SEV-SNP, so install the\r
    // memory accept protocol implementation for a SEV-SNP active guest.\r
    //\r
    Status = gBS->InstallMultipleProtocolInterfaces (\r
                    &mAmdSevDxeHandle,\r
                    &gEdkiiMemoryAcceptProtocolGuid,\r
                    &mMemoryAcceptProtocol,\r
                    &gOvmfSevMemoryAcceptanceProtocolGuid,\r
                    &mMemoryAcceptanceProtocol,\r
                    NULL\r
                    );\r
    ASSERT_EFI_ERROR (Status);\r
\r
    // SEV-SNP support does not automatically imply unaccepted memory support,\r
    // so make ExitBootServices accept all unaccepted memory if support is\r
    // not communicated.\r
    Status = gBS->CreateEventEx (\r
                    EVT_NOTIFY_SIGNAL,\r
                    TPL_CALLBACK,\r
                    ResolveUnacceptedMemory,\r
                    NULL,\r
                    &gEfiEventBeforeExitBootServicesGuid,\r
                    &mAcceptAllMemoryEvent\r
                    );\r
\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((DEBUG_ERROR, "AllowUnacceptedMemory event creation for EventBeforeExitBootServices failed.\n"));\r
    }\r
\r
    //\r
    // If its SEV-SNP active guest then install the CONFIDENTIAL_COMPUTING_SEV_SNP_BLOB.\r
    // It contains the location for both the Secrets and CPUID page.\r
    //\r
    return gBS->InstallConfigurationTable (\r
                  &gConfidentialComputingSevSnpBlobGuid,\r
                  &mSnpBootDxeTable\r
                  );\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r