[mirror_edk2.git] / OvmfPkg / Include / IndustryStandard / PageTable.h

/** @file\r
\r
  x86_64 Page Tables structures\r
\r
  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
  Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
  Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h\r
\r
**/\r
\r
#ifndef PAGE_TABLE_H_\r
#define PAGE_TABLE_H_\r
\r
#include <Base.h>\r
\r
#pragma pack(1)\r
\r
//\r
// Page-Map Level-4 Offset (PML4) and\r
// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
//\r
\r
typedef union {\r
  struct {\r
    UINT64    Present              : 1;  // 0 = Not present in memory,\r
                                         //   1 = Present in memory\r
    UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write\r
    UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User\r
    UINT64    WriteThrough         : 1;  // 0 = Write-Back caching,\r
                                         //   1 = Write-Through caching\r
    UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached\r
    UINT64    Accessed             : 1;  // 0 = Not accessed,\r
                                         //   1 = Accessed (set by CPU)\r
    UINT64    Reserved             : 1;  // Reserved\r
    UINT64    MustBeZero           : 2;  // Must Be Zero\r
    UINT64    Available            : 3;  // Available for use by system software\r
    UINT64    PageTableBaseAddress : 40; // Page Table Base Address\r
    UINT64    AvabilableHigh       : 11; // Available for use by system software\r
    UINT64    Nx                   : 1;  // No Execute bit\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_MAP_AND_DIRECTORY_POINTER;\r
\r
//\r
// Page Table Entry 4KB\r
//\r
typedef union {\r
  struct {\r
    UINT64    Present              : 1;  // 0 = Not present in memory,\r
                                         //   1 = Present in memory\r
    UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write\r
    UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User\r
    UINT64    WriteThrough         : 1;  // 0 = Write-Back caching,\r
                                         //   1 = Write-Through caching\r
    UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached\r
    UINT64    Accessed             : 1;  // 0 = Not accessed,\r
                                         //   1 = Accessed (set by CPU)\r
    UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by\r
                                         //   processor on access to page\r
    UINT64    PAT                  : 1;  //\r
    UINT64    Global               : 1;  // 0 = Not global page, 1 = global page\r
                                         //   TLB not cleared on CR3 write\r
    UINT64    Available            : 3;  // Available for use by system software\r
    UINT64    PageTableBaseAddress : 40; // Page Table Base Address\r
    UINT64    AvabilableHigh       : 11; // Available for use by system software\r
    UINT64    Nx                   : 1;  // 0 = Execute Code,\r
                                         //   1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_4K_ENTRY;\r
\r
//\r
// Page Table Entry 2MB\r
//\r
typedef union {\r
  struct {\r
    UINT64    Present              : 1;  // 0 = Not present in memory,\r
                                         //   1 = Present in memory\r
    UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write\r
    UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User\r
    UINT64    WriteThrough         : 1;  // 0 = Write-Back caching,\r
                                         //   1=Write-Through caching\r
    UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached\r
    UINT64    Accessed             : 1;  // 0 = Not accessed,\r
                                         //   1 = Accessed (set by CPU)\r
    UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by\r
                                         //   processor on access to page\r
    UINT64    MustBe1              : 1;  // Must be 1\r
    UINT64    Global               : 1;  // 0 = Not global page, 1 = global page\r
                                         //   TLB not cleared on CR3 write\r
    UINT64    Available            : 3;  // Available for use by system software\r
    UINT64    PAT                  : 1;  //\r
    UINT64    MustBeZero           : 8;  // Must be zero;\r
    UINT64    PageTableBaseAddress : 31; // Page Table Base Address\r
    UINT64    AvabilableHigh       : 11; // Available for use by system software\r
    UINT64    Nx                   : 1;  // 0 = Execute Code,\r
                                         //   1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_ENTRY;\r
\r
//\r
// Page Table Entry 1GB\r
//\r
typedef union {\r
  struct {\r
    UINT64    Present              : 1;  // 0 = Not present in memory,\r
                                         //   1 = Present in memory\r
    UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write\r
    UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User\r
    UINT64    WriteThrough         : 1;  // 0 = Write-Back caching,\r
                                         //   1 = Write-Through caching\r
    UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached\r
    UINT64    Accessed             : 1;  // 0 = Not accessed,\r
                                         //   1 = Accessed (set by CPU)\r
    UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by\r
                                         //   processor on access to page\r
    UINT64    MustBe1              : 1;  // Must be 1\r
    UINT64    Global               : 1;  // 0 = Not global page, 1 = global page\r
                                         //   TLB not cleared on CR3 write\r
    UINT64    Available            : 3;  // Available for use by system software\r
    UINT64    PAT                  : 1;  //\r
    UINT64    MustBeZero           : 17; // Must be zero;\r
    UINT64    PageTableBaseAddress : 22; // Page Table Base Address\r
    UINT64    AvabilableHigh       : 11; // Available for use by system software\r
    UINT64    Nx                   : 1;  // 0 = Execute Code,\r
                                         //   1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_1G_ENTRY;\r
\r
#pragma pack()\r
\r
#define IA32_PG_P   BIT0\r
#define IA32_PG_RW  BIT1\r
#define IA32_PG_PS  BIT7\r
\r
#define PAGING_PAE_INDEX_MASK  0x1FF\r
\r
#define PAGING_4K_ADDRESS_MASK_64  0x000FFFFFFFFFF000ull\r
#define PAGING_2M_ADDRESS_MASK_64  0x000FFFFFFFE00000ull\r
#define PAGING_1G_ADDRESS_MASK_64  0x000FFFFFC0000000ull\r
\r
#define PAGING_L1_ADDRESS_SHIFT  12\r
#define PAGING_L2_ADDRESS_SHIFT  21\r
#define PAGING_L3_ADDRESS_SHIFT  30\r
#define PAGING_L4_ADDRESS_SHIFT  39\r
\r
#define PAGING_PML4E_NUMBER  4\r
\r
#define PAGETABLE_ENTRY_MASK  ((1UL << 9) - 1)\r
#define PML4_OFFSET(x)  ( (x >> 39) & PAGETABLE_ENTRY_MASK)\r
#define PDP_OFFSET(x)   ( (x >> 30) & PAGETABLE_ENTRY_MASK)\r
#define PDE_OFFSET(x)   ( (x >> 21) & PAGETABLE_ENTRY_MASK)\r
#define PTE_OFFSET(x)   ( (x >> 12) & PAGETABLE_ENTRY_MASK)\r
#define PAGING_1G_ADDRESS_MASK_64  0x000FFFFFC0000000ull\r
\r
#endif\r
Commit	Line	Data
9d686149 AP	1	/** @file\r
	2	\r
	3	x86_64 Page Tables structures\r
	4	\r
	5	Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
	6	Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.<BR>\r
	7	\r
	8	SPDX-License-Identifier: BSD-2-Clause-Patent\r
	9	\r
	10	Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h\r
	11	\r
	12	**/\r
	13	\r
	14	#ifndef PAGE_TABLE_H_\r
	15	#define PAGE_TABLE_H_\r
	16	\r
	17	#include <Base.h>\r
	18	\r
	19	#pragma pack(1)\r
	20	\r
	21	//\r
	22	// Page-Map Level-4 Offset (PML4) and\r
	23	// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
	24	//\r
	25	\r
	26	typedef union {\r
	27	struct {\r
ac0a286f MK	28	UINT64 Present : 1; // 0 = Not present in memory,\r
	29	// 1 = Present in memory\r
	30	UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write\r
	31	UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User\r
	32	UINT64 WriteThrough : 1; // 0 = Write-Back caching,\r
	33	// 1 = Write-Through caching\r
	34	UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached\r
	35	UINT64 Accessed : 1; // 0 = Not accessed,\r
	36	// 1 = Accessed (set by CPU)\r
	37	UINT64 Reserved : 1; // Reserved\r
	38	UINT64 MustBeZero : 2; // Must Be Zero\r
	39	UINT64 Available : 3; // Available for use by system software\r
	40	UINT64 PageTableBaseAddress : 40; // Page Table Base Address\r
	41	UINT64 AvabilableHigh : 11; // Available for use by system software\r
	42	UINT64 Nx : 1; // No Execute bit\r
9d686149 AP	43	} Bits;\r
	44	UINT64 Uint64;\r
	45	} PAGE_MAP_AND_DIRECTORY_POINTER;\r
	46	\r
	47	//\r
	48	// Page Table Entry 4KB\r
	49	//\r
	50	typedef union {\r
	51	struct {\r
ac0a286f MK	52	UINT64 Present : 1; // 0 = Not present in memory,\r
	53	// 1 = Present in memory\r
	54	UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write\r
	55	UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User\r
	56	UINT64 WriteThrough : 1; // 0 = Write-Back caching,\r
	57	// 1 = Write-Through caching\r
	58	UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached\r
	59	UINT64 Accessed : 1; // 0 = Not accessed,\r
	60	// 1 = Accessed (set by CPU)\r
	61	UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by\r
	62	// processor on access to page\r
	63	UINT64 PAT : 1; //\r
	64	UINT64 Global : 1; // 0 = Not global page, 1 = global page\r
	65	// TLB not cleared on CR3 write\r
	66	UINT64 Available : 3; // Available for use by system software\r
	67	UINT64 PageTableBaseAddress : 40; // Page Table Base Address\r
	68	UINT64 AvabilableHigh : 11; // Available for use by system software\r
	69	UINT64 Nx : 1; // 0 = Execute Code,\r
	70	// 1 = No Code Execution\r
9d686149 AP	71	} Bits;\r
	72	UINT64 Uint64;\r
	73	} PAGE_TABLE_4K_ENTRY;\r
	74	\r
	75	//\r
	76	// Page Table Entry 2MB\r
	77	//\r
	78	typedef union {\r
	79	struct {\r
ac0a286f MK	80	UINT64 Present : 1; // 0 = Not present in memory,\r
	81	// 1 = Present in memory\r
	82	UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write\r
	83	UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User\r
	84	UINT64 WriteThrough : 1; // 0 = Write-Back caching,\r
	85	// 1=Write-Through caching\r
	86	UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached\r
	87	UINT64 Accessed : 1; // 0 = Not accessed,\r
	88	// 1 = Accessed (set by CPU)\r
	89	UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by\r
	90	// processor on access to page\r
	91	UINT64 MustBe1 : 1; // Must be 1\r
	92	UINT64 Global : 1; // 0 = Not global page, 1 = global page\r
	93	// TLB not cleared on CR3 write\r
	94	UINT64 Available : 3; // Available for use by system software\r
	95	UINT64 PAT : 1; //\r
	96	UINT64 MustBeZero : 8; // Must be zero;\r
	97	UINT64 PageTableBaseAddress : 31; // Page Table Base Address\r
	98	UINT64 AvabilableHigh : 11; // Available for use by system software\r
	99	UINT64 Nx : 1; // 0 = Execute Code,\r
	100	// 1 = No Code Execution\r
9d686149 AP	101	} Bits;\r
	102	UINT64 Uint64;\r
	103	} PAGE_TABLE_ENTRY;\r
	104	\r
	105	//\r
	106	// Page Table Entry 1GB\r
	107	//\r
	108	typedef union {\r
	109	struct {\r
ac0a286f MK	110	UINT64 Present : 1; // 0 = Not present in memory,\r
	111	// 1 = Present in memory\r
	112	UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write\r
	113	UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User\r
	114	UINT64 WriteThrough : 1; // 0 = Write-Back caching,\r
	115	// 1 = Write-Through caching\r
	116	UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached\r
	117	UINT64 Accessed : 1; // 0 = Not accessed,\r
	118	// 1 = Accessed (set by CPU)\r
	119	UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by\r
	120	// processor on access to page\r
	121	UINT64 MustBe1 : 1; // Must be 1\r
	122	UINT64 Global : 1; // 0 = Not global page, 1 = global page\r
	123	// TLB not cleared on CR3 write\r
	124	UINT64 Available : 3; // Available for use by system software\r
	125	UINT64 PAT : 1; //\r
	126	UINT64 MustBeZero : 17; // Must be zero;\r
	127	UINT64 PageTableBaseAddress : 22; // Page Table Base Address\r
	128	UINT64 AvabilableHigh : 11; // Available for use by system software\r
	129	UINT64 Nx : 1; // 0 = Execute Code,\r
	130	// 1 = No Code Execution\r
9d686149 AP	131	} Bits;\r
	132	UINT64 Uint64;\r
	133	} PAGE_TABLE_1G_ENTRY;\r
	134	\r
	135	#pragma pack()\r
	136	\r
ac0a286f MK	137	#define IA32_PG_P BIT0\r
	138	#define IA32_PG_RW BIT1\r
	139	#define IA32_PG_PS BIT7\r
9d686149	140	\r
ac0a286f	141	#define PAGING_PAE_INDEX_MASK 0x1FF\r
9d686149	142	\r
ac0a286f MK	143	#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull\r
	144	#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r
	145	#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
9d686149	146	\r
ac0a286f MK	147	#define PAGING_L1_ADDRESS_SHIFT 12\r
	148	#define PAGING_L2_ADDRESS_SHIFT 21\r
	149	#define PAGING_L3_ADDRESS_SHIFT 30\r
	150	#define PAGING_L4_ADDRESS_SHIFT 39\r
9d686149	151	\r
ac0a286f	152	#define PAGING_PML4E_NUMBER 4\r
9d686149	153	\r
ac0a286f MK	154	#define PAGETABLE_ENTRY_MASK ((1UL << 9) - 1)\r
	155	#define PML4_OFFSET(x) ( (x >> 39) & PAGETABLE_ENTRY_MASK)\r
	156	#define PDP_OFFSET(x) ( (x >> 30) & PAGETABLE_ENTRY_MASK)\r
	157	#define PDE_OFFSET(x) ( (x >> 21) & PAGETABLE_ENTRY_MASK)\r
	158	#define PTE_OFFSET(x) ( (x >> 12) & PAGETABLE_ENTRY_MASK)\r
	159	#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
9d686149 AP	160	\r
9d686149 AP	161	#endif\r