OvmfPkg/Include/IndustryStandard/PageTable.h

   1 /** @file
   2
   3   x86_64 Page Tables structures
   4
   5   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   6   Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.<BR>
   7
   8   SPDX-License-Identifier: BSD-2-Clause-Patent
   9
  10   Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
  11
  12 **/
  13
  14 #ifndef PAGE_TABLE_H_
  15 #define PAGE_TABLE_H_
  16
  17 #include <Base.h>
  18
  19 #pragma pack(1)
  20
  21 //
  22 // Page-Map Level-4 Offset (PML4) and
  23 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
  24 //
  25
  26 typedef union {
  27   struct {
  28     UINT64    Present              : 1;  // 0 = Not present in memory,
  29                                          //   1 = Present in memory
  30     UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write
  31     UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User
  32     UINT64    WriteThrough         : 1;  // 0 = Write-Back caching,
  33                                          //   1 = Write-Through caching
  34     UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached
  35     UINT64    Accessed             : 1;  // 0 = Not accessed,
  36                                          //   1 = Accessed (set by CPU)
  37     UINT64    Reserved             : 1;  // Reserved
  38     UINT64    MustBeZero           : 2;  // Must Be Zero
  39     UINT64    Available            : 3;  // Available for use by system software
  40     UINT64    PageTableBaseAddress : 40; // Page Table Base Address
  41     UINT64    AvabilableHigh       : 11; // Available for use by system software
  42     UINT64    Nx                   : 1;  // No Execute bit
  43   } Bits;
  44   UINT64    Uint64;
  45 } PAGE_MAP_AND_DIRECTORY_POINTER;
  46
  47 //
  48 // Page Table Entry 4KB
  49 //
  50 typedef union {
  51   struct {
  52     UINT64    Present              : 1;  // 0 = Not present in memory,
  53                                          //   1 = Present in memory
  54     UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write
  55     UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User
  56     UINT64    WriteThrough         : 1;  // 0 = Write-Back caching,
  57                                          //   1 = Write-Through caching
  58     UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached
  59     UINT64    Accessed             : 1;  // 0 = Not accessed,
  60                                          //   1 = Accessed (set by CPU)
  61     UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by
  62                                          //   processor on access to page
  63     UINT64    PAT                  : 1;  //
  64     UINT64    Global               : 1;  // 0 = Not global page, 1 = global page
  65                                          //   TLB not cleared on CR3 write
  66     UINT64    Available            : 3;  // Available for use by system software
  67     UINT64    PageTableBaseAddress : 40; // Page Table Base Address
  68     UINT64    AvabilableHigh       : 11; // Available for use by system software
  69     UINT64    Nx                   : 1;  // 0 = Execute Code,
  70                                          //   1 = No Code Execution
  71   } Bits;
  72   UINT64    Uint64;
  73 } PAGE_TABLE_4K_ENTRY;
  74
  75 //
  76 // Page Table Entry 2MB
  77 //
  78 typedef union {
  79   struct {
  80     UINT64    Present              : 1;  // 0 = Not present in memory,
  81                                          //   1 = Present in memory
  82     UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write
  83     UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User
  84     UINT64    WriteThrough         : 1;  // 0 = Write-Back caching,
  85                                          //   1=Write-Through caching
  86     UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached
  87     UINT64    Accessed             : 1;  // 0 = Not accessed,
  88                                          //   1 = Accessed (set by CPU)
  89     UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by
  90                                          //   processor on access to page
  91     UINT64    MustBe1              : 1;  // Must be 1
  92     UINT64    Global               : 1;  // 0 = Not global page, 1 = global page
  93                                          //   TLB not cleared on CR3 write
  94     UINT64    Available            : 3;  // Available for use by system software
  95     UINT64    PAT                  : 1;  //
  96     UINT64    MustBeZero           : 8;  // Must be zero;
  97     UINT64    PageTableBaseAddress : 31; // Page Table Base Address
  98     UINT64    AvabilableHigh       : 11; // Available for use by system software
  99     UINT64    Nx                   : 1;  // 0 = Execute Code,
 100                                          //   1 = No Code Execution
 101   } Bits;
 102   UINT64    Uint64;
 103 } PAGE_TABLE_ENTRY;
 104
 105 //
 106 // Page Table Entry 1GB
 107 //
 108 typedef union {
 109   struct {
 110     UINT64    Present              : 1;  // 0 = Not present in memory,
 111                                          //   1 = Present in memory
 112     UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write
 113     UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User
 114     UINT64    WriteThrough         : 1;  // 0 = Write-Back caching,
 115                                          //   1 = Write-Through caching
 116     UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached
 117     UINT64    Accessed             : 1;  // 0 = Not accessed,
 118                                          //   1 = Accessed (set by CPU)
 119     UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by
 120                                          //   processor on access to page
 121     UINT64    MustBe1              : 1;  // Must be 1
 122     UINT64    Global               : 1;  // 0 = Not global page, 1 = global page
 123                                          //   TLB not cleared on CR3 write
 124     UINT64    Available            : 3;  // Available for use by system software
 125     UINT64    PAT                  : 1;  //
 126     UINT64    MustBeZero           : 17; // Must be zero;
 127     UINT64    PageTableBaseAddress : 22; // Page Table Base Address
 128     UINT64    AvabilableHigh       : 11; // Available for use by system software
 129     UINT64    Nx                   : 1;  // 0 = Execute Code,
 130                                          //   1 = No Code Execution
 131   } Bits;
 132   UINT64    Uint64;
 133 } PAGE_TABLE_1G_ENTRY;
 134
 135 #pragma pack()
 136
 137 #define IA32_PG_P   BIT0
 138 #define IA32_PG_RW  BIT1
 139 #define IA32_PG_PS  BIT7
 140
 141 #define PAGING_PAE_INDEX_MASK  0x1FF
 142
 143 #define PAGING_4K_ADDRESS_MASK_64  0x000FFFFFFFFFF000ull
 144 #define PAGING_2M_ADDRESS_MASK_64  0x000FFFFFFFE00000ull
 145 #define PAGING_1G_ADDRESS_MASK_64  0x000FFFFFC0000000ull
 146
 147 #define PAGING_L1_ADDRESS_SHIFT  12
 148 #define PAGING_L2_ADDRESS_SHIFT  21
 149 #define PAGING_L3_ADDRESS_SHIFT  30
 150 #define PAGING_L4_ADDRESS_SHIFT  39
 151
 152 #define PAGING_PML4E_NUMBER  4
 153
 154 #define PAGETABLE_ENTRY_MASK  ((1UL << 9) - 1)
 155 #define PML4_OFFSET(x)  ( (x >> 39) & PAGETABLE_ENTRY_MASK)
 156 #define PDP_OFFSET(x)   ( (x >> 30) & PAGETABLE_ENTRY_MASK)
 157 #define PDE_OFFSET(x)   ( (x >> 21) & PAGETABLE_ENTRY_MASK)
 158 #define PTE_OFFSET(x)   ( (x >> 12) & PAGETABLE_ENTRY_MASK)
 159 #define PAGING_1G_ADDRESS_MASK_64  0x000FFFFFC0000000ull
 160
 161 #endif