projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| cb2e3007 LE |
1 | /** @file\r |
| 2 | Various register numbers and value bits based on the following publications:\r | |
| 3 | - Intel(R) datasheet 316966-002\r | |
| 4 | - Intel(R) datasheet 316972-004\r | |
| 5 | \r | |
| 6 | Copyright (C) 2015, Red Hat, Inc.\r | |
| 7 | Copyright (c) 2014, Gabriel L. Somlo <somlo@cmu.edu>\r | |
| 8 | \r | |
| 9 | This program and the accompanying materials are licensed and made available\r | |
| 10 | under the terms and conditions of the BSD License which accompanies this\r | |
| 11 | distribution. The full text of the license may be found at\r | |
| 12 | http://opensource.org/licenses/bsd-license.php\r | |
| 13 | \r | |
| 14 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r | |
| 15 | WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 16 | **/\r | |
| 17 | \r | |
| 18 | #ifndef __Q35_MCH_ICH9_H__\r | |
| 19 | #define __Q35_MCH_ICH9_H__\r | |
| 20 | \r | |
| 21 | #include <Library/PciLib.h>\r | |
| 7ecfa0aa LE |
22 | #include <Uefi/UefiBaseType.h>\r |
| 23 | #include <Uefi/UefiSpec.h>\r | |
| 24 | #include <Protocol/PciRootBridgeIo.h>\r | |
| cb2e3007 LE |
25 | \r |
| 26 | //\r | |
| 27 | // Host Bridge Device ID (DID) value for Q35/MCH\r | |
| 28 | //\r | |
| 29 | #define INTEL_Q35_MCH_DEVICE_ID 0x29C0\r | |
| 30 | \r | |
| 6b225ace LE |
31 | //\r |
| 32 | // B/D/F/Type: 0/0/0/PCI\r | |
| 33 | //\r | |
| 34 | #define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))\r | |
| 35 | \r | |
| 031e4ce2 LE |
36 | #define MCH_EXT_TSEG_MB 0x50\r |
| 37 | #define MCH_EXT_TSEG_MB_QUERY 0xFFFF\r | |
| 38 | \r | |
| 6b225ace LE |
39 | #define MCH_GGC 0x52\r |
| 40 | #define MCH_GGC_IVD BIT1\r | |
| 41 | \r | |
| 0aff49e2 LE |
42 | #define MCH_PCIEXBAR_LOW 0x60\r |
| 43 | #define MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF\r | |
| 44 | #define MCH_PCIEXBAR_BUS_FF 0\r | |
| 45 | #define MCH_PCIEXBAR_EN BIT0\r | |
| 46 | \r | |
| 47 | #define MCH_PCIEXBAR_HIGH 0x64\r | |
| 48 | #define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0\r | |
| 49 | \r | |
| ba1d245f LE |
50 | #define MCH_PAM0 0x90\r |
| 51 | #define MCH_PAM1 0x91\r | |
| 52 | #define MCH_PAM2 0x92\r | |
| 53 | #define MCH_PAM3 0x93\r | |
| 54 | #define MCH_PAM4 0x94\r | |
| 55 | #define MCH_PAM5 0x95\r | |
| 56 | #define MCH_PAM6 0x96\r | |
| 57 | \r | |
| 6b225ace LE |
58 | #define MCH_SMRAM 0x9D\r |
| 59 | #define MCH_SMRAM_D_LCK BIT4\r | |
| 60 | #define MCH_SMRAM_G_SMRAME BIT3\r | |
| 61 | \r | |
| 62 | #define MCH_ESMRAMC 0x9E\r | |
| 63 | #define MCH_ESMRAMC_H_SMRAME BIT7\r | |
| 64 | #define MCH_ESMRAMC_E_SMERR BIT6\r | |
| 65 | #define MCH_ESMRAMC_SM_CACHE BIT5\r | |
| 66 | #define MCH_ESMRAMC_SM_L1 BIT4\r | |
| 67 | #define MCH_ESMRAMC_SM_L2 BIT3\r | |
| 031e4ce2 | 68 | #define MCH_ESMRAMC_TSEG_EXT (BIT2 | BIT1)\r |
| 6b225ace LE |
69 | #define MCH_ESMRAMC_TSEG_8MB BIT2\r |
| 70 | #define MCH_ESMRAMC_TSEG_2MB BIT1\r | |
| 71 | #define MCH_ESMRAMC_TSEG_1MB 0\r | |
| 72 | #define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1)\r | |
| 73 | #define MCH_ESMRAMC_T_EN BIT0\r | |
| 74 | \r | |
| 75 | #define MCH_GBSM 0xA4\r | |
| 76 | #define MCH_GBSM_MB_SHIFT 20\r | |
| 77 | \r | |
| 78 | #define MCH_BGSM 0xA8\r | |
| 79 | #define MCH_BGSM_MB_SHIFT 20\r | |
| 80 | \r | |
| 81 | #define MCH_TSEGMB 0xAC\r | |
| 82 | #define MCH_TSEGMB_MB_SHIFT 20\r | |
| 83 | \r | |
| 84 | #define MCH_TOLUD 0xB0\r | |
| 85 | #define MCH_TOLUD_MB_SHIFT 4\r | |
| 86 | \r | |
| cb2e3007 LE |
87 | //\r |
| 88 | // B/D/F/Type: 0/0x1f/0/PCI\r | |
| 89 | //\r | |
| 90 | #define POWER_MGMT_REGISTER_Q35(Offset) \\r | |
| 91 | PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset))\r | |
| 92 | \r | |
| 7ecfa0aa LE |
93 | #define POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS(Offset) \\r |
| 94 | EFI_PCI_ADDRESS (0, 0x1f, 0, (Offset))\r | |
| 95 | \r | |
| 6b225ace LE |
96 | #define ICH9_PMBASE 0x40\r |
| 97 | #define ICH9_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \\r | |
| 98 | BIT10 | BIT9 | BIT8 | BIT7)\r | |
| 99 | \r | |
| 100 | #define ICH9_ACPI_CNTL 0x44\r | |
| 101 | #define ICH9_ACPI_CNTL_ACPI_EN BIT7\r | |
| 102 | \r | |
| 103 | #define ICH9_GEN_PMCON_1 0xA0\r | |
| 104 | #define ICH9_GEN_PMCON_1_SMI_LOCK BIT4\r | |
| 105 | \r | |
| 90721ba5 PA |
106 | #define ICH9_RCBA 0xF0\r |
| 107 | #define ICH9_RCBA_EN BIT0\r | |
| 108 | \r | |
| 6b225ace LE |
109 | //\r |
| 110 | // IO ports\r | |
| 111 | //\r | |
| 112 | #define ICH9_APM_CNT 0xB2\r | |
| 113 | #define ICH9_APM_STS 0xB3\r | |
| 114 | \r | |
| 115 | //\r | |
| 116 | // IO ports relative to PMBASE\r | |
| 117 | //\r | |
| 118 | #define ICH9_PMBASE_OFS_SMI_EN 0x30\r | |
| 119 | #define ICH9_SMI_EN_APMC_EN BIT5\r | |
| 120 | #define ICH9_SMI_EN_GBL_SMI_EN BIT0\r | |
| 121 | \r | |
| 90721ba5 PA |
122 | #define ICH9_ROOT_COMPLEX_BASE 0xFED1C000\r |
| 123 | \r | |
| cb2e3007 | 124 | #endif\r |