OvmfPkg/CsmSupportLib: move PAM register addresses to IndustryStandard

* Introduce the PIIX4_PAM* and MCH_PAM* macros under
  "OvmfPkg/Include/IndustryStandard". These macros capture the PAM
  register offsets (in PCI config space) on the respective Memory
  Controller B/D/F, from the respective data sheets.

* Under IndustryStandard, introduce the PMC_REGISTER_PIIX4() macro for
  PIIX4. (For Q35, we already have DRAMC_REGISTER_Q35().) In both cases,
  the B/D/F is 0/0/0.

* Under CsmSupportLib, replace the "PAMRegOffset" field (UINT8) in the
  PAM_REGISTER_VALUE structure with "PAMRegPciLibAddress" (UINTN). The new
  field contains the return value of the PCI_LIB_ADDRESS() macro.

* Under CsmSupportLib, replace the "mRegisterValues440" elements as
  follows:

    REG_PAMx_OFFSET_440, ReadEnableData, WriteEnableData
    -->
    PMC_REGISTER_PIIX4 (PIIX4_PAMx), ReadEnableData, WriteEnableData

* Under CsmSupportLib, replace the "mRegisterValuesQ35" elements as
  follows:

    REG_PAMx_OFFSET_Q35, ReadEnableData, WriteEnableData
    -->
    DRAMC_REGISTER_Q35 (MCH_PAMx), ReadEnableData, WriteEnableData

* Under CsmSupportLib, update the register address calculations as follows
  (for all of PciOr8(), PciAnd8() and PciRead8()):

    PCI_LIB_ADDRESS (
      PAM_PCI_BUS,
      PAM_PCI_DEV,
      PAM_PCI_FUNC,
      mRegisterValues[Index].PAMRegOffset
      )
    -->
    mRegisterValues[Index].PAMRegPciLibAddress

* Under CsmSupportLib, remove the PAM_PCI_* and REG_PAM*_OFFSET_* macros.

Technically speaking, these changes could be split into three patches
(IndustryStandard macro additions, CsmSupportLib code updates,
CsmSupportLib macro removals). However, the patch is not big, and in this
case it is actually helpful to present the code movement / refactoring in
one step, for easier verification.

Cc: Aleksei Kovura <alex3kov@zoho.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Ref: https://bugs.launchpad.net/qemu/+bug/1715700
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Aleksei Kovura <alex3kov@zoho.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c
index 8d5d2e58a99438e1b9b81739f28cf3900ec81667..c13d4bb88f47cd478d22f722fcd040e0f0f63d9d 100644 (file)
--- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c
+++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c
@@ -52,35 +52,35 @@ STATIC LEGACY_MEMORY_SECTION_INFO   mSectionArray[] = {
 };\r
 \r
 STATIC PAM_REGISTER_VALUE  mRegisterValues440[] = {\r
-  {REG_PAM1_OFFSET_440, 0x01, 0x02},\r
-  {REG_PAM1_OFFSET_440, 0x10, 0x20},\r
-  {REG_PAM2_OFFSET_440, 0x01, 0x02},\r
-  {REG_PAM2_OFFSET_440, 0x10, 0x20},\r
-  {REG_PAM3_OFFSET_440, 0x01, 0x02},\r
-  {REG_PAM3_OFFSET_440, 0x10, 0x20},\r
-  {REG_PAM4_OFFSET_440, 0x01, 0x02},\r
-  {REG_PAM4_OFFSET_440, 0x10, 0x20},\r
-  {REG_PAM5_OFFSET_440, 0x01, 0x02},\r
-  {REG_PAM5_OFFSET_440, 0x10, 0x20},\r
-  {REG_PAM6_OFFSET_440, 0x01, 0x02},\r
-  {REG_PAM6_OFFSET_440, 0x10, 0x20},\r
-  {REG_PAM0_OFFSET_440, 0x10, 0x20}\r
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM1), 0x01, 0x02},\r
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM1), 0x10, 0x20},\r
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM2), 0x01, 0x02},\r
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM2), 0x10, 0x20},\r
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM3), 0x01, 0x02},\r
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM3), 0x10, 0x20},\r
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM4), 0x01, 0x02},\r
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM4), 0x10, 0x20},\r
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM5), 0x01, 0x02},\r
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM5), 0x10, 0x20},\r
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM6), 0x01, 0x02},\r
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM6), 0x10, 0x20},\r
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM0), 0x10, 0x20}\r
 };\r
 \r
 STATIC PAM_REGISTER_VALUE  mRegisterValuesQ35[] = {\r
-  {REG_PAM1_OFFSET_Q35, 0x01, 0x02},\r
-  {REG_PAM1_OFFSET_Q35, 0x10, 0x20},\r
-  {REG_PAM2_OFFSET_Q35, 0x01, 0x02},\r
-  {REG_PAM2_OFFSET_Q35, 0x10, 0x20},\r
-  {REG_PAM3_OFFSET_Q35, 0x01, 0x02},\r
-  {REG_PAM3_OFFSET_Q35, 0x10, 0x20},\r
-  {REG_PAM4_OFFSET_Q35, 0x01, 0x02},\r
-  {REG_PAM4_OFFSET_Q35, 0x10, 0x20},\r
-  {REG_PAM5_OFFSET_Q35, 0x01, 0x02},\r
-  {REG_PAM5_OFFSET_Q35, 0x10, 0x20},\r
-  {REG_PAM6_OFFSET_Q35, 0x01, 0x02},\r
-  {REG_PAM6_OFFSET_Q35, 0x10, 0x20},\r
-  {REG_PAM0_OFFSET_Q35, 0x10, 0x20}\r
+  {DRAMC_REGISTER_Q35 (MCH_PAM1), 0x01, 0x02},\r
+  {DRAMC_REGISTER_Q35 (MCH_PAM1), 0x10, 0x20},\r
+  {DRAMC_REGISTER_Q35 (MCH_PAM2), 0x01, 0x02},\r
+  {DRAMC_REGISTER_Q35 (MCH_PAM2), 0x10, 0x20},\r
+  {DRAMC_REGISTER_Q35 (MCH_PAM3), 0x01, 0x02},\r
+  {DRAMC_REGISTER_Q35 (MCH_PAM3), 0x10, 0x20},\r
+  {DRAMC_REGISTER_Q35 (MCH_PAM4), 0x01, 0x02},\r
+  {DRAMC_REGISTER_Q35 (MCH_PAM4), 0x10, 0x20},\r
+  {DRAMC_REGISTER_Q35 (MCH_PAM5), 0x01, 0x02},\r
+  {DRAMC_REGISTER_Q35 (MCH_PAM5), 0x10, 0x20},\r
+  {DRAMC_REGISTER_Q35 (MCH_PAM6), 0x01, 0x02},\r
+  {DRAMC_REGISTER_Q35 (MCH_PAM6), 0x10, 0x20},\r
+  {DRAMC_REGISTER_Q35 (MCH_PAM0), 0x10, 0x20}\r
 };\r
 \r
 STATIC PAM_REGISTER_VALUE *mRegisterValues;\r
@@ -145,12 +145,12 @@ LegacyRegionManipulationInternal (
     if (ReadEnable != NULL) {\r
       if (*ReadEnable) {\r
         PciOr8 (\r
-          PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),\r
+          mRegisterValues[Index].PAMRegPciLibAddress,\r
           mRegisterValues[Index].ReadEnableData\r
           );\r
       } else {\r
         PciAnd8 (\r
-          PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),\r
+          mRegisterValues[Index].PAMRegPciLibAddress,\r
           (UINT8) (~mRegisterValues[Index].ReadEnableData)\r
           );\r
       }\r
@@ -158,12 +158,12 @@ LegacyRegionManipulationInternal (
     if (WriteEnable != NULL) {\r
       if (*WriteEnable) {\r
         PciOr8 (\r
-          PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),\r
+          mRegisterValues[Index].PAMRegPciLibAddress,\r
           mRegisterValues[Index].WriteEnableData\r
           );\r
       } else {\r
         PciAnd8 (\r
-          PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),\r
+          mRegisterValues[Index].PAMRegPciLibAddress,\r
           (UINT8) (~mRegisterValues[Index].WriteEnableData)\r
           );\r
       }\r
@@ -204,7 +204,7 @@ LegacyRegionGetInfoInternal (
   //\r
   *DescriptorCount = sizeof(mSectionArray) / sizeof (mSectionArray[0]);\r
   for (Index = 0; Index < *DescriptorCount; Index++) {\r
-    PamValue = PciRead8 (PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset));\r
+    PamValue = PciRead8 (mRegisterValues[Index].PAMRegPciLibAddress);\r
     mSectionArray[Index].ReadEnabled = FALSE;\r
     if ((PamValue & mRegisterValues[Index].ReadEnableData) != 0) {\r
       mSectionArray[Index].ReadEnabled = TRUE;\r

diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h
index f755a2a359e52293578611b10d174d291a8da495..01d3109a7d7deb879f7b45770d9cc403d7fb83a6 100644 (file)
--- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h
+++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h
@@ -30,26 +30,6 @@
 #include <Library/MemoryAllocationLib.h>\r
 #include <Library/UefiBootServicesTableLib.h>\r
 \r
-#define PAM_PCI_BUS        0\r
-#define PAM_PCI_DEV        0\r
-#define PAM_PCI_FUNC       0\r
-\r
-#define REG_PAM0_OFFSET_440    0x59    // Programmable Attribute Map 0\r
-#define REG_PAM1_OFFSET_440    0x5a    // Programmable Attribute Map 1\r
-#define REG_PAM2_OFFSET_440    0x5b    // Programmable Attribute Map 2\r
-#define REG_PAM3_OFFSET_440    0x5c    // Programmable Attribute Map 3\r
-#define REG_PAM4_OFFSET_440    0x5d    // Programmable Attribute Map 4\r
-#define REG_PAM5_OFFSET_440    0x5e    // Programmable Attribute Map 5\r
-#define REG_PAM6_OFFSET_440    0x5f    // Programmable Attribute Map 6\r
-\r
-#define REG_PAM0_OFFSET_Q35    0x90    // Programmable Attribute Map 0\r
-#define REG_PAM1_OFFSET_Q35    0x91    // Programmable Attribute Map 1\r
-#define REG_PAM2_OFFSET_Q35    0x92    // Programmable Attribute Map 2\r
-#define REG_PAM3_OFFSET_Q35    0x93    // Programmable Attribute Map 3\r
-#define REG_PAM4_OFFSET_Q35    0x94    // Programmable Attribute Map 4\r
-#define REG_PAM5_OFFSET_Q35    0x95    // Programmable Attribute Map 5\r
-#define REG_PAM6_OFFSET_Q35    0x96    // Programmable Attribute Map 6\r
-\r
 #define PAM_BASE_ADDRESS   0xc0000\r
 #define PAM_LIMIT_ADDRESS  BASE_1MB\r
 \r
@@ -67,7 +47,7 @@ typedef struct {
 // Provides a map of the PAM registers and bits used to set Read/Write access.\r
 //\r
 typedef struct {\r
-  UINT8   PAMRegOffset;\r
+  UINTN   PAMRegPciLibAddress;\r
   UINT8   ReadEnableData;\r
   UINT8   WriteEnableData;\r
 } PAM_REGISTER_VALUE;\r

diff --git a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
index baa4c063f16af84fdfa58b16f1c70fe6be462912..efe6e5c27834e272bcf6640978cc6f688f5198c8 100644 (file)
--- a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
+++ b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
@@ -27,6 +27,19 @@
 //\r
 #define INTEL_82441_DEVICE_ID 0x1237\r
 \r
+//\r
+// B/D/F/Type: 0/0/0/PCI\r
+//\r
+#define PMC_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))\r
+\r
+#define PIIX4_PAM0              0x59\r
+#define PIIX4_PAM1              0x5A\r
+#define PIIX4_PAM2              0x5B\r
+#define PIIX4_PAM3              0x5C\r
+#define PIIX4_PAM4              0x5D\r
+#define PIIX4_PAM5              0x5E\r
+#define PIIX4_PAM6              0x5F\r
+\r
 //\r
 // B/D/F/Type: 0/1/3/PCI\r
 //\r

diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
index 68485bec71f7d861a127a9fd5539871270a023e8..193a262e5b543d1cfed4a78942e2257e30eb3ec7 100644 (file)
--- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
+++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
@@ -47,6 +47,14 @@
 #define MCH_PCIEXBAR_HIGH     0x64\r
 #define MCH_PCIEXBAR_HIGHMASK   0xFFFFFFF0\r
 \r
+#define MCH_PAM0              0x90\r
+#define MCH_PAM1              0x91\r
+#define MCH_PAM2              0x92\r
+#define MCH_PAM3              0x93\r
+#define MCH_PAM4              0x94\r
+#define MCH_PAM5              0x95\r
+#define MCH_PAM6              0x96\r
+\r
 #define MCH_SMRAM             0x9D\r
 #define MCH_SMRAM_D_LCK         BIT4\r
 #define MCH_SMRAM_G_SMRAME      BIT3\r