[mirror_edk2.git] / OvmfPkg / IncompatiblePciDeviceSupportDxe / IncompatiblePciDeviceSupport.c

/** @file\r
  A simple DXE_DRIVER that causes the PCI Bus UEFI_DRIVER to allocate 64-bit\r
  MMIO BARs above 4 GB, regardless of option ROM availability (as long as a CSM\r
  is not present), conserving 32-bit MMIO aperture for 32-bit BARs.\r
\r
  Copyright (C) 2016, Red Hat, Inc.\r
  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
**/\r
\r
#include <IndustryStandard/Acpi10.h>\r
#include <IndustryStandard/Pci22.h>\r
\r
#include <Library/DebugLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
\r
#include <Protocol/IncompatiblePciDeviceSupport.h>\r
#include <Protocol/LegacyBios.h>\r
\r
//\r
// The Legacy BIOS protocol has been located.\r
//\r
STATIC BOOLEAN mLegacyBiosInstalled;\r
\r
//\r
// The protocol interface this driver produces.\r
//\r
STATIC EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL\r
                                                 mIncompatiblePciDeviceSupport;\r
\r
//\r
// Configuration template for the CheckDevice() protocol member function.\r
//\r
// Refer to Table 20 "ACPI 2.0 & 3.0 QWORD Address Space Descriptor Usage" in\r
// the Platform Init 1.4a Spec, Volume 5.\r
//\r
// This structure is interpreted by the UpdatePciInfo() function in the edk2\r
// PCI Bus UEFI_DRIVER.\r
//\r
#pragma pack (1)\r
typedef struct {\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR AddressSpaceDesc;\r
  EFI_ACPI_END_TAG_DESCRIPTOR       EndDesc;\r
} MMIO64_PREFERENCE;\r
#pragma pack ()\r
\r
STATIC CONST MMIO64_PREFERENCE mConfiguration = {\r
  //\r
  // AddressSpaceDesc\r
  //\r
  {\r
    ACPI_ADDRESS_SPACE_DESCRIPTOR,                 // Desc\r
    (UINT16)(                                      // Len\r
      sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) -\r
      OFFSET_OF (\r
        EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR,\r
        ResType\r
        )\r
      ),\r
    ACPI_ADDRESS_SPACE_TYPE_MEM,                   // ResType\r
    0,                                             // GenFlag\r
    0,                                             // SpecificFlag\r
    64,                                            // AddrSpaceGranularity:\r
                                                   //   aperture selection hint\r
                                                   //   for BAR allocation\r
    0,                                             // AddrRangeMin\r
    0,                                             // AddrRangeMax:\r
                                                   //   no special alignment\r
                                                   //   for affected BARs\r
    MAX_UINT64,                                    // AddrTranslationOffset:\r
                                                   //   hint covers all\r
                                                   //   eligible BARs\r
    0                                              // AddrLen:\r
                                                   //   use probed BAR size\r
  },\r
  //\r
  // EndDesc\r
  //\r
  {\r
    ACPI_END_TAG_DESCRIPTOR,                       // Desc\r
    0                                              // Checksum: to be ignored\r
  }\r
};\r
\r
//\r
// The CheckDevice() member function has been called.\r
//\r
STATIC BOOLEAN mCheckDeviceCalled;\r
\r
\r
/**\r
  Notification callback for Legacy BIOS protocol installation.\r
\r
  @param[in] Event    Event whose notification function is being invoked.\r
\r
  @param[in] Context  The pointer to the notification function's context, which\r
                      is implementation-dependent.\r
**/\r
STATIC\r
VOID\r
EFIAPI\r
LegacyBiosInstalled (\r
  IN EFI_EVENT Event,\r
  IN VOID      *Context\r
  )\r
{\r
  EFI_STATUS               Status;\r
  EFI_LEGACY_BIOS_PROTOCOL *LegacyBios;\r
\r
  ASSERT (!mCheckDeviceCalled);\r
\r
  Status = gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid,\r
                  NULL /* Registration */, (VOID **)&LegacyBios);\r
  if (EFI_ERROR (Status)) {\r
    return;\r
  }\r
\r
  mLegacyBiosInstalled = TRUE;\r
\r
  //\r
  // Close the event and deregister this callback.\r
  //\r
  Status = gBS->CloseEvent (Event);\r
  ASSERT_EFI_ERROR (Status);\r
}\r
\r
\r
/**\r
  Returns a list of ACPI resource descriptors that detail the special resource\r
  configuration requirements for an incompatible PCI device.\r
\r
  Prior to bus enumeration, the PCI bus driver will look for the presence of\r
  the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL. Only one instance of this\r
  protocol can be present in the system. For each PCI device that the PCI bus\r
  driver discovers, the PCI bus driver calls this function with the device's\r
  vendor ID, device ID, revision ID, subsystem vendor ID, and subsystem device\r
  ID. If the VendorId, DeviceId, RevisionId, SubsystemVendorId, or\r
  SubsystemDeviceId value is set to (UINTN)-1, that field will be ignored. The\r
  ID values that are not (UINTN)-1 will be used to identify the current device.\r
\r
  This function will only return EFI_SUCCESS. However, if the device is an\r
  incompatible PCI device, a list of ACPI resource descriptors will be returned\r
  in Configuration. Otherwise, NULL will be returned in Configuration instead.\r
  The PCI bus driver does not need to allocate memory for Configuration.\r
  However, it is the PCI bus driver's responsibility to free it. The PCI bus\r
  driver then can configure this device with the information that is derived\r
  from this list of resource nodes, rather than the result of BAR probing.\r
\r
  Only the following two resource descriptor types from the ACPI Specification\r
  may be used to describe the incompatible PCI device resource requirements:\r
  - QWORD Address Space Descriptor (ACPI 2.0, section 6.4.3.5.1; also ACPI 3.0)\r
  - End Tag (ACPI 2.0, section 6.4.2.8; also ACPI 3.0)\r
\r
  The QWORD Address Space Descriptor can describe memory, I/O, and bus number\r
  ranges for dynamic or fixed resources. The configuration of a PCI root bridge\r
  is described with one or more QWORD Address Space Descriptors, followed by an\r
  End Tag. See the ACPI Specification for details on the field values.\r
\r
  @param[in]  This                Pointer to the\r
                                  EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL\r
                                  instance.\r
\r
  @param[in]  VendorId            A unique ID to identify the manufacturer of\r
                                  the PCI device.  See the Conventional PCI\r
                                  Specification 3.0 for details.\r
\r
  @param[in]  DeviceId            A unique ID to identify the particular PCI\r
                                  device. See the Conventional PCI\r
                                  Specification 3.0 for details.\r
\r
  @param[in]  RevisionId          A PCI device-specific revision identifier.\r
                                  See the Conventional PCI Specification 3.0\r
                                  for details.\r
\r
  @param[in]  SubsystemVendorId   Specifies the subsystem vendor ID. See the\r
                                  Conventional PCI Specification 3.0 for\r
                                  details.\r
\r
  @param[in]  SubsystemDeviceId   Specifies the subsystem device ID. See the\r
                                  Conventional PCI Specification 3.0 for\r
                                  details.\r
\r
  @param[out] Configuration       A list of ACPI resource descriptors that\r
                                  detail the configuration requirement.\r
\r
  @retval EFI_SUCCESS   The function always returns EFI_SUCCESS.\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
CheckDevice (\r
  IN  EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL  *This,\r
  IN  UINTN                                         VendorId,\r
  IN  UINTN                                         DeviceId,\r
  IN  UINTN                                         RevisionId,\r
  IN  UINTN                                         SubsystemVendorId,\r
  IN  UINTN                                         SubsystemDeviceId,\r
  OUT VOID                                          **Configuration\r
  )\r
{\r
  mCheckDeviceCalled = TRUE;\r
\r
  //\r
  // Unlike the general description of this protocol member suggests, there is\r
  // nothing incompatible about the PCI devices that we'll match here. We'll\r
  // match all PCI devices, and generate exactly one QWORD Address Space\r
  // Descriptor for each. That descriptor will instruct the PCI Bus UEFI_DRIVER\r
  // not to degrade 64-bit MMIO BARs for the device, even if a PCI option ROM\r
  // BAR is present on the device.\r
  //\r
  // The concern captured in the PCI Bus UEFI_DRIVER is that a legacy BIOS boot\r
  // (via a CSM) could dispatch a legacy option ROM on the device, which might\r
  // have trouble with MMIO BARs that have been allocated outside of the 32-bit\r
  // address space. But, if we don't support legacy option ROMs at all, then\r
  // this problem cannot arise.\r
  //\r
  if (mLegacyBiosInstalled) {\r
    //\r
    // Don't interfere with resource degradation.\r
    //\r
    *Configuration = NULL;\r
    return EFI_SUCCESS;\r
  }\r
\r
  //\r
  // This member function is mis-specified actually: it is supposed to allocate\r
  // memory, but as specified, it could not return an error status. Thankfully,\r
  // the edk2 PCI Bus UEFI_DRIVER actually handles error codes; see the\r
  // UpdatePciInfo() function.\r
  //\r
  *Configuration = AllocateCopyPool (sizeof mConfiguration, &mConfiguration);\r
  if (*Configuration == NULL) {\r
    DEBUG ((EFI_D_WARN,\r
      "%a: 64-bit MMIO BARs may be degraded for PCI 0x%04x:0x%04x (rev %d)\n",\r
      __FUNCTION__, (UINT32)VendorId, (UINT32)DeviceId, (UINT8)RevisionId));\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
  return EFI_SUCCESS;\r
}\r
\r
\r
/**\r
  Entry point for this driver.\r
\r
  @param[in] ImageHandle  Image handle of this driver.\r
  @param[in] SystemTable  Pointer to SystemTable.\r
\r
  @retval EFI_SUCESS       Driver has loaded successfully.\r
  @retval EFI_UNSUPPORTED  PCI resource allocation has been disabled.\r
  @retval EFI_UNSUPPORTED  There is no 64-bit PCI MMIO aperture.\r
  @return                  Error codes from lower level functions.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
DriverInitialize (\r
  IN EFI_HANDLE       ImageHandle,\r
  IN EFI_SYSTEM_TABLE *SystemTable\r
  )\r
{\r
  EFI_STATUS Status;\r
  EFI_EVENT  Event;\r
  VOID       *Registration;\r
\r
  //\r
  // If the PCI Bus driver is not supposed to allocate resources, then it makes\r
  // no sense to install a protocol that influences the resource allocation.\r
  //\r
  // Similarly, if there is no 64-bit PCI MMIO aperture, then 64-bit MMIO BARs\r
  // have to be allocated under 4 GB unconditionally.\r
  //\r
  if (PcdGetBool (PcdPciDisableBusEnumeration) ||\r
      PcdGet64 (PcdPciMmio64Size) == 0) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  //\r
  // Otherwise, create a protocol notify to see if a CSM is present. (With the\r
  // CSM absent, the PCI Bus driver won't have to worry about allocating 64-bit\r
  // MMIO BARs in the 32-bit MMIO aperture, for the sake of a legacy BIOS.)\r
  //\r
  // If the Legacy BIOS Protocol is present at the time of this driver starting\r
  // up, we can mark immediately that the PCI Bus driver should perform the\r
  // usual 64-bit MMIO BAR degradation.\r
  //\r
  // Otherwise, if the Legacy BIOS Protocol is absent at startup, it may be\r
  // installed later. However, if it doesn't show up until the first\r
  // EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL.CheckDevice() call from the\r
  // PCI Bus driver, then it never will:\r
  //\r
  // 1. The following drivers are dispatched in some unspecified order:\r
  //    - PCI Host Bridge DXE_DRIVER,\r
  //    - PCI Bus UEFI_DRIVER,\r
  //    - this DXE_DRIVER,\r
  //    - Legacy BIOS DXE_DRIVER.\r
  //\r
  // 2. The DXE_CORE enters BDS.\r
  //\r
  // 3. The platform BDS connects the PCI Root Bridge IO instances (produced by\r
  //    the PCI Host Bridge DXE_DRIVER).\r
  //\r
  // 4. The PCI Bus UEFI_DRIVER enumerates resources and calls into this\r
  //    DXE_DRIVER (CheckDevice()).\r
  //\r
  // 5. This driver remembers if EFI_LEGACY_BIOS_PROTOCOL has been installed\r
  //    sometime during step 1 (produced by the Legacy BIOS DXE_DRIVER).\r
  //\r
  // For breaking this order, the Legacy BIOS DXE_DRIVER would have to install\r
  // its protocol after the firmware enters BDS, which cannot happen.\r
  //\r
  Status = gBS->CreateEvent (EVT_NOTIFY_SIGNAL, TPL_CALLBACK,\r
                  LegacyBiosInstalled, NULL /* Context */, &Event);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Status = gBS->RegisterProtocolNotify (&gEfiLegacyBiosProtocolGuid, Event,\r
                  &Registration);\r
  if (EFI_ERROR (Status)) {\r
    goto CloseEvent;\r
  }\r
\r
  Status = gBS->SignalEvent (Event);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  mIncompatiblePciDeviceSupport.CheckDevice = CheckDevice;\r
  Status = gBS->InstallMultipleProtocolInterfaces (&ImageHandle,\r
                  &gEfiIncompatiblePciDeviceSupportProtocolGuid,\r
                  &mIncompatiblePciDeviceSupport, NULL);\r
  if (EFI_ERROR (Status)) {\r
    goto CloseEvent;\r
  }\r
\r
  return EFI_SUCCESS;\r
\r
CloseEvent:\r
  if (!mLegacyBiosInstalled) {\r
    EFI_STATUS CloseStatus;\r
\r
    CloseStatus = gBS->CloseEvent (Event);\r
    ASSERT_EFI_ERROR (CloseStatus);\r
  }\r
\r
  return Status;\r
}\r
Commit	Line	Data
855743f7 LE	1	/** @file\r
	2	A simple DXE_DRIVER that causes the PCI Bus UEFI_DRIVER to allocate 64-bit\r
	3	MMIO BARs above 4 GB, regardless of option ROM availability (as long as a CSM\r
	4	is not present), conserving 32-bit MMIO aperture for 32-bit BARs.\r
	5	\r
	6	Copyright (C) 2016, Red Hat, Inc.\r
a419fd0d	7	Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
855743f7	8	\r
b26f0cf9	9	SPDX-License-Identifier: BSD-2-Clause-Patent\r
855743f7 LE	10	**/\r
	11	\r
	12	#include <IndustryStandard/Acpi10.h>\r
	13	#include <IndustryStandard/Pci22.h>\r
	14	\r
	15	#include <Library/DebugLib.h>\r
	16	#include <Library/MemoryAllocationLib.h>\r
	17	#include <Library/PcdLib.h>\r
	18	#include <Library/UefiBootServicesTableLib.h>\r
	19	\r
	20	#include <Protocol/IncompatiblePciDeviceSupport.h>\r
	21	#include <Protocol/LegacyBios.h>\r
	22	\r
	23	//\r
	24	// The Legacy BIOS protocol has been located.\r
	25	//\r
	26	STATIC BOOLEAN mLegacyBiosInstalled;\r
	27	\r
	28	//\r
	29	// The protocol interface this driver produces.\r
	30	//\r
	31	STATIC EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL\r
	32	mIncompatiblePciDeviceSupport;\r
	33	\r
	34	//\r
	35	// Configuration template for the CheckDevice() protocol member function.\r
	36	//\r
	37	// Refer to Table 20 "ACPI 2.0 & 3.0 QWORD Address Space Descriptor Usage" in\r
	38	// the Platform Init 1.4a Spec, Volume 5.\r
	39	//\r
	40	// This structure is interpreted by the UpdatePciInfo() function in the edk2\r
	41	// PCI Bus UEFI_DRIVER.\r
	42	//\r
	43	#pragma pack (1)\r
	44	typedef struct {\r
	45	EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR AddressSpaceDesc;\r
	46	EFI_ACPI_END_TAG_DESCRIPTOR EndDesc;\r
	47	} MMIO64_PREFERENCE;\r
	48	#pragma pack ()\r
	49	\r
	50	STATIC CONST MMIO64_PREFERENCE mConfiguration = {\r
	51	//\r
	52	// AddressSpaceDesc\r
	53	//\r
	54	{\r
	55	ACPI_ADDRESS_SPACE_DESCRIPTOR, // Desc\r
	56	(UINT16)( // Len\r
	57	sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) -\r
	58	OFFSET_OF (\r
	59	EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR,\r
	60	ResType\r
	61	)\r
	62	),\r
	63	ACPI_ADDRESS_SPACE_TYPE_MEM, // ResType\r
a419fd0d RN	64	0, // GenFlag\r
a419fd0d RN	65	0, // SpecificFlag\r
855743f7 LE	66	64, // AddrSpaceGranularity:\r
	67	// aperture selection hint\r
	68	// for BAR allocation\r
a419fd0d RN	69	0, // AddrRangeMin\r
a419fd0d RN	70	0, // AddrRangeMax:\r
855743f7 LE	71	// no special alignment\r
855743f7 LE	72	// for affected BARs\r
a419fd0d	73	MAX_UINT64, // AddrTranslationOffset:\r
855743f7 LE	74	// hint covers all\r
855743f7 LE	75	// eligible BARs\r
a419fd0d	76	0 // AddrLen:\r
855743f7 LE	77	// use probed BAR size\r
	78	},\r
	79	//\r
	80	// EndDesc\r
	81	//\r
	82	{\r
	83	ACPI_END_TAG_DESCRIPTOR, // Desc\r
	84	0 // Checksum: to be ignored\r
	85	}\r
	86	};\r
	87	\r
	88	//\r
	89	// The CheckDevice() member function has been called.\r
	90	//\r
	91	STATIC BOOLEAN mCheckDeviceCalled;\r
	92	\r
	93	\r
	94	/**\r
	95	Notification callback for Legacy BIOS protocol installation.\r
	96	\r
	97	@param[in] Event Event whose notification function is being invoked.\r
	98	\r
	99	@param[in] Context The pointer to the notification function's context, which\r
	100	is implementation-dependent.\r
	101	**/\r
	102	STATIC\r
	103	VOID\r
	104	EFIAPI\r
	105	LegacyBiosInstalled (\r
	106	IN EFI_EVENT Event,\r
	107	IN VOID *Context\r
	108	)\r
	109	{\r
	110	EFI_STATUS Status;\r
	111	EFI_LEGACY_BIOS_PROTOCOL *LegacyBios;\r
	112	\r
	113	ASSERT (!mCheckDeviceCalled);\r
	114	\r
	115	Status = gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid,\r
	116	NULL /* Registration /, (VOID *)&LegacyBios);\r
	117	if (EFI_ERROR (Status)) {\r
	118	return;\r
	119	}\r
	120	\r
	121	mLegacyBiosInstalled = TRUE;\r
	122	\r
	123	//\r
	124	// Close the event and deregister this callback.\r
	125	//\r
	126	Status = gBS->CloseEvent (Event);\r
	127	ASSERT_EFI_ERROR (Status);\r
	128	}\r
	129	\r
	130	\r
	131	/**\r
	132	Returns a list of ACPI resource descriptors that detail the special resource\r
	133	configuration requirements for an incompatible PCI device.\r
	134	\r
	135	Prior to bus enumeration, the PCI bus driver will look for the presence of\r
	136	the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL. Only one instance of this\r
	137	protocol can be present in the system. For each PCI device that the PCI bus\r
	138	driver discovers, the PCI bus driver calls this function with the device's\r
	139	vendor ID, device ID, revision ID, subsystem vendor ID, and subsystem device\r
	140	ID. If the VendorId, DeviceId, RevisionId, SubsystemVendorId, or\r
141	SubsystemDeviceId value is set to (UINTN)-1, that field will be ignored. The\r
142	ID values that are not (UINTN)-1 will be used to identify the current device.\r
143	\r
144	This function will only return EFI_SUCCESS. However, if the device is an\r
145	incompatible PCI device, a list of ACPI resource descriptors will be returned\r
146	in Configuration. Otherwise, NULL will be returned in Configuration instead.\r
147	The PCI bus driver does not need to allocate memory for Configuration.\r
148	However, it is the PCI bus driver's responsibility to free it. The PCI bus\r
149	driver then can configure this device with the information that is derived\r
150	from this list of resource nodes, rather than the result of BAR probing.\r
151	\r
152	Only the following two resource descriptor types from the ACPI Specification\r
153	may be used to describe the incompatible PCI device resource requirements:\r
154	- QWORD Address Space Descriptor (ACPI 2.0, section 6.4.3.5.1; also ACPI 3.0)\r
155	- End Tag (ACPI 2.0, section 6.4.2.8; also ACPI 3.0)\r
156	\r
157	The QWORD Address Space Descriptor can describe memory, I/O, and bus number\r
158	ranges for dynamic or fixed resources. The configuration of a PCI root bridge\r
159	is described with one or more QWORD Address Space Descriptors, followed by an\r
160	End Tag. See the ACPI Specification for details on the field values.\r
161	\r
162	@param[in] This Pointer to the\r
163	EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL\r
164	instance.\r
165	\r
166	@param[in] VendorId A unique ID to identify the manufacturer of\r
167	the PCI device. See the Conventional PCI\r
168	Specification 3.0 for details.\r
169	\r
170	@param[in] DeviceId A unique ID to identify the particular PCI\r
171	device. See the Conventional PCI\r
172	Specification 3.0 for details.\r
173	\r
174	@param[in] RevisionId A PCI device-specific revision identifier.\r
175	See the Conventional PCI Specification 3.0\r
176	for details.\r
177	\r
178	@param[in] SubsystemVendorId Specifies the subsystem vendor ID. See the\r
179	Conventional PCI Specification 3.0 for\r
180	details.\r
181	\r
182	@param[in] SubsystemDeviceId Specifies the subsystem device ID. See the\r
183	Conventional PCI Specification 3.0 for\r
184	details.\r
185	\r
186	@param[out] Configuration A list of ACPI resource descriptors that\r
187	detail the configuration requirement.\r
188	\r
189	@retval EFI_SUCCESS The function always returns EFI_SUCCESS.\r
190	**/\r
191	STATIC\r
192	EFI_STATUS\r
193	EFIAPI\r
194	CheckDevice (\r
195	IN EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *This,\r
196	IN UINTN VendorId,\r
197	IN UINTN DeviceId,\r
198	IN UINTN RevisionId,\r
199	IN UINTN SubsystemVendorId,\r
200	IN UINTN SubsystemDeviceId,\r
201	OUT VOID **Configuration\r
202	)\r
203	{\r
204	mCheckDeviceCalled = TRUE;\r
205	\r
206	//\r
207	// Unlike the general description of this protocol member suggests, there is\r
208	// nothing incompatible about the PCI devices that we'll match here. We'll\r
209	// match all PCI devices, and generate exactly one QWORD Address Space\r
210	// Descriptor for each. That descriptor will instruct the PCI Bus UEFI_DRIVER\r
211	// not to degrade 64-bit MMIO BARs for the device, even if a PCI option ROM\r
212	// BAR is present on the device.\r
213	//\r
214	// The concern captured in the PCI Bus UEFI_DRIVER is that a legacy BIOS boot\r
215	// (via a CSM) could dispatch a legacy option ROM on the device, which might\r
216	// have trouble with MMIO BARs that have been allocated outside of the 32-bit\r
217	// address space. But, if we don't support legacy option ROMs at all, then\r
218	// this problem cannot arise.\r
219	//\r
220	if (mLegacyBiosInstalled) {\r
221	//\r
222	// Don't interfere with resource degradation.\r
223	//\r
224	*Configuration = NULL;\r
225	return EFI_SUCCESS;\r
226	}\r
227	\r
228	//\r
229	// This member function is mis-specified actually: it is supposed to allocate\r
230	// memory, but as specified, it could not return an error status. Thankfully,\r
231	// the edk2 PCI Bus UEFI_DRIVER actually handles error codes; see the\r
232	// UpdatePciInfo() function.\r
233	//\r
234	*Configuration = AllocateCopyPool (sizeof mConfiguration, &mConfiguration);\r
235	if (*Configuration == NULL) {\r
236	DEBUG ((EFI_D_WARN,\r
237	"%a: 64-bit MMIO BARs may be degraded for PCI 0x%04x:0x%04x (rev %d)\n",\r
238	__FUNCTION__, (UINT32)VendorId, (UINT32)DeviceId, (UINT8)RevisionId));\r
239	return EFI_OUT_OF_RESOURCES;\r
240	}\r
241	return EFI_SUCCESS;\r
242	}\r
243	\r
244	\r
245	/**\r
246	Entry point for this driver.\r
247	\r
248	@param[in] ImageHandle Image handle of this driver.\r
249	@param[in] SystemTable Pointer to SystemTable.\r
250	\r
251	@retval EFI_SUCESS Driver has loaded successfully.\r
252	@retval EFI_UNSUPPORTED PCI resource allocation has been disabled.\r
253	@retval EFI_UNSUPPORTED There is no 64-bit PCI MMIO aperture.\r
254	@return Error codes from lower level functions.\r
255	\r
256	**/\r
257	EFI_STATUS\r
258	EFIAPI\r
259	DriverInitialize (\r
260	IN EFI_HANDLE ImageHandle,\r
261	IN EFI_SYSTEM_TABLE *SystemTable\r
262	)\r
263	{\r
264	EFI_STATUS Status;\r
265	EFI_EVENT Event;\r
266	VOID *Registration;\r
267	\r
268	//\r
269	// If the PCI Bus driver is not supposed to allocate resources, then it makes\r
270	// no sense to install a protocol that influences the resource allocation.\r
271	//\r
272	// Similarly, if there is no 64-bit PCI MMIO aperture, then 64-bit MMIO BARs\r
273	// have to be allocated under 4 GB unconditionally.\r
274	//\r
275	if (PcdGetBool (PcdPciDisableBusEnumeration) \|\|\r
276	PcdGet64 (PcdPciMmio64Size) == 0) {\r
277	return EFI_UNSUPPORTED;\r
278	}\r
279	\r
280	//\r
281	// Otherwise, create a protocol notify to see if a CSM is present. (With the\r
282	// CSM absent, the PCI Bus driver won't have to worry about allocating 64-bit\r
283	// MMIO BARs in the 32-bit MMIO aperture, for the sake of a legacy BIOS.)\r
284	//\r
285	// If the Legacy BIOS Protocol is present at the time of this driver starting\r
286	// up, we can mark immediately that the PCI Bus driver should perform the\r
287	// usual 64-bit MMIO BAR degradation.\r
288	//\r
289	// Otherwise, if the Legacy BIOS Protocol is absent at startup, it may be\r
290	// installed later. However, if it doesn't show up until the first\r
291	// EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL.CheckDevice() call from the\r
292	// PCI Bus driver, then it never will:\r
293	//\r
294	// 1. The following drivers are dispatched in some unspecified order:\r
295	// - PCI Host Bridge DXE_DRIVER,\r
296	// - PCI Bus UEFI_DRIVER,\r
297	// - this DXE_DRIVER,\r
298	// - Legacy BIOS DXE_DRIVER.\r
299	//\r
300	// 2. The DXE_CORE enters BDS.\r
301	//\r
302	// 3. The platform BDS connects the PCI Root Bridge IO instances (produced by\r
303	// the PCI Host Bridge DXE_DRIVER).\r
304	//\r
305	// 4. The PCI Bus UEFI_DRIVER enumerates resources and calls into this\r
306	// DXE_DRIVER (CheckDevice()).\r
307	//\r
308	// 5. This driver remembers if EFI_LEGACY_BIOS_PROTOCOL has been installed\r
309	// sometime during step 1 (produced by the Legacy BIOS DXE_DRIVER).\r
310	//\r
311	// For breaking this order, the Legacy BIOS DXE_DRIVER would have to install\r
312	// its protocol after the firmware enters BDS, which cannot happen.\r
313	//\r
314	Status = gBS->CreateEvent (EVT_NOTIFY_SIGNAL, TPL_CALLBACK,\r
315	LegacyBiosInstalled, NULL /* Context */, &Event);\r
316	if (EFI_ERROR (Status)) {\r
317	return Status;\r
318	}\r
319	\r
320	Status = gBS->RegisterProtocolNotify (&gEfiLegacyBiosProtocolGuid, Event,\r
321	&Registration);\r
322	if (EFI_ERROR (Status)) {\r
323	goto CloseEvent;\r
324	}\r
325	\r
326	Status = gBS->SignalEvent (Event);\r
327	ASSERT_EFI_ERROR (Status);\r
328	\r
329	mIncompatiblePciDeviceSupport.CheckDevice = CheckDevice;\r
330	Status = gBS->InstallMultipleProtocolInterfaces (&ImageHandle,\r
331	&gEfiIncompatiblePciDeviceSupportProtocolGuid,\r
332	&mIncompatiblePciDeviceSupport, NULL);\r
333	if (EFI_ERROR (Status)) {\r
334	goto CloseEvent;\r
335	}\r
336	\r
337	return EFI_SUCCESS;\r
338	\r
339	CloseEvent:\r
340	if (!mLegacyBiosInstalled) {\r
341	EFI_STATUS CloseStatus;\r
342	\r
343	CloseStatus = gBS->CloseEvent (Event);\r
344	ASSERT_EFI_ERROR (CloseStatus);\r
345	}\r
346	\r
347	return Status;\r
348	}\r