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1 /** @file
2 A simple DXE_DRIVER that causes the PCI Bus UEFI_DRIVER to allocate 64-bit
3 MMIO BARs above 4 GB, regardless of option ROM availability (as long as a CSM
4 is not present), conserving 32-bit MMIO aperture for 32-bit BARs.
5
6 Copyright (C) 2016, Red Hat, Inc.
7 Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
8
9 SPDX-License-Identifier: BSD-2-Clause-Patent
10 **/
11
12 #include <IndustryStandard/Acpi10.h>
13 #include <IndustryStandard/Pci22.h>
14
15 #include <Library/DebugLib.h>
16 #include <Library/MemoryAllocationLib.h>
17 #include <Library/PcdLib.h>
18 #include <Library/UefiBootServicesTableLib.h>
19
20 #include <Protocol/IncompatiblePciDeviceSupport.h>
21 #include <Protocol/LegacyBios.h>
22
23 //
24 // The Legacy BIOS protocol has been located.
25 //
26 STATIC BOOLEAN mLegacyBiosInstalled;
27
28 //
29 // The protocol interface this driver produces.
30 //
31 STATIC EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL
32 mIncompatiblePciDeviceSupport;
33
34 //
35 // Configuration template for the CheckDevice() protocol member function.
36 //
37 // Refer to Table 20 "ACPI 2.0 & 3.0 QWORD Address Space Descriptor Usage" in
38 // the Platform Init 1.4a Spec, Volume 5.
39 //
40 // This structure is interpreted by the UpdatePciInfo() function in the edk2
41 // PCI Bus UEFI_DRIVER.
42 //
43 #pragma pack (1)
44 typedef struct {
45 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR AddressSpaceDesc;
46 EFI_ACPI_END_TAG_DESCRIPTOR EndDesc;
47 } MMIO64_PREFERENCE;
48 #pragma pack ()
49
50 STATIC CONST MMIO64_PREFERENCE mConfiguration = {
51 //
52 // AddressSpaceDesc
53 //
54 {
55 ACPI_ADDRESS_SPACE_DESCRIPTOR, // Desc
56 (UINT16)( // Len
57 sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) -
58 OFFSET_OF (
59 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR,
60 ResType
61 )
62 ),
63 ACPI_ADDRESS_SPACE_TYPE_MEM, // ResType
64 0, // GenFlag
65 0, // SpecificFlag
66 64, // AddrSpaceGranularity:
67 // aperture selection hint
68 // for BAR allocation
69 0, // AddrRangeMin
70 0, // AddrRangeMax:
71 // no special alignment
72 // for affected BARs
73 MAX_UINT64, // AddrTranslationOffset:
74 // hint covers all
75 // eligible BARs
76 0 // AddrLen:
77 // use probed BAR size
78 },
79 //
80 // EndDesc
81 //
82 {
83 ACPI_END_TAG_DESCRIPTOR, // Desc
84 0 // Checksum: to be ignored
85 }
86 };
87
88 //
89 // The CheckDevice() member function has been called.
90 //
91 STATIC BOOLEAN mCheckDeviceCalled;
92
93
94 /**
95 Notification callback for Legacy BIOS protocol installation.
96
97 @param[in] Event Event whose notification function is being invoked.
98
99 @param[in] Context The pointer to the notification function's context, which
100 is implementation-dependent.
101 **/
102 STATIC
103 VOID
104 EFIAPI
105 LegacyBiosInstalled (
106 IN EFI_EVENT Event,
107 IN VOID *Context
108 )
109 {
110 EFI_STATUS Status;
111 EFI_LEGACY_BIOS_PROTOCOL *LegacyBios;
112
113 ASSERT (!mCheckDeviceCalled);
114
115 Status = gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid,
116 NULL /* Registration */, (VOID **)&LegacyBios);
117 if (EFI_ERROR (Status)) {
118 return;
119 }
120
121 mLegacyBiosInstalled = TRUE;
122
123 //
124 // Close the event and deregister this callback.
125 //
126 Status = gBS->CloseEvent (Event);
127 ASSERT_EFI_ERROR (Status);
128 }
129
130
131 /**
132 Returns a list of ACPI resource descriptors that detail the special resource
133 configuration requirements for an incompatible PCI device.
134
135 Prior to bus enumeration, the PCI bus driver will look for the presence of
136 the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL. Only one instance of this
137 protocol can be present in the system. For each PCI device that the PCI bus
138 driver discovers, the PCI bus driver calls this function with the device's
139 vendor ID, device ID, revision ID, subsystem vendor ID, and subsystem device
140 ID. If the VendorId, DeviceId, RevisionId, SubsystemVendorId, or
141 SubsystemDeviceId value is set to (UINTN)-1, that field will be ignored. The
142 ID values that are not (UINTN)-1 will be used to identify the current device.
143
144 This function will only return EFI_SUCCESS. However, if the device is an
145 incompatible PCI device, a list of ACPI resource descriptors will be returned
146 in Configuration. Otherwise, NULL will be returned in Configuration instead.
147 The PCI bus driver does not need to allocate memory for Configuration.
148 However, it is the PCI bus driver's responsibility to free it. The PCI bus
149 driver then can configure this device with the information that is derived
150 from this list of resource nodes, rather than the result of BAR probing.
151
152 Only the following two resource descriptor types from the ACPI Specification
153 may be used to describe the incompatible PCI device resource requirements:
154 - QWORD Address Space Descriptor (ACPI 2.0, section 6.4.3.5.1; also ACPI 3.0)
155 - End Tag (ACPI 2.0, section 6.4.2.8; also ACPI 3.0)
156
157 The QWORD Address Space Descriptor can describe memory, I/O, and bus number
158 ranges for dynamic or fixed resources. The configuration of a PCI root bridge
159 is described with one or more QWORD Address Space Descriptors, followed by an
160 End Tag. See the ACPI Specification for details on the field values.
161
162 @param[in] This Pointer to the
163 EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL
164 instance.
165
166 @param[in] VendorId A unique ID to identify the manufacturer of
167 the PCI device. See the Conventional PCI
168 Specification 3.0 for details.
169
170 @param[in] DeviceId A unique ID to identify the particular PCI
171 device. See the Conventional PCI
172 Specification 3.0 for details.
173
174 @param[in] RevisionId A PCI device-specific revision identifier.
175 See the Conventional PCI Specification 3.0
176 for details.
177
178 @param[in] SubsystemVendorId Specifies the subsystem vendor ID. See the
179 Conventional PCI Specification 3.0 for
180 details.
181
182 @param[in] SubsystemDeviceId Specifies the subsystem device ID. See the
183 Conventional PCI Specification 3.0 for
184 details.
185
186 @param[out] Configuration A list of ACPI resource descriptors that
187 detail the configuration requirement.
188
189 @retval EFI_SUCCESS The function always returns EFI_SUCCESS.
190 **/
191 STATIC
192 EFI_STATUS
193 EFIAPI
194 CheckDevice (
195 IN EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *This,
196 IN UINTN VendorId,
197 IN UINTN DeviceId,
198 IN UINTN RevisionId,
199 IN UINTN SubsystemVendorId,
200 IN UINTN SubsystemDeviceId,
201 OUT VOID **Configuration
202 )
203 {
204 mCheckDeviceCalled = TRUE;
205
206 //
207 // Unlike the general description of this protocol member suggests, there is
208 // nothing incompatible about the PCI devices that we'll match here. We'll
209 // match all PCI devices, and generate exactly one QWORD Address Space
210 // Descriptor for each. That descriptor will instruct the PCI Bus UEFI_DRIVER
211 // not to degrade 64-bit MMIO BARs for the device, even if a PCI option ROM
212 // BAR is present on the device.
213 //
214 // The concern captured in the PCI Bus UEFI_DRIVER is that a legacy BIOS boot
215 // (via a CSM) could dispatch a legacy option ROM on the device, which might
216 // have trouble with MMIO BARs that have been allocated outside of the 32-bit
217 // address space. But, if we don't support legacy option ROMs at all, then
218 // this problem cannot arise.
219 //
220 if (mLegacyBiosInstalled) {
221 //
222 // Don't interfere with resource degradation.
223 //
224 *Configuration = NULL;
225 return EFI_SUCCESS;
226 }
227
228 //
229 // This member function is mis-specified actually: it is supposed to allocate
230 // memory, but as specified, it could not return an error status. Thankfully,
231 // the edk2 PCI Bus UEFI_DRIVER actually handles error codes; see the
232 // UpdatePciInfo() function.
233 //
234 *Configuration = AllocateCopyPool (sizeof mConfiguration, &mConfiguration);
235 if (*Configuration == NULL) {
236 DEBUG ((EFI_D_WARN,
237 "%a: 64-bit MMIO BARs may be degraded for PCI 0x%04x:0x%04x (rev %d)\n",
238 __FUNCTION__, (UINT32)VendorId, (UINT32)DeviceId, (UINT8)RevisionId));
239 return EFI_OUT_OF_RESOURCES;
240 }
241 return EFI_SUCCESS;
242 }
243
244
245 /**
246 Entry point for this driver.
247
248 @param[in] ImageHandle Image handle of this driver.
249 @param[in] SystemTable Pointer to SystemTable.
250
251 @retval EFI_SUCESS Driver has loaded successfully.
252 @retval EFI_UNSUPPORTED PCI resource allocation has been disabled.
253 @retval EFI_UNSUPPORTED There is no 64-bit PCI MMIO aperture.
254 @return Error codes from lower level functions.
255
256 **/
257 EFI_STATUS
258 EFIAPI
259 DriverInitialize (
260 IN EFI_HANDLE ImageHandle,
261 IN EFI_SYSTEM_TABLE *SystemTable
262 )
263 {
264 EFI_STATUS Status;
265 EFI_EVENT Event;
266 VOID *Registration;
267
268 //
269 // If the PCI Bus driver is not supposed to allocate resources, then it makes
270 // no sense to install a protocol that influences the resource allocation.
271 //
272 // Similarly, if there is no 64-bit PCI MMIO aperture, then 64-bit MMIO BARs
273 // have to be allocated under 4 GB unconditionally.
274 //
275 if (PcdGetBool (PcdPciDisableBusEnumeration) ||
276 PcdGet64 (PcdPciMmio64Size) == 0) {
277 return EFI_UNSUPPORTED;
278 }
279
280 //
281 // Otherwise, create a protocol notify to see if a CSM is present. (With the
282 // CSM absent, the PCI Bus driver won't have to worry about allocating 64-bit
283 // MMIO BARs in the 32-bit MMIO aperture, for the sake of a legacy BIOS.)
284 //
285 // If the Legacy BIOS Protocol is present at the time of this driver starting
286 // up, we can mark immediately that the PCI Bus driver should perform the
287 // usual 64-bit MMIO BAR degradation.
288 //
289 // Otherwise, if the Legacy BIOS Protocol is absent at startup, it may be
290 // installed later. However, if it doesn't show up until the first
291 // EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL.CheckDevice() call from the
292 // PCI Bus driver, then it never will:
293 //
294 // 1. The following drivers are dispatched in some unspecified order:
295 // - PCI Host Bridge DXE_DRIVER,
296 // - PCI Bus UEFI_DRIVER,
297 // - this DXE_DRIVER,
298 // - Legacy BIOS DXE_DRIVER.
299 //
300 // 2. The DXE_CORE enters BDS.
301 //
302 // 3. The platform BDS connects the PCI Root Bridge IO instances (produced by
303 // the PCI Host Bridge DXE_DRIVER).
304 //
305 // 4. The PCI Bus UEFI_DRIVER enumerates resources and calls into this
306 // DXE_DRIVER (CheckDevice()).
307 //
308 // 5. This driver remembers if EFI_LEGACY_BIOS_PROTOCOL has been installed
309 // sometime during step 1 (produced by the Legacy BIOS DXE_DRIVER).
310 //
311 // For breaking this order, the Legacy BIOS DXE_DRIVER would have to install
312 // its protocol after the firmware enters BDS, which cannot happen.
313 //
314 Status = gBS->CreateEvent (EVT_NOTIFY_SIGNAL, TPL_CALLBACK,
315 LegacyBiosInstalled, NULL /* Context */, &Event);
316 if (EFI_ERROR (Status)) {
317 return Status;
318 }
319
320 Status = gBS->RegisterProtocolNotify (&gEfiLegacyBiosProtocolGuid, Event,
321 &Registration);
322 if (EFI_ERROR (Status)) {
323 goto CloseEvent;
324 }
325
326 Status = gBS->SignalEvent (Event);
327 ASSERT_EFI_ERROR (Status);
328
329 mIncompatiblePciDeviceSupport.CheckDevice = CheckDevice;
330 Status = gBS->InstallMultipleProtocolInterfaces (&ImageHandle,
331 &gEfiIncompatiblePciDeviceSupportProtocolGuid,
332 &mIncompatiblePciDeviceSupport, NULL);
333 if (EFI_ERROR (Status)) {
334 goto CloseEvent;
335 }
336
337 return EFI_SUCCESS;
338
339 CloseEvent:
340 if (!mLegacyBiosInstalled) {
341 EFI_STATUS CloseStatus;
342
343 CloseStatus = gBS->CloseEvent (Event);
344 ASSERT_EFI_ERROR (CloseStatus);
345 }
346
347 return Status;
348 }