UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / OvmfPkg / Library / AcpiTimerLib / BaseRomAcpiTimerLib.c

/** @file\r
  Provide constructor and GetTick for BaseRom instance of ACPI Timer Library\r
\r
  Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.\r
  Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
**/\r
\r
#include <Library/DebugLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PciLib.h>\r
#include <OvmfPlatforms.h>\r
\r
/**\r
  The constructor function enables ACPI IO space.\r
\r
  If ACPI I/O space not enabled, this function will enable it.\r
  It will always return RETURN_SUCCESS.\r
\r
  @retval EFI_SUCCESS   The constructor always returns RETURN_SUCCESS.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
AcpiTimerLibConstructor (\r
  VOID\r
  )\r
{\r
  UINT16  HostBridgeDevId;\r
  UINTN   Pmba;\r
  UINT32  PmbaAndVal;\r
  UINT32  PmbaOrVal;\r
  UINTN   AcpiCtlReg;\r
  UINT8   AcpiEnBit;\r
\r
  //\r
  // Query Host Bridge DID to determine platform type\r
  //\r
  HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
  switch (HostBridgeDevId) {\r
    case INTEL_82441_DEVICE_ID:\r
      Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
      PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r
      PmbaOrVal  = PIIX4_PMBA_VALUE;\r
      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
      AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;\r
      break;\r
    case INTEL_Q35_MCH_DEVICE_ID:\r
      Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
      PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r
      PmbaOrVal  = ICH9_PMBASE_VALUE;\r
      AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
      AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;\r
      break;\r
    case CLOUDHV_DEVICE_ID:\r
      return RETURN_SUCCESS;\r
    default:\r
      DEBUG ((\r
        DEBUG_ERROR,\r
        "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
        __FUNCTION__,\r
        HostBridgeDevId\r
        ));\r
      ASSERT (FALSE);\r
      return RETURN_UNSUPPORTED;\r
  }\r
\r
  //\r
  // Check to see if the Power Management Base Address is already enabled\r
  //\r
  if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
    //\r
    // If the Power Management Base Address is not programmed,\r
    // then program it now.\r
    //\r
    PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r
\r
    //\r
    // Enable PMBA I/O port decodes\r
    //\r
    PciOr8 (AcpiCtlReg, AcpiEnBit);\r
  }\r
\r
  return RETURN_SUCCESS;\r
}\r
\r
/**\r
  Internal function to read the current tick counter of ACPI.\r
\r
  Dynamically compute the address of the ACPI tick counter based on the\r
  properties of the underlying platform, to avoid relying on global variables.\r
\r
  @return The tick counter read.\r
\r
**/\r
UINT32\r
InternalAcpiGetTimerTick (\r
  VOID\r
  )\r
{\r
  UINT16  HostBridgeDevId;\r
  UINTN   Pmba;\r
\r
  //\r
  // Query Host Bridge DID to determine platform type\r
  //\r
  HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
  switch (HostBridgeDevId) {\r
    case INTEL_82441_DEVICE_ID:\r
      Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
      break;\r
    case INTEL_Q35_MCH_DEVICE_ID:\r
      Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
      break;\r
    case CLOUDHV_DEVICE_ID:\r
      return IoRead32 (CLOUDHV_ACPI_TIMER_IO_ADDRESS);\r
    default:\r
      DEBUG ((\r
        DEBUG_ERROR,\r
        "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
        __FUNCTION__,\r
        HostBridgeDevId\r
        ));\r
      ASSERT (FALSE);\r
      return 0;\r
  }\r
\r
  //\r
  //   Read PMBA to read and return the current ACPI timer value.\r
  //\r
  return IoRead32 ((PciRead32 (Pmba) & ~PMBA_RTE) + ACPI_TIMER_OFFSET);\r
}\r