projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 86d71589 | 1 | /** @file\r |
| b1bfdd65 | 2 | The CPU specific programming for PiSmmCpuDxeSmm module.\r |
| 86d71589 | 3 | \r |
| b1bfdd65 | 4 | Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r |
| 86d71589 | 5 | \r |
| b26f0cf9 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 86d71589 PB |
7 | **/\r |
| 8 | \r | |
| 300aae11 | 9 | #include <IndustryStandard/Q35MchIch9.h>\r |
| 86d71589 | 10 | #include <Library/BaseLib.h>\r |
| 4036b4e5 | 11 | #include <Library/BaseMemoryLib.h>\r |
| 4a9b250b | 12 | #include <Library/DebugLib.h>\r |
| 5ef3b66f | 13 | #include <Library/MemEncryptSevLib.h>\r |
| 300aae11 | 14 | #include <Library/PcdLib.h>\r |
| 4a9b250b | 15 | #include <Library/SmmCpuFeaturesLib.h>\r |
| 4036b4e5 | 16 | #include <Library/SmmServicesTableLib.h>\r |
| 5ef3b66f | 17 | #include <Library/UefiBootServicesTableLib.h>\r |
| 4a9b250b | 18 | #include <PiSmm.h>\r |
| 300aae11 | 19 | #include <Register/Intel/SmramSaveStateMap.h>\r |
| c1fcd80b | 20 | #include <Register/QemuSmramSaveStateMap.h>\r |
| 86d71589 | 21 | \r |
| 4036b4e5 PB |
22 | //\r |
| 23 | // EFER register LMA bit\r | |
| 24 | //\r | |
| 25 | #define LMA BIT10\r | |
| 26 | \r | |
| 86d71589 PB |
27 | /**\r |
| 28 | The constructor function\r | |
| 29 | \r | |
| 30 | @param[in] ImageHandle The firmware allocated handle for the EFI image.\r | |
| 31 | @param[in] SystemTable A pointer to the EFI System Table.\r | |
| 32 | \r | |
| 33 | @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r | |
| 34 | \r | |
| 35 | **/\r | |
| 36 | EFI_STATUS\r | |
| 37 | EFIAPI\r | |
| 38 | SmmCpuFeaturesLibConstructor (\r | |
| 39 | IN EFI_HANDLE ImageHandle,\r | |
| 40 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
| 41 | )\r | |
| 42 | {\r | |
| 86d71589 | 43 | //\r |
| d7e71b29 | 44 | // No need to program SMRRs on our virtual platform.\r |
| 86d71589 | 45 | //\r |
| 86d71589 PB |
46 | return EFI_SUCCESS;\r |
| 47 | }\r | |
| 48 | \r | |
| 49 | /**\r | |
| 50 | Called during the very first SMI into System Management Mode to initialize\r | |
| 51 | CPU features, including SMBASE, for the currently executing CPU. Since this\r | |
| 52 | is the first SMI, the SMRAM Save State Map is at the default address of\r | |
| 53 | SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing\r | |
| 54 | CPU is specified by CpuIndex and CpuIndex can be used to access information\r | |
| 55 | about the currently executing CPU in the ProcessorInfo array and the\r | |
| 56 | HotPlugCpuData data structure.\r | |
| 57 | \r | |
| 58 | @param[in] CpuIndex The index of the CPU to initialize. The value\r | |
| 59 | must be between 0 and the NumberOfCpus field in\r | |
| 60 | the System Management System Table (SMST).\r | |
| 61 | @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that\r | |
| 62 | was elected as monarch during System Management\r | |
| 63 | Mode initialization.\r | |
| 64 | FALSE if the CpuIndex is not the index of the CPU\r | |
| 65 | that was elected as monarch during System\r | |
| 66 | Management Mode initialization.\r | |
| 67 | @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION\r | |
| 68 | structures. ProcessorInfo[CpuIndex] contains the\r | |
| 69 | information for the currently executing CPU.\r | |
| 70 | @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that\r | |
| 71 | contains the ApidId and SmBase arrays.\r | |
| 72 | **/\r | |
| 73 | VOID\r | |
| 74 | EFIAPI\r | |
| 75 | SmmCpuFeaturesInitializeProcessor (\r | |
| 76 | IN UINTN CpuIndex,\r | |
| 77 | IN BOOLEAN IsMonarch,\r | |
| 78 | IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,\r | |
| 79 | IN CPU_HOT_PLUG_DATA *CpuHotPlugData\r | |
| 80 | )\r | |
| 81 | {\r | |
| c1fcd80b | 82 | QEMU_SMRAM_SAVE_STATE_MAP *CpuState;\r |
| 86d71589 PB |
83 | \r |
| 84 | //\r | |
| 85 | // Configure SMBASE.\r | |
| 86 | //\r | |
| b1bfdd65 LE |
87 | CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(\r |
| 88 | SMM_DEFAULT_SMBASE +\r | |
| 89 | SMRAM_SAVE_STATE_MAP_OFFSET\r | |
| 90 | );\r | |
| c1fcd80b PB |
91 | if ((CpuState->x86.SMMRevId & 0xFFFF) == 0) {\r |
| 92 | CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r | |
| 93 | } else {\r | |
| 94 | CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r | |
| 95 | }\r | |
| 86d71589 PB |
96 | \r |
| 97 | //\r | |
| d7e71b29 | 98 | // No need to program SMRRs on our virtual platform.\r |
| 86d71589 | 99 | //\r |
| 86d71589 PB |
100 | }\r |
| 101 | \r | |
| 102 | /**\r | |
| 103 | This function updates the SMRAM save state on the currently executing CPU\r | |
| 104 | to resume execution at a specific address after an RSM instruction. This\r | |
| 105 | function must evaluate the SMRAM save state to determine the execution mode\r | |
| 106 | the RSM instruction resumes and update the resume execution address with\r | |
| 107 | either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart\r | |
| 108 | flag in the SMRAM save state must always be cleared. This function returns\r | |
| 109 | the value of the instruction pointer from the SMRAM save state that was\r | |
| 110 | replaced. If this function returns 0, then the SMRAM save state was not\r | |
| 111 | modified.\r | |
| 112 | \r | |
| 113 | This function is called during the very first SMI on each CPU after\r | |
| 114 | SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode\r | |
| 115 | to signal that the SMBASE of each CPU has been updated before the default\r | |
| 116 | SMBASE address is used for the first SMI to the next CPU.\r | |
| 117 | \r | |
| 118 | @param[in] CpuIndex The index of the CPU to hook. The value\r | |
| 119 | must be between 0 and the NumberOfCpus\r | |
| b1bfdd65 LE |
120 | field in the System Management System\r |
| 121 | Table (SMST).\r | |
| 86d71589 PB |
122 | @param[in] CpuState Pointer to SMRAM Save State Map for the\r |
| 123 | currently executing CPU.\r | |
| 124 | @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r | |
| 125 | 32-bit execution mode from 64-bit SMM.\r | |
| 126 | @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r | |
| 127 | same execution mode as SMM.\r | |
| 128 | \r | |
| 129 | @retval 0 This function did modify the SMRAM save state.\r | |
| 130 | @retval > 0 The original instruction pointer value from the SMRAM save state\r | |
| 131 | before it was replaced.\r | |
| 132 | **/\r | |
| 133 | UINT64\r | |
| 134 | EFIAPI\r | |
| 135 | SmmCpuFeaturesHookReturnFromSmm (\r | |
| 136 | IN UINTN CpuIndex,\r | |
| 137 | IN SMRAM_SAVE_STATE_MAP *CpuState,\r | |
| 138 | IN UINT64 NewInstructionPointer32,\r | |
| 139 | IN UINT64 NewInstructionPointer\r | |
| 140 | )\r | |
| 141 | {\r | |
| c1fcd80b | 142 | UINT64 OriginalInstructionPointer;\r |
| b1bfdd65 | 143 | QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r |
| 4036b4e5 | 144 | \r |
| b1bfdd65 | 145 | CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState;\r |
| 4036b4e5 PB |
146 | if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r |
| 147 | OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP;\r | |
| 148 | CpuSaveState->x86._EIP = (UINT32)NewInstructionPointer;\r | |
| 149 | //\r | |
| 150 | // Clear the auto HALT restart flag so the RSM instruction returns\r | |
| 151 | // program control to the instruction following the HLT instruction.\r | |
| 152 | //\r | |
| 153 | if ((CpuSaveState->x86.AutoHALTRestart & BIT0) != 0) {\r | |
| 154 | CpuSaveState->x86.AutoHALTRestart &= ~BIT0;\r | |
| 155 | }\r | |
| 156 | } else {\r | |
| 157 | OriginalInstructionPointer = CpuSaveState->x64._RIP;\r | |
| 158 | if ((CpuSaveState->x64.IA32_EFER & LMA) == 0) {\r | |
| 159 | CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer32;\r | |
| 160 | } else {\r | |
| 161 | CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer;\r | |
| 162 | }\r | |
| 163 | //\r | |
| 164 | // Clear the auto HALT restart flag so the RSM instruction returns\r | |
| 165 | // program control to the instruction following the HLT instruction.\r | |
| 166 | //\r | |
| 167 | if ((CpuSaveState->x64.AutoHALTRestart & BIT0) != 0) {\r | |
| 168 | CpuSaveState->x64.AutoHALTRestart &= ~BIT0;\r | |
| 169 | }\r | |
| 170 | }\r | |
| 171 | return OriginalInstructionPointer;\r | |
| 86d71589 PB |
172 | }\r |
| 173 | \r | |
| 174 | /**\r | |
| 175 | Hook point in normal execution mode that allows the one CPU that was elected\r | |
| 176 | as monarch during System Management Mode initialization to perform additional\r | |
| 177 | initialization actions immediately after all of the CPUs have processed their\r | |
| 178 | first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE\r | |
| 179 | into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().\r | |
| 180 | **/\r | |
| 181 | VOID\r | |
| 182 | EFIAPI\r | |
| 183 | SmmCpuFeaturesSmmRelocationComplete (\r | |
| 184 | VOID\r | |
| 185 | )\r | |
| 186 | {\r | |
| 5ef3b66f LE |
187 | EFI_STATUS Status;\r |
| 188 | UINTN MapPagesBase;\r | |
| 189 | UINTN MapPagesCount;\r | |
| 190 | \r | |
| 191 | if (!MemEncryptSevIsEnabled ()) {\r | |
| 192 | return;\r | |
| 193 | }\r | |
| 194 | \r | |
| 195 | //\r | |
| 196 | // Now that SMBASE relocation is complete, re-encrypt the original SMRAM save\r | |
| 197 | // state map's container pages, and release the pages to DXE. (The pages were\r | |
| 198 | // allocated in PlatformPei.)\r | |
| 199 | //\r | |
| 200 | Status = MemEncryptSevLocateInitialSmramSaveStateMapPages (\r | |
| 201 | &MapPagesBase,\r | |
| 202 | &MapPagesCount\r | |
| 203 | );\r | |
| 204 | ASSERT_EFI_ERROR (Status);\r | |
| 205 | \r | |
| 206 | Status = MemEncryptSevSetPageEncMask (\r | |
| 207 | 0, // Cr3BaseAddress -- use current CR3\r | |
| 208 | MapPagesBase, // BaseAddress\r | |
| 209 | MapPagesCount, // NumPages\r | |
| 210 | TRUE // Flush\r | |
| 211 | );\r | |
| 212 | if (EFI_ERROR (Status)) {\r | |
| 213 | DEBUG ((DEBUG_ERROR, "%a: MemEncryptSevSetPageEncMask(): %r\n",\r | |
| 214 | __FUNCTION__, Status));\r | |
| 215 | ASSERT (FALSE);\r | |
| 216 | CpuDeadLoop ();\r | |
| 217 | }\r | |
| 218 | \r | |
| 219 | ZeroMem ((VOID *)MapPagesBase, EFI_PAGES_TO_SIZE (MapPagesCount));\r | |
| 220 | \r | |
| 300aae11 LE |
221 | if (PcdGetBool (PcdQ35SmramAtDefaultSmbase)) {\r |
| 222 | //\r | |
| 223 | // The initial SMRAM Save State Map has been covered as part of a larger\r | |
| 224 | // reserved memory allocation in PlatformPei's InitializeRamRegions(). That\r | |
| 225 | // allocation is supposed to survive into OS runtime; we must not release\r | |
| 226 | // any part of it. Only re-assert the containment here.\r | |
| 227 | //\r | |
| 228 | ASSERT (SMM_DEFAULT_SMBASE <= MapPagesBase);\r | |
| 229 | ASSERT (\r | |
| 230 | (MapPagesBase + EFI_PAGES_TO_SIZE (MapPagesCount) <=\r | |
| 231 | SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE)\r | |
| 232 | );\r | |
| 233 | } else {\r | |
| 234 | Status = gBS->FreePages (MapPagesBase, MapPagesCount);\r | |
| 235 | ASSERT_EFI_ERROR (Status);\r | |
| 236 | }\r | |
| 86d71589 PB |
237 | }\r |
| 238 | \r | |
| 239 | /**\r | |
| 240 | Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is\r | |
| 241 | returned, then a custom SMI handler is not provided by this library,\r | |
| 242 | and the default SMI handler must be used.\r | |
| 243 | \r | |
| 244 | @retval 0 Use the default SMI handler.\r | |
| b1bfdd65 LE |
245 | @retval > 0 Use the SMI handler installed by\r |
| 246 | SmmCpuFeaturesInstallSmiHandler(). The caller is required to\r | |
| 247 | allocate enough SMRAM for each CPU to support the size of the\r | |
| 248 | custom SMI handler.\r | |
| 86d71589 PB |
249 | **/\r |
| 250 | UINTN\r | |
| 251 | EFIAPI\r | |
| 252 | SmmCpuFeaturesGetSmiHandlerSize (\r | |
| 253 | VOID\r | |
| 254 | )\r | |
| 255 | {\r | |
| 256 | return 0;\r | |
| 257 | }\r | |
| 258 | \r | |
| 259 | /**\r | |
| b1bfdd65 LE |
260 | Install a custom SMI handler for the CPU specified by CpuIndex. This\r |
| 261 | function is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size\r | |
| 262 | is greater than zero and is called by the CPU that was elected as monarch\r | |
| 263 | during System Management Mode initialization.\r | |
| 86d71589 PB |
264 | \r |
| 265 | @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r | |
| 266 | The value must be between 0 and the NumberOfCpus field\r | |
| 267 | in the System Management System Table (SMST).\r | |
| 268 | @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r | |
| 269 | @param[in] SmiStack The stack to use when an SMI is processed by the\r | |
| 270 | the CPU specified by CpuIndex.\r | |
| 271 | @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r | |
| 272 | processed by the CPU specified by CpuIndex.\r | |
| 273 | @param[in] GdtBase The base address of the GDT to use when an SMI is\r | |
| 274 | processed by the CPU specified by CpuIndex.\r | |
| 275 | @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r | |
| 276 | processed by the CPU specified by CpuIndex.\r | |
| 277 | @param[in] IdtBase The base address of the IDT to use when an SMI is\r | |
| 278 | processed by the CPU specified by CpuIndex.\r | |
| 279 | @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r | |
| 280 | processed by the CPU specified by CpuIndex.\r | |
| 281 | @param[in] Cr3 The base address of the page tables to use when an SMI\r | |
| 282 | is processed by the CPU specified by CpuIndex.\r | |
| 283 | **/\r | |
| 284 | VOID\r | |
| 285 | EFIAPI\r | |
| 286 | SmmCpuFeaturesInstallSmiHandler (\r | |
| 287 | IN UINTN CpuIndex,\r | |
| 288 | IN UINT32 SmBase,\r | |
| 289 | IN VOID *SmiStack,\r | |
| 290 | IN UINTN StackSize,\r | |
| 291 | IN UINTN GdtBase,\r | |
| 292 | IN UINTN GdtSize,\r | |
| 293 | IN UINTN IdtBase,\r | |
| 294 | IN UINTN IdtSize,\r | |
| 295 | IN UINT32 Cr3\r | |
| 296 | )\r | |
| 297 | {\r | |
| 298 | }\r | |
| 299 | \r | |
| 300 | /**\r | |
| 301 | Determines if MTRR registers must be configured to set SMRAM cache-ability\r | |
| 302 | when executing in System Management Mode.\r | |
| 303 | \r | |
| 304 | @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.\r | |
| 305 | @retval FALSE MTRR registers do not need to be configured to set SMRAM\r | |
| 306 | cache-ability.\r | |
| 307 | **/\r | |
| 308 | BOOLEAN\r | |
| 309 | EFIAPI\r | |
| 310 | SmmCpuFeaturesNeedConfigureMtrrs (\r | |
| 311 | VOID\r | |
| 312 | )\r | |
| 313 | {\r | |
| d7e71b29 | 314 | return FALSE;\r |
| 86d71589 PB |
315 | }\r |
| 316 | \r | |
| 317 | /**\r | |
| b1bfdd65 LE |
318 | Disable SMRR register if SMRR is supported and\r |
| 319 | SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.\r | |
| 86d71589 PB |
320 | **/\r |
| 321 | VOID\r | |
| 322 | EFIAPI\r | |
| 323 | SmmCpuFeaturesDisableSmrr (\r | |
| 324 | VOID\r | |
| 325 | )\r | |
| 326 | {\r | |
| d7e71b29 PB |
327 | //\r |
| 328 | // No SMRR support, nothing to do\r | |
| 329 | //\r | |
| 86d71589 PB |
330 | }\r |
| 331 | \r | |
| 332 | /**\r | |
| b1bfdd65 LE |
333 | Enable SMRR register if SMRR is supported and\r |
| 334 | SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.\r | |
| 86d71589 PB |
335 | **/\r |
| 336 | VOID\r | |
| 337 | EFIAPI\r | |
| 338 | SmmCpuFeaturesReenableSmrr (\r | |
| 339 | VOID\r | |
| 340 | )\r | |
| 341 | {\r | |
| d7e71b29 PB |
342 | //\r |
| 343 | // No SMRR support, nothing to do\r | |
| 344 | //\r | |
| 86d71589 PB |
345 | }\r |
| 346 | \r | |
| 347 | /**\r | |
| 348 | Processor specific hook point each time a CPU enters System Management Mode.\r | |
| 349 | \r | |
| 350 | @param[in] CpuIndex The index of the CPU that has entered SMM. The value\r | |
| 351 | must be between 0 and the NumberOfCpus field in the\r | |
| 352 | System Management System Table (SMST).\r | |
| 353 | **/\r | |
| 354 | VOID\r | |
| 355 | EFIAPI\r | |
| 356 | SmmCpuFeaturesRendezvousEntry (\r | |
| 357 | IN UINTN CpuIndex\r | |
| 358 | )\r | |
| 359 | {\r | |
| 360 | //\r | |
| d7e71b29 | 361 | // No SMRR support, nothing to do\r |
| 86d71589 | 362 | //\r |
| 86d71589 PB |
363 | }\r |
| 364 | \r | |
| 365 | /**\r | |
| 366 | Processor specific hook point each time a CPU exits System Management Mode.\r | |
| 367 | \r | |
| b1bfdd65 LE |
368 | @param[in] CpuIndex The index of the CPU that is exiting SMM. The value\r |
| 369 | must be between 0 and the NumberOfCpus field in the\r | |
| 370 | System Management System Table (SMST).\r | |
| 86d71589 PB |
371 | **/\r |
| 372 | VOID\r | |
| 373 | EFIAPI\r | |
| 374 | SmmCpuFeaturesRendezvousExit (\r | |
| 375 | IN UINTN CpuIndex\r | |
| 376 | )\r | |
| 377 | {\r | |
| 378 | }\r | |
| 379 | \r | |
| 380 | /**\r | |
| 381 | Check to see if an SMM register is supported by a specified CPU.\r | |
| 382 | \r | |
| 383 | @param[in] CpuIndex The index of the CPU to check for SMM register support.\r | |
| 384 | The value must be between 0 and the NumberOfCpus field\r | |
| 385 | in the System Management System Table (SMST).\r | |
| 386 | @param[in] RegName Identifies the SMM register to check for support.\r | |
| 387 | \r | |
| 388 | @retval TRUE The SMM register specified by RegName is supported by the CPU\r | |
| 389 | specified by CpuIndex.\r | |
| 390 | @retval FALSE The SMM register specified by RegName is not supported by the\r | |
| 391 | CPU specified by CpuIndex.\r | |
| 392 | **/\r | |
| 393 | BOOLEAN\r | |
| 394 | EFIAPI\r | |
| 395 | SmmCpuFeaturesIsSmmRegisterSupported (\r | |
| 396 | IN UINTN CpuIndex,\r | |
| 397 | IN SMM_REG_NAME RegName\r | |
| 398 | )\r | |
| 399 | {\r | |
| d7e71b29 | 400 | ASSERT (RegName == SmmRegFeatureControl);\r |
| 86d71589 PB |
401 | return FALSE;\r |
| 402 | }\r | |
| 403 | \r | |
| 404 | /**\r | |
| 405 | Returns the current value of the SMM register for the specified CPU.\r | |
| 406 | If the SMM register is not supported, then 0 is returned.\r | |
| 407 | \r | |
| 408 | @param[in] CpuIndex The index of the CPU to read the SMM register. The\r | |
| 409 | value must be between 0 and the NumberOfCpus field in\r | |
| 410 | the System Management System Table (SMST).\r | |
| 411 | @param[in] RegName Identifies the SMM register to read.\r | |
| 412 | \r | |
| 413 | @return The value of the SMM register specified by RegName from the CPU\r | |
| 414 | specified by CpuIndex.\r | |
| 415 | **/\r | |
| 416 | UINT64\r | |
| 417 | EFIAPI\r | |
| 418 | SmmCpuFeaturesGetSmmRegister (\r | |
| 419 | IN UINTN CpuIndex,\r | |
| 420 | IN SMM_REG_NAME RegName\r | |
| 421 | )\r | |
| 422 | {\r | |
| d7e71b29 PB |
423 | //\r |
| 424 | // This is called for SmmRegSmmDelayed, SmmRegSmmBlocked, SmmRegSmmEnable.\r | |
| 425 | // The last of these should actually be SmmRegSmmDisable, so we can just\r | |
| 426 | // return FALSE.\r | |
| 427 | //\r | |
| 86d71589 PB |
428 | return 0;\r |
| 429 | }\r | |
| 430 | \r | |
| 431 | /**\r | |
| 432 | Sets the value of an SMM register on a specified CPU.\r | |
| 433 | If the SMM register is not supported, then no action is performed.\r | |
| 434 | \r | |
| 435 | @param[in] CpuIndex The index of the CPU to write the SMM register. The\r | |
| 436 | value must be between 0 and the NumberOfCpus field in\r | |
| 437 | the System Management System Table (SMST).\r | |
| 438 | @param[in] RegName Identifies the SMM register to write.\r | |
| 439 | registers are read-only.\r | |
| 440 | @param[in] Value The value to write to the SMM register.\r | |
| 441 | **/\r | |
| 442 | VOID\r | |
| 443 | EFIAPI\r | |
| 444 | SmmCpuFeaturesSetSmmRegister (\r | |
| 445 | IN UINTN CpuIndex,\r | |
| 446 | IN SMM_REG_NAME RegName,\r | |
| 447 | IN UINT64 Value\r | |
| 448 | )\r | |
| 449 | {\r | |
| d7e71b29 | 450 | ASSERT (FALSE);\r |
| 86d71589 PB |
451 | }\r |
| 452 | \r | |
| 4036b4e5 | 453 | ///\r |
| b1bfdd65 LE |
454 | /// Macro used to simplify the lookup table entries of type\r |
| 455 | /// CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r | |
| 4036b4e5 | 456 | ///\r |
| c1fcd80b | 457 | #define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)\r |
| 4036b4e5 PB |
458 | \r |
| 459 | ///\r | |
| b1bfdd65 LE |
460 | /// Macro used to simplify the lookup table entries of type\r |
| 461 | /// CPU_SMM_SAVE_STATE_REGISTER_RANGE\r | |
| 4036b4e5 PB |
462 | ///\r |
| 463 | #define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }\r | |
| 464 | \r | |
| 465 | ///\r | |
| 466 | /// Structure used to describe a range of registers\r | |
| 467 | ///\r | |
| 468 | typedef struct {\r | |
| 469 | EFI_SMM_SAVE_STATE_REGISTER Start;\r | |
| 470 | EFI_SMM_SAVE_STATE_REGISTER End;\r | |
| 471 | UINTN Length;\r | |
| 472 | } CPU_SMM_SAVE_STATE_REGISTER_RANGE;\r | |
| 473 | \r | |
| 474 | ///\r | |
| 475 | /// Structure used to build a lookup table to retrieve the widths and offsets\r | |
| 476 | /// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value\r | |
| 477 | ///\r | |
| 478 | \r | |
| 479 | #define SMM_SAVE_STATE_REGISTER_FIRST_INDEX 1\r | |
| 480 | \r | |
| 481 | typedef struct {\r | |
| 482 | UINT8 Width32;\r | |
| 483 | UINT8 Width64;\r | |
| 484 | UINT16 Offset32;\r | |
| 485 | UINT16 Offset64Lo;\r | |
| 486 | UINT16 Offset64Hi;\r | |
| 487 | BOOLEAN Writeable;\r | |
| 488 | } CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;\r | |
| 489 | \r | |
| 490 | ///\r | |
| b1bfdd65 | 491 | /// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER\r |
| 4036b4e5 PB |
492 | /// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r |
| 493 | ///\r | |
| ea992760 | 494 | STATIC CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {\r |
| b1bfdd65 LE |
495 | SMM_REGISTER_RANGE (\r |
| 496 | EFI_SMM_SAVE_STATE_REGISTER_GDTBASE,\r | |
| 497 | EFI_SMM_SAVE_STATE_REGISTER_LDTINFO\r | |
| 498 | ),\r | |
| 499 | SMM_REGISTER_RANGE (\r | |
| 500 | EFI_SMM_SAVE_STATE_REGISTER_ES,\r | |
| 501 | EFI_SMM_SAVE_STATE_REGISTER_RIP\r | |
| 502 | ),\r | |
| 503 | SMM_REGISTER_RANGE (\r | |
| 504 | EFI_SMM_SAVE_STATE_REGISTER_RFLAGS,\r | |
| 505 | EFI_SMM_SAVE_STATE_REGISTER_CR4\r | |
| 506 | ),\r | |
| 4036b4e5 PB |
507 | { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }\r |
| 508 | };\r | |
| 509 | \r | |
| 510 | ///\r | |
| b1bfdd65 LE |
511 | /// Lookup table used to retrieve the widths and offsets associated with each\r |
| 512 | /// supported EFI_SMM_SAVE_STATE_REGISTER value\r | |
| 4036b4e5 | 513 | ///\r |
| ea992760 | 514 | STATIC CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {\r |
| b1bfdd65 LE |
515 | {\r |
| 516 | 0, // Width32\r | |
| 517 | 0, // Width64\r | |
| 518 | 0, // Offset32\r | |
| 519 | 0, // Offset64Lo\r | |
| 520 | 0, // Offset64Hi\r | |
| 521 | FALSE // Writeable\r | |
| 522 | }, // Reserved\r | |
| 4036b4e5 PB |
523 | \r |
| 524 | //\r | |
| 525 | // CPU Save State registers defined in PI SMM CPU Protocol.\r | |
| 526 | //\r | |
| b1bfdd65 LE |
527 | {\r |
| 528 | 0, // Width32\r | |
| 529 | 8, // Width64\r | |
| 530 | 0, // Offset32\r | |
| 531 | SMM_CPU_OFFSET (x64._GDTRBase), // Offset64Lo\r | |
| 532 | SMM_CPU_OFFSET (x64._GDTRBase) + 4, // Offset64Hi\r | |
| 533 | FALSE // Writeable\r | |
| 534 | }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4\r | |
| 535 | \r | |
| 536 | {\r | |
| 537 | 0, // Width32\r | |
| 538 | 8, // Width64\r | |
| 539 | 0, // Offset32\r | |
| 540 | SMM_CPU_OFFSET (x64._IDTRBase), // Offset64Lo\r | |
| 541 | SMM_CPU_OFFSET (x64._IDTRBase) + 4, // Offset64Hi\r | |
| 542 | FALSE // Writeable\r | |
| 543 | }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5\r | |
| 544 | \r | |
| 545 | {\r | |
| 546 | 0, // Width32\r | |
| 547 | 8, // Width64\r | |
| 548 | 0, // Offset32\r | |
| 549 | SMM_CPU_OFFSET (x64._LDTRBase), // Offset64Lo\r | |
| 550 | SMM_CPU_OFFSET (x64._LDTRBase) + 4, // Offset64Hi\r | |
| 551 | FALSE // Writeable\r | |
| 552 | }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6\r | |
| 553 | \r | |
| 554 | {\r | |
| 555 | 0, // Width32\r | |
| 556 | 0, // Width64\r | |
| 557 | 0, // Offset32\r | |
| 558 | SMM_CPU_OFFSET (x64._GDTRLimit), // Offset64Lo\r | |
| 559 | SMM_CPU_OFFSET (x64._GDTRLimit) + 4, // Offset64Hi\r | |
| 560 | FALSE // Writeable\r | |
| 561 | }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7\r | |
| 562 | \r | |
| 563 | {\r | |
| 564 | 0, // Width32\r | |
| 565 | 0, // Width64\r | |
| 566 | 0, // Offset32\r | |
| 567 | SMM_CPU_OFFSET (x64._IDTRLimit), // Offset64Lo\r | |
| 568 | SMM_CPU_OFFSET (x64._IDTRLimit) + 4, // Offset64Hi\r | |
| 569 | FALSE // Writeable\r | |
| 570 | }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8\r | |
| 571 | \r | |
| 572 | {\r | |
| 573 | 0, // Width32\r | |
| 574 | 0, // Width64\r | |
| 575 | 0, // Offset32\r | |
| 576 | SMM_CPU_OFFSET (x64._LDTRLimit), // Offset64Lo\r | |
| 577 | SMM_CPU_OFFSET (x64._LDTRLimit) + 4, // Offset64Hi\r | |
| 578 | FALSE // Writeable\r | |
| 579 | }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9\r | |
| 580 | \r | |
| 581 | {\r | |
| 582 | 0, // Width32\r | |
| 583 | 0, // Width64\r | |
| 584 | 0, // Offset32\r | |
| 585 | 0, // Offset64Lo\r | |
| 586 | 0 + 4, // Offset64Hi\r | |
| 587 | FALSE // Writeable\r | |
| 588 | }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10\r | |
| 589 | \r | |
| 590 | {\r | |
| 591 | 4, // Width32\r | |
| 592 | 4, // Width64\r | |
| 593 | SMM_CPU_OFFSET (x86._ES), // Offset32\r | |
| 594 | SMM_CPU_OFFSET (x64._ES), // Offset64Lo\r | |
| 595 | 0, // Offset64Hi\r | |
| 596 | FALSE // Writeable\r | |
| 597 | }, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20\r | |
| 598 | \r | |
| 599 | {\r | |
| 600 | 4, // Width32\r | |
| 601 | 4, // Width64\r | |
| 602 | SMM_CPU_OFFSET (x86._CS), // Offset32\r | |
| 603 | SMM_CPU_OFFSET (x64._CS), // Offset64Lo\r | |
| 604 | 0, // Offset64Hi\r | |
| 605 | FALSE // Writeable\r | |
| 606 | }, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21\r | |
| 607 | \r | |
| 608 | {\r | |
| 609 | 4, // Width32\r | |
| 610 | 4, // Width64\r | |
| 611 | SMM_CPU_OFFSET (x86._SS), // Offset32\r | |
| 612 | SMM_CPU_OFFSET (x64._SS), // Offset64Lo\r | |
| 613 | 0, // Offset64Hi\r | |
| 614 | FALSE // Writeable\r | |
| 615 | }, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22\r | |
| 616 | \r | |
| 617 | {\r | |
| 618 | 4, // Width32\r | |
| 619 | 4, // Width64\r | |
| 620 | SMM_CPU_OFFSET (x86._DS), // Offset32\r | |
| 621 | SMM_CPU_OFFSET (x64._DS), // Offset64Lo\r | |
| 622 | 0, // Offset64Hi\r | |
| 623 | FALSE // Writeable\r | |
| 624 | }, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23\r | |
| 625 | \r | |
| 626 | {\r | |
| 627 | 4, // Width32\r | |
| 628 | 4, // Width64\r | |
| 629 | SMM_CPU_OFFSET (x86._FS), // Offset32\r | |
| 630 | SMM_CPU_OFFSET (x64._FS), // Offset64Lo\r | |
| 631 | 0, // Offset64Hi\r | |
| 632 | FALSE // Writeable\r | |
| 633 | }, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24\r | |
| 634 | \r | |
| 635 | {\r | |
| 636 | 4, // Width32\r | |
| 637 | 4, // Width64\r | |
| 638 | SMM_CPU_OFFSET (x86._GS), // Offset32\r | |
| 639 | SMM_CPU_OFFSET (x64._GS), // Offset64Lo\r | |
| 640 | 0, // Offset64Hi\r | |
| 641 | FALSE // Writeable\r | |
| 642 | }, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25\r | |
| 643 | \r | |
| 644 | {\r | |
| 645 | 0, // Width32\r | |
| 646 | 4, // Width64\r | |
| 647 | 0, // Offset32\r | |
| 648 | SMM_CPU_OFFSET (x64._LDTR), // Offset64Lo\r | |
| 649 | 0, // Offset64Hi\r | |
| 650 | FALSE // Writeable\r | |
| 651 | }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26\r | |
| 652 | \r | |
| 653 | {\r | |
| 654 | 4, // Width32\r | |
| 655 | 4, // Width64\r | |
| 656 | SMM_CPU_OFFSET (x86._TR), // Offset32\r | |
| 657 | SMM_CPU_OFFSET (x64._TR), // Offset64Lo\r | |
| 658 | 0, // Offset64Hi\r | |
| 659 | FALSE // Writeable\r | |
| 660 | }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27\r | |
| 661 | \r | |
| 662 | {\r | |
| 663 | 4, // Width32\r | |
| 664 | 8, // Width64\r | |
| 665 | SMM_CPU_OFFSET (x86._DR7), // Offset32\r | |
| 666 | SMM_CPU_OFFSET (x64._DR7), // Offset64Lo\r | |
| 667 | SMM_CPU_OFFSET (x64._DR7) + 4, // Offset64Hi\r | |
| 668 | FALSE // Writeable\r | |
| 669 | }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28\r | |
| 670 | \r | |
| 671 | {\r | |
| 672 | 4, // Width32\r | |
| 673 | 8, // Width64\r | |
| 674 | SMM_CPU_OFFSET (x86._DR6), // Offset32\r | |
| 675 | SMM_CPU_OFFSET (x64._DR6), // Offset64Lo\r | |
| 676 | SMM_CPU_OFFSET (x64._DR6) + 4, // Offset64Hi\r | |
| 677 | FALSE // Writeable\r | |
| 678 | }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29\r | |
| 679 | \r | |
| 680 | {\r | |
| 681 | 0, // Width32\r | |
| 682 | 8, // Width64\r | |
| 683 | 0, // Offset32\r | |
| 684 | SMM_CPU_OFFSET (x64._R8), // Offset64Lo\r | |
| 685 | SMM_CPU_OFFSET (x64._R8) + 4, // Offset64Hi\r | |
| 686 | TRUE // Writeable\r | |
| 687 | }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30\r | |
| 688 | \r | |
| 689 | {\r | |
| 690 | 0, // Width32\r | |
| 691 | 8, // Width64\r | |
| 692 | 0, // Offset32\r | |
| 693 | SMM_CPU_OFFSET (x64._R9), // Offset64Lo\r | |
| 694 | SMM_CPU_OFFSET (x64._R9) + 4, // Offset64Hi\r | |
| 695 | TRUE // Writeable\r | |
| 696 | }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31\r | |
| 697 | \r | |
| 698 | {\r | |
| 699 | 0, // Width32\r | |
| 700 | 8, // Width64\r | |
| 701 | 0, // Offset32\r | |
| 702 | SMM_CPU_OFFSET (x64._R10), // Offset64Lo\r | |
| 703 | SMM_CPU_OFFSET (x64._R10) + 4, // Offset64Hi\r | |
| 704 | TRUE // Writeable\r | |
| 705 | }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32\r | |
| 706 | \r | |
| 707 | {\r | |
| 708 | 0, // Width32\r | |
| 709 | 8, // Width64\r | |
| 710 | 0, // Offset32\r | |
| 711 | SMM_CPU_OFFSET (x64._R11), // Offset64Lo\r | |
| 712 | SMM_CPU_OFFSET (x64._R11) + 4, // Offset64Hi\r | |
| 713 | TRUE // Writeable\r | |
| 714 | }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33\r | |
| 715 | \r | |
| 716 | {\r | |
| 717 | 0, // Width32\r | |
| 718 | 8, // Width64\r | |
| 719 | 0, // Offset32\r | |
| 720 | SMM_CPU_OFFSET (x64._R12), // Offset64Lo\r | |
| 721 | SMM_CPU_OFFSET (x64._R12) + 4, // Offset64Hi\r | |
| 722 | TRUE // Writeable\r | |
| 723 | }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34\r | |
| 724 | \r | |
| 725 | {\r | |
| 726 | 0, // Width32\r | |
| 727 | 8, // Width64\r | |
| 728 | 0, // Offset32\r | |
| 729 | SMM_CPU_OFFSET (x64._R13), // Offset64Lo\r | |
| 730 | SMM_CPU_OFFSET (x64._R13) + 4, // Offset64Hi\r | |
| 731 | TRUE // Writeable\r | |
| 732 | }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35\r | |
| 733 | \r | |
| 734 | {\r | |
| 735 | 0, // Width32\r | |
| 736 | 8, // Width64\r | |
| 737 | 0, // Offset32\r | |
| 738 | SMM_CPU_OFFSET (x64._R14), // Offset64Lo\r | |
| 739 | SMM_CPU_OFFSET (x64._R14) + 4, // Offset64Hi\r | |
| 740 | TRUE // Writeable\r | |
| 741 | }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36\r | |
| 742 | \r | |
| 743 | {\r | |
| 744 | 0, // Width32\r | |
| 745 | 8, // Width64\r | |
| 746 | 0, // Offset32\r | |
| 747 | SMM_CPU_OFFSET (x64._R15), // Offset64Lo\r | |
| 748 | SMM_CPU_OFFSET (x64._R15) + 4, // Offset64Hi\r | |
| 749 | TRUE // Writeable\r | |
| 750 | }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37\r | |
| 751 | \r | |
| 752 | {\r | |
| 753 | 4, // Width32\r | |
| 754 | 8, // Width64\r | |
| 755 | SMM_CPU_OFFSET (x86._EAX), // Offset32\r | |
| 756 | SMM_CPU_OFFSET (x64._RAX), // Offset64Lo\r | |
| 757 | SMM_CPU_OFFSET (x64._RAX) + 4, // Offset64Hi\r | |
| 758 | TRUE // Writeable\r | |
| 759 | }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38\r | |
| 760 | \r | |
| 761 | {\r | |
| 762 | 4, // Width32\r | |
| 763 | 8, // Width64\r | |
| 764 | SMM_CPU_OFFSET (x86._EBX), // Offset32\r | |
| 765 | SMM_CPU_OFFSET (x64._RBX), // Offset64Lo\r | |
| 766 | SMM_CPU_OFFSET (x64._RBX) + 4, // Offset64Hi\r | |
| 767 | TRUE // Writeable\r | |
| 768 | }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39\r | |
| 769 | \r | |
| 770 | {\r | |
| 771 | 4, // Width32\r | |
| 772 | 8, // Width64\r | |
| 773 | SMM_CPU_OFFSET (x86._ECX), // Offset32\r | |
| 774 | SMM_CPU_OFFSET (x64._RCX), // Offset64Lo\r | |
| 775 | SMM_CPU_OFFSET (x64._RCX) + 4, // Offset64Hi\r | |
| 776 | TRUE // Writeable\r | |
| 777 | }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40\r | |
| 778 | \r | |
| 779 | {\r | |
| 780 | 4, // Width32\r | |
| 781 | 8, // Width64\r | |
| 782 | SMM_CPU_OFFSET (x86._EDX), // Offset32\r | |
| 783 | SMM_CPU_OFFSET (x64._RDX), // Offset64Lo\r | |
| 784 | SMM_CPU_OFFSET (x64._RDX) + 4, // Offset64Hi\r | |
| 785 | TRUE // Writeable\r | |
| 786 | }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41\r | |
| 787 | \r | |
| 788 | {\r | |
| 789 | 4, // Width32\r | |
| 790 | 8, // Width64\r | |
| 791 | SMM_CPU_OFFSET (x86._ESP), // Offset32\r | |
| 792 | SMM_CPU_OFFSET (x64._RSP), // Offset64Lo\r | |
| 793 | SMM_CPU_OFFSET (x64._RSP) + 4, // Offset64Hi\r | |
| 794 | TRUE // Writeable\r | |
| 795 | }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42\r | |
| 796 | \r | |
| 797 | {\r | |
| 798 | 4, // Width32\r | |
| 799 | 8, // Width64\r | |
| 800 | SMM_CPU_OFFSET (x86._EBP), // Offset32\r | |
| 801 | SMM_CPU_OFFSET (x64._RBP), // Offset64Lo\r | |
| 802 | SMM_CPU_OFFSET (x64._RBP) + 4, // Offset64Hi\r | |
| 803 | TRUE // Writeable\r | |
| 804 | }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43\r | |
| 805 | \r | |
| 806 | {\r | |
| 807 | 4, // Width32\r | |
| 808 | 8, // Width64\r | |
| 809 | SMM_CPU_OFFSET (x86._ESI), // Offset32\r | |
| 810 | SMM_CPU_OFFSET (x64._RSI), // Offset64Lo\r | |
| 811 | SMM_CPU_OFFSET (x64._RSI) + 4, // Offset64Hi\r | |
| 812 | TRUE // Writeable\r | |
| 813 | }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44\r | |
| 814 | \r | |
| 815 | {\r | |
| 816 | 4, // Width32\r | |
| 817 | 8, // Width64\r | |
| 818 | SMM_CPU_OFFSET (x86._EDI), // Offset32\r | |
| 819 | SMM_CPU_OFFSET (x64._RDI), // Offset64Lo\r | |
| 820 | SMM_CPU_OFFSET (x64._RDI) + 4, // Offset64Hi\r | |
| 821 | TRUE // Writeable\r | |
| 822 | }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45\r | |
| 823 | \r | |
| 824 | {\r | |
| 825 | 4, // Width32\r | |
| 826 | 8, // Width64\r | |
| 827 | SMM_CPU_OFFSET (x86._EIP), // Offset32\r | |
| 828 | SMM_CPU_OFFSET (x64._RIP), // Offset64Lo\r | |
| 829 | SMM_CPU_OFFSET (x64._RIP) + 4, // Offset64Hi\r | |
| 830 | TRUE // Writeable\r | |
| 831 | }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46\r | |
| 832 | \r | |
| 833 | {\r | |
| 834 | 4, // Width32\r | |
| 835 | 8, // Width64\r | |
| 836 | SMM_CPU_OFFSET (x86._EFLAGS), // Offset32\r | |
| 837 | SMM_CPU_OFFSET (x64._RFLAGS), // Offset64Lo\r | |
| 838 | SMM_CPU_OFFSET (x64._RFLAGS) + 4, // Offset64Hi\r | |
| 839 | TRUE // Writeable\r | |
| 840 | }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51\r | |
| 841 | \r | |
| 842 | {\r | |
| 843 | 4, // Width32\r | |
| 844 | 8, // Width64\r | |
| 845 | SMM_CPU_OFFSET (x86._CR0), // Offset32\r | |
| 846 | SMM_CPU_OFFSET (x64._CR0), // Offset64Lo\r | |
| 847 | SMM_CPU_OFFSET (x64._CR0) + 4, // Offset64Hi\r | |
| 848 | FALSE // Writeable\r | |
| 849 | }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52\r | |
| 850 | \r | |
| 851 | {\r | |
| 852 | 4, // Width32\r | |
| 853 | 8, // Width64\r | |
| 854 | SMM_CPU_OFFSET (x86._CR3), // Offset32\r | |
| 855 | SMM_CPU_OFFSET (x64._CR3), // Offset64Lo\r | |
| 856 | SMM_CPU_OFFSET (x64._CR3) + 4, // Offset64Hi\r | |
| 857 | FALSE // Writeable\r | |
| 858 | }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53\r | |
| 859 | \r | |
| 860 | {\r | |
| 861 | 0, // Width32\r | |
| 862 | 4, // Width64\r | |
| 863 | 0, // Offset32\r | |
| 864 | SMM_CPU_OFFSET (x64._CR4), // Offset64Lo\r | |
| 865 | SMM_CPU_OFFSET (x64._CR4) + 4, // Offset64Hi\r | |
| 866 | FALSE // Writeable\r | |
| 867 | }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54\r | |
| 4036b4e5 PB |
868 | };\r |
| 869 | \r | |
| 870 | //\r | |
| 871 | // No support for I/O restart\r | |
| 872 | //\r | |
| 873 | \r | |
| 874 | /**\r | |
| 875 | Read information from the CPU save state.\r | |
| 876 | \r | |
| 877 | @param Register Specifies the CPU register to read form the save state.\r | |
| 878 | \r | |
| 879 | @retval 0 Register is not valid\r | |
| 880 | @retval >0 Index into mSmmCpuWidthOffset[] associated with Register\r | |
| 881 | \r | |
| 882 | **/\r | |
| ea992760 LE |
883 | STATIC\r |
| 884 | UINTN\r | |
| 4036b4e5 PB |
885 | GetRegisterIndex (\r |
| 886 | IN EFI_SMM_SAVE_STATE_REGISTER Register\r | |
| 887 | )\r | |
| 888 | {\r | |
| 889 | UINTN Index;\r | |
| 890 | UINTN Offset;\r | |
| 891 | \r | |
| b1bfdd65 LE |
892 | for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX;\r |
| 893 | mSmmCpuRegisterRanges[Index].Length != 0;\r | |
| 894 | Index++) {\r | |
| 895 | if (Register >= mSmmCpuRegisterRanges[Index].Start &&\r | |
| 896 | Register <= mSmmCpuRegisterRanges[Index].End) {\r | |
| 4036b4e5 PB |
897 | return Register - mSmmCpuRegisterRanges[Index].Start + Offset;\r |
| 898 | }\r | |
| 899 | Offset += mSmmCpuRegisterRanges[Index].Length;\r | |
| 900 | }\r | |
| 901 | return 0;\r | |
| 902 | }\r | |
| 903 | \r | |
| 904 | /**\r | |
| 905 | Read a CPU Save State register on the target processor.\r | |
| 906 | \r | |
| b1bfdd65 LE |
907 | This function abstracts the differences that whether the CPU Save State\r |
| 908 | register is in the IA32 CPU Save State Map or X64 CPU Save State Map.\r | |
| 4036b4e5 | 909 | \r |
| b1bfdd65 LE |
910 | This function supports reading a CPU Save State register in SMBase relocation\r |
| 911 | handler.\r | |
| 4036b4e5 | 912 | \r |
| b1bfdd65 LE |
913 | @param[in] CpuIndex Specifies the zero-based index of the CPU save\r |
| 914 | state.\r | |
| 4036b4e5 | 915 | @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r |
| b1bfdd65 LE |
916 | @param[in] Width The number of bytes to read from the CPU save\r |
| 917 | state.\r | |
| 918 | @param[out] Buffer Upon return, this holds the CPU register value\r | |
| 919 | read from the save state.\r | |
| 4036b4e5 PB |
920 | \r |
| 921 | @retval EFI_SUCCESS The register was read from Save State.\r | |
| b1bfdd65 LE |
922 | @retval EFI_NOT_FOUND The register is not defined for the Save State\r |
| 923 | of Processor.\r | |
| 4036b4e5 PB |
924 | @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r |
| 925 | \r | |
| 926 | **/\r | |
| ea992760 LE |
927 | STATIC\r |
| 928 | EFI_STATUS\r | |
| 4036b4e5 PB |
929 | ReadSaveStateRegisterByIndex (\r |
| 930 | IN UINTN CpuIndex,\r | |
| 931 | IN UINTN RegisterIndex,\r | |
| 932 | IN UINTN Width,\r | |
| 933 | OUT VOID *Buffer\r | |
| 934 | )\r | |
| 935 | {\r | |
| c1fcd80b | 936 | QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r |
| 4036b4e5 | 937 | \r |
| c1fcd80b | 938 | CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r |
| 4036b4e5 PB |
939 | \r |
| 940 | if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r | |
| 941 | //\r | |
| b1bfdd65 LE |
942 | // If 32-bit mode width is zero, then the specified register can not be\r |
| 943 | // accessed\r | |
| 4036b4e5 PB |
944 | //\r |
| 945 | if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {\r | |
| 946 | return EFI_NOT_FOUND;\r | |
| 947 | }\r | |
| 948 | \r | |
| 949 | //\r | |
| b1bfdd65 LE |
950 | // If Width is bigger than the 32-bit mode width, then the specified\r |
| 951 | // register can not be accessed\r | |
| 4036b4e5 PB |
952 | //\r |
| 953 | if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r | |
| 954 | return EFI_INVALID_PARAMETER;\r | |
| 955 | }\r | |
| 956 | \r | |
| 957 | //\r | |
| 958 | // Write return buffer\r | |
| 959 | //\r | |
| 960 | ASSERT(CpuSaveState != NULL);\r | |
| b1bfdd65 LE |
961 | CopyMem (\r |
| 962 | Buffer,\r | |
| 963 | (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,\r | |
| 964 | Width\r | |
| 965 | );\r | |
| 4036b4e5 PB |
966 | } else {\r |
| 967 | //\r | |
| b1bfdd65 LE |
968 | // If 64-bit mode width is zero, then the specified register can not be\r |
| 969 | // accessed\r | |
| 4036b4e5 PB |
970 | //\r |
| 971 | if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {\r | |
| 972 | return EFI_NOT_FOUND;\r | |
| 973 | }\r | |
| 974 | \r | |
| 975 | //\r | |
| b1bfdd65 LE |
976 | // If Width is bigger than the 64-bit mode width, then the specified\r |
| 977 | // register can not be accessed\r | |
| 4036b4e5 PB |
978 | //\r |
| 979 | if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {\r | |
| 980 | return EFI_INVALID_PARAMETER;\r | |
| 981 | }\r | |
| 982 | \r | |
| 983 | //\r | |
| 984 | // Write lower 32-bits of return buffer\r | |
| 985 | //\r | |
| b1bfdd65 LE |
986 | CopyMem (\r |
| 987 | Buffer,\r | |
| 988 | (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,\r | |
| 989 | MIN (4, Width)\r | |
| 990 | );\r | |
| 4036b4e5 PB |
991 | if (Width >= 4) {\r |
| 992 | //\r | |
| 993 | // Write upper 32-bits of return buffer\r | |
| 994 | //\r | |
| b1bfdd65 LE |
995 | CopyMem (\r |
| 996 | (UINT8 *)Buffer + 4,\r | |
| 997 | (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,\r | |
| 998 | Width - 4\r | |
| 999 | );\r | |
| 4036b4e5 PB |
1000 | }\r |
| 1001 | }\r | |
| 1002 | return EFI_SUCCESS;\r | |
| 1003 | }\r | |
| 1004 | \r | |
| 86d71589 PB |
1005 | /**\r |
| 1006 | Read an SMM Save State register on the target processor. If this function\r | |
| 1007 | returns EFI_UNSUPPORTED, then the caller is responsible for reading the\r | |
| 1008 | SMM Save Sate register.\r | |
| 1009 | \r | |
| 1010 | @param[in] CpuIndex The index of the CPU to read the SMM Save State. The\r | |
| 1011 | value must be between 0 and the NumberOfCpus field in\r | |
| 1012 | the System Management System Table (SMST).\r | |
| 1013 | @param[in] Register The SMM Save State register to read.\r | |
| 1014 | @param[in] Width The number of bytes to read from the CPU save state.\r | |
| 1015 | @param[out] Buffer Upon return, this holds the CPU register value read\r | |
| 1016 | from the save state.\r | |
| 1017 | \r | |
| 1018 | @retval EFI_SUCCESS The register was read from Save State.\r | |
| 1019 | @retval EFI_INVALID_PARAMTER Buffer is NULL.\r | |
| b1bfdd65 LE |
1020 | @retval EFI_UNSUPPORTED This function does not support reading\r |
| 1021 | Register.\r | |
| 86d71589 PB |
1022 | **/\r |
| 1023 | EFI_STATUS\r | |
| 1024 | EFIAPI\r | |
| 1025 | SmmCpuFeaturesReadSaveStateRegister (\r | |
| 1026 | IN UINTN CpuIndex,\r | |
| 1027 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
| 1028 | IN UINTN Width,\r | |
| 1029 | OUT VOID *Buffer\r | |
| 1030 | )\r | |
| 1031 | {\r | |
| c1fcd80b PB |
1032 | UINTN RegisterIndex;\r |
| 1033 | QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r | |
| 4036b4e5 PB |
1034 | \r |
| 1035 | //\r | |
| 1036 | // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA\r | |
| 1037 | //\r | |
| 1038 | if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {\r | |
| 1039 | //\r | |
| 1040 | // Only byte access is supported for this register\r | |
| 1041 | //\r | |
| 1042 | if (Width != 1) {\r | |
| 1043 | return EFI_INVALID_PARAMETER;\r | |
| 1044 | }\r | |
| 1045 | \r | |
| c1fcd80b | 1046 | CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r |
| 4036b4e5 PB |
1047 | \r |
| 1048 | //\r | |
| 1049 | // Check CPU mode\r | |
| 1050 | //\r | |
| 1051 | if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r | |
| 1052 | *(UINT8 *)Buffer = 32;\r | |
| 1053 | } else {\r | |
| 1054 | *(UINT8 *)Buffer = 64;\r | |
| 1055 | }\r | |
| 1056 | \r | |
| 1057 | return EFI_SUCCESS;\r | |
| 1058 | }\r | |
| 1059 | \r | |
| 1060 | //\r | |
| 1061 | // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO\r | |
| 1062 | //\r | |
| 1063 | if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {\r | |
| 1064 | return EFI_NOT_FOUND;\r | |
| 1065 | }\r | |
| 1066 | \r | |
| 1067 | //\r | |
| 1068 | // Convert Register to a register lookup table index. Let\r | |
| 1069 | // PiSmmCpuDxeSmm implement other special registers (currently\r | |
| 1070 | // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).\r | |
| 1071 | //\r | |
| 1072 | RegisterIndex = GetRegisterIndex (Register);\r | |
| 1073 | if (RegisterIndex == 0) {\r | |
| b1bfdd65 LE |
1074 | return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?\r |
| 1075 | EFI_NOT_FOUND :\r | |
| 1076 | EFI_UNSUPPORTED);\r | |
| 4036b4e5 PB |
1077 | }\r |
| 1078 | \r | |
| 1079 | return ReadSaveStateRegisterByIndex (CpuIndex, RegisterIndex, Width, Buffer);\r | |
| 86d71589 PB |
1080 | }\r |
| 1081 | \r | |
| 1082 | /**\r | |
| 1083 | Writes an SMM Save State register on the target processor. If this function\r | |
| 1084 | returns EFI_UNSUPPORTED, then the caller is responsible for writing the\r | |
| 1085 | SMM Save Sate register.\r | |
| 1086 | \r | |
| 1087 | @param[in] CpuIndex The index of the CPU to write the SMM Save State. The\r | |
| 1088 | value must be between 0 and the NumberOfCpus field in\r | |
| 1089 | the System Management System Table (SMST).\r | |
| 1090 | @param[in] Register The SMM Save State register to write.\r | |
| 1091 | @param[in] Width The number of bytes to write to the CPU save state.\r | |
| 1092 | @param[in] Buffer Upon entry, this holds the new CPU register value.\r | |
| 1093 | \r | |
| 1094 | @retval EFI_SUCCESS The register was written to Save State.\r | |
| 1095 | @retval EFI_INVALID_PARAMTER Buffer is NULL.\r | |
| b1bfdd65 LE |
1096 | @retval EFI_UNSUPPORTED This function does not support writing\r |
| 1097 | Register.\r | |
| 86d71589 PB |
1098 | **/\r |
| 1099 | EFI_STATUS\r | |
| 1100 | EFIAPI\r | |
| 1101 | SmmCpuFeaturesWriteSaveStateRegister (\r | |
| 1102 | IN UINTN CpuIndex,\r | |
| 1103 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
| 1104 | IN UINTN Width,\r | |
| 1105 | IN CONST VOID *Buffer\r | |
| 1106 | )\r | |
| 1107 | {\r | |
| c1fcd80b PB |
1108 | UINTN RegisterIndex;\r |
| 1109 | QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r | |
| 4036b4e5 PB |
1110 | \r |
| 1111 | //\r | |
| 1112 | // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored\r | |
| 1113 | //\r | |
| 1114 | if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {\r | |
| 1115 | return EFI_SUCCESS;\r | |
| 1116 | }\r | |
| 1117 | \r | |
| 1118 | //\r | |
| 1119 | // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported\r | |
| 1120 | //\r | |
| 1121 | if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {\r | |
| 1122 | return EFI_NOT_FOUND;\r | |
| 1123 | }\r | |
| 1124 | \r | |
| 1125 | //\r | |
| 1126 | // Convert Register to a register lookup table index. Let\r | |
| 1127 | // PiSmmCpuDxeSmm implement other special registers (currently\r | |
| 1128 | // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).\r | |
| 1129 | //\r | |
| 1130 | RegisterIndex = GetRegisterIndex (Register);\r | |
| 1131 | if (RegisterIndex == 0) {\r | |
| b1bfdd65 LE |
1132 | return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?\r |
| 1133 | EFI_NOT_FOUND :\r | |
| 1134 | EFI_UNSUPPORTED);\r | |
| 4036b4e5 PB |
1135 | }\r |
| 1136 | \r | |
| c1fcd80b | 1137 | CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r |
| 4036b4e5 PB |
1138 | \r |
| 1139 | //\r | |
| 1140 | // Do not write non-writable SaveState, because it will cause exception.\r | |
| b1bfdd65 | 1141 | //\r |
| 4036b4e5 PB |
1142 | if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {\r |
| 1143 | return EFI_UNSUPPORTED;\r | |
| 1144 | }\r | |
| 1145 | \r | |
| 1146 | //\r | |
| 1147 | // Check CPU mode\r | |
| 1148 | //\r | |
| 1149 | if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r | |
| 1150 | //\r | |
| b1bfdd65 LE |
1151 | // If 32-bit mode width is zero, then the specified register can not be\r |
| 1152 | // accessed\r | |
| 4036b4e5 PB |
1153 | //\r |
| 1154 | if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {\r | |
| 1155 | return EFI_NOT_FOUND;\r | |
| 1156 | }\r | |
| 1157 | \r | |
| 1158 | //\r | |
| b1bfdd65 LE |
1159 | // If Width is bigger than the 32-bit mode width, then the specified\r |
| 1160 | // register can not be accessed\r | |
| 4036b4e5 PB |
1161 | //\r |
| 1162 | if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r | |
| 1163 | return EFI_INVALID_PARAMETER;\r | |
| 1164 | }\r | |
| 1165 | //\r | |
| 1166 | // Write SMM State register\r | |
| 1167 | //\r | |
| 1168 | ASSERT (CpuSaveState != NULL);\r | |
| b1bfdd65 LE |
1169 | CopyMem (\r |
| 1170 | (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,\r | |
| 1171 | Buffer,\r | |
| 1172 | Width\r | |
| 1173 | );\r | |
| 4036b4e5 PB |
1174 | } else {\r |
| 1175 | //\r | |
| b1bfdd65 LE |
1176 | // If 64-bit mode width is zero, then the specified register can not be\r |
| 1177 | // accessed\r | |
| 4036b4e5 PB |
1178 | //\r |
| 1179 | if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {\r | |
| 1180 | return EFI_NOT_FOUND;\r | |
| 1181 | }\r | |
| 1182 | \r | |
| 1183 | //\r | |
| b1bfdd65 LE |
1184 | // If Width is bigger than the 64-bit mode width, then the specified\r |
| 1185 | // register can not be accessed\r | |
| 4036b4e5 PB |
1186 | //\r |
| 1187 | if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {\r | |
| 1188 | return EFI_INVALID_PARAMETER;\r | |
| 1189 | }\r | |
| 1190 | \r | |
| 1191 | //\r | |
| 1192 | // Write lower 32-bits of SMM State register\r | |
| 1193 | //\r | |
| b1bfdd65 LE |
1194 | CopyMem (\r |
| 1195 | (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,\r | |
| 1196 | Buffer,\r | |
| 1197 | MIN (4, Width)\r | |
| 1198 | );\r | |
| 4036b4e5 PB |
1199 | if (Width >= 4) {\r |
| 1200 | //\r | |
| 1201 | // Write upper 32-bits of SMM State register\r | |
| 1202 | //\r | |
| b1bfdd65 LE |
1203 | CopyMem (\r |
| 1204 | (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,\r | |
| 1205 | (UINT8 *)Buffer + 4,\r | |
| 1206 | Width - 4\r | |
| 1207 | );\r | |
| 4036b4e5 PB |
1208 | }\r |
| 1209 | }\r | |
| 1210 | return EFI_SUCCESS;\r | |
| 86d71589 PB |
1211 | }\r |
| 1212 | \r | |
| 1213 | /**\r | |
| 1214 | This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r | |
| 1215 | notification is completely processed.\r | |
| 1216 | **/\r | |
| 1217 | VOID\r | |
| 1218 | EFIAPI\r | |
| 1219 | SmmCpuFeaturesCompleteSmmReadyToLock (\r | |
| 1220 | VOID\r | |
| 1221 | )\r | |
| 1222 | {\r | |
| 1223 | }\r | |
| 1224 | \r | |
| 1225 | /**\r | |
| b1bfdd65 LE |
1226 | This API provides a method for a CPU to allocate a specific region for\r |
| 1227 | storing page tables.\r | |
| 86d71589 PB |
1228 | \r |
| 1229 | This API can be called more once to allocate memory for page tables.\r | |
| 1230 | \r | |
| b1bfdd65 LE |
1231 | Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns\r |
| 1232 | a pointer to the allocated buffer. The buffer returned is aligned on a 4KB\r | |
| 1233 | boundary. If Pages is 0, then NULL is returned. If there is not enough\r | |
| 1234 | memory remaining to satisfy the request, then NULL is returned.\r | |
| 86d71589 | 1235 | \r |
| b1bfdd65 LE |
1236 | This function can also return NULL if there is no preference on where the\r |
| 1237 | page tables are allocated in SMRAM.\r | |
| 86d71589 PB |
1238 | \r |
| 1239 | @param Pages The number of 4 KB pages to allocate.\r | |
| 1240 | \r | |
| 1241 | @return A pointer to the allocated buffer for page tables.\r | |
| 1242 | @retval NULL Fail to allocate a specific region for storing page tables,\r | |
| b1bfdd65 LE |
1243 | Or there is no preference on where the page tables are\r |
| 1244 | allocated in SMRAM.\r | |
| 86d71589 PB |
1245 | \r |
| 1246 | **/\r | |
| 1247 | VOID *\r | |
| 1248 | EFIAPI\r | |
| 1249 | SmmCpuFeaturesAllocatePageTableMemory (\r | |
| 1250 | IN UINTN Pages\r | |
| 1251 | )\r | |
| 1252 | {\r | |
| 1253 | return NULL;\r | |
| 1254 | }\r | |
| 1255 | \r |