OvmfPkg/SmmCpuFeaturesLib: sort #includes, and entries in INF file sections
[mirror_edk2.git] / OvmfPkg / Library / SmmCpuFeaturesLib / SmmCpuFeaturesLib.c
CommitLineData
86d71589 1/** @file\r
b1bfdd65 2 The CPU specific programming for PiSmmCpuDxeSmm module.\r
86d71589 3\r
b1bfdd65 4 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
86d71589 5\r
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6 This program and the accompanying materials are licensed and made available\r
7 under the terms and conditions of the BSD License which accompanies this\r
8 distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php\r
86d71589 10\r
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11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
12 WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
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13**/\r
14\r
86d71589 15#include <Library/BaseLib.h>\r
4036b4e5 16#include <Library/BaseMemoryLib.h>\r
4a9b250b 17#include <Library/DebugLib.h>\r
86d71589 18#include <Library/MemoryAllocationLib.h>\r
4a9b250b
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19#include <Library/PcdLib.h>\r
20#include <Library/SmmCpuFeaturesLib.h>\r
4036b4e5 21#include <Library/SmmServicesTableLib.h>\r
4a9b250b 22#include <PiSmm.h>\r
c1fcd80b 23#include <Register/QemuSmramSaveStateMap.h>\r
86d71589 24\r
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25//\r
26// EFER register LMA bit\r
27//\r
28#define LMA BIT10\r
29\r
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30/**\r
31 The constructor function\r
32\r
33 @param[in] ImageHandle The firmware allocated handle for the EFI image.\r
34 @param[in] SystemTable A pointer to the EFI System Table.\r
35\r
36 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r
37\r
38**/\r
39EFI_STATUS\r
40EFIAPI\r
41SmmCpuFeaturesLibConstructor (\r
42 IN EFI_HANDLE ImageHandle,\r
43 IN EFI_SYSTEM_TABLE *SystemTable\r
44 )\r
45{\r
86d71589 46 //\r
d7e71b29 47 // No need to program SMRRs on our virtual platform.\r
86d71589 48 //\r
86d71589
PB
49 return EFI_SUCCESS;\r
50}\r
51\r
52/**\r
53 Called during the very first SMI into System Management Mode to initialize\r
54 CPU features, including SMBASE, for the currently executing CPU. Since this\r
55 is the first SMI, the SMRAM Save State Map is at the default address of\r
56 SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing\r
57 CPU is specified by CpuIndex and CpuIndex can be used to access information\r
58 about the currently executing CPU in the ProcessorInfo array and the\r
59 HotPlugCpuData data structure.\r
60\r
61 @param[in] CpuIndex The index of the CPU to initialize. The value\r
62 must be between 0 and the NumberOfCpus field in\r
63 the System Management System Table (SMST).\r
64 @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that\r
65 was elected as monarch during System Management\r
66 Mode initialization.\r
67 FALSE if the CpuIndex is not the index of the CPU\r
68 that was elected as monarch during System\r
69 Management Mode initialization.\r
70 @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION\r
71 structures. ProcessorInfo[CpuIndex] contains the\r
72 information for the currently executing CPU.\r
73 @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that\r
74 contains the ApidId and SmBase arrays.\r
75**/\r
76VOID\r
77EFIAPI\r
78SmmCpuFeaturesInitializeProcessor (\r
79 IN UINTN CpuIndex,\r
80 IN BOOLEAN IsMonarch,\r
81 IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,\r
82 IN CPU_HOT_PLUG_DATA *CpuHotPlugData\r
83 )\r
84{\r
c1fcd80b 85 QEMU_SMRAM_SAVE_STATE_MAP *CpuState;\r
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PB
86\r
87 //\r
88 // Configure SMBASE.\r
89 //\r
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LE
90 CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(\r
91 SMM_DEFAULT_SMBASE +\r
92 SMRAM_SAVE_STATE_MAP_OFFSET\r
93 );\r
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PB
94 if ((CpuState->x86.SMMRevId & 0xFFFF) == 0) {\r
95 CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
96 } else {\r
97 CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
98 }\r
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99\r
100 //\r
d7e71b29 101 // No need to program SMRRs on our virtual platform.\r
86d71589 102 //\r
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103}\r
104\r
105/**\r
106 This function updates the SMRAM save state on the currently executing CPU\r
107 to resume execution at a specific address after an RSM instruction. This\r
108 function must evaluate the SMRAM save state to determine the execution mode\r
109 the RSM instruction resumes and update the resume execution address with\r
110 either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart\r
111 flag in the SMRAM save state must always be cleared. This function returns\r
112 the value of the instruction pointer from the SMRAM save state that was\r
113 replaced. If this function returns 0, then the SMRAM save state was not\r
114 modified.\r
115\r
116 This function is called during the very first SMI on each CPU after\r
117 SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode\r
118 to signal that the SMBASE of each CPU has been updated before the default\r
119 SMBASE address is used for the first SMI to the next CPU.\r
120\r
121 @param[in] CpuIndex The index of the CPU to hook. The value\r
122 must be between 0 and the NumberOfCpus\r
b1bfdd65
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123 field in the System Management System\r
124 Table (SMST).\r
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125 @param[in] CpuState Pointer to SMRAM Save State Map for the\r
126 currently executing CPU.\r
127 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
128 32-bit execution mode from 64-bit SMM.\r
129 @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r
130 same execution mode as SMM.\r
131\r
132 @retval 0 This function did modify the SMRAM save state.\r
133 @retval > 0 The original instruction pointer value from the SMRAM save state\r
134 before it was replaced.\r
135**/\r
136UINT64\r
137EFIAPI\r
138SmmCpuFeaturesHookReturnFromSmm (\r
139 IN UINTN CpuIndex,\r
140 IN SMRAM_SAVE_STATE_MAP *CpuState,\r
141 IN UINT64 NewInstructionPointer32,\r
142 IN UINT64 NewInstructionPointer\r
143 )\r
144{\r
c1fcd80b 145 UINT64 OriginalInstructionPointer;\r
b1bfdd65 146 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
4036b4e5 147\r
b1bfdd65 148 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState;\r
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PB
149 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
150 OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP;\r
151 CpuSaveState->x86._EIP = (UINT32)NewInstructionPointer;\r
152 //\r
153 // Clear the auto HALT restart flag so the RSM instruction returns\r
154 // program control to the instruction following the HLT instruction.\r
155 //\r
156 if ((CpuSaveState->x86.AutoHALTRestart & BIT0) != 0) {\r
157 CpuSaveState->x86.AutoHALTRestart &= ~BIT0;\r
158 }\r
159 } else {\r
160 OriginalInstructionPointer = CpuSaveState->x64._RIP;\r
161 if ((CpuSaveState->x64.IA32_EFER & LMA) == 0) {\r
162 CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer32;\r
163 } else {\r
164 CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer;\r
165 }\r
166 //\r
167 // Clear the auto HALT restart flag so the RSM instruction returns\r
168 // program control to the instruction following the HLT instruction.\r
169 //\r
170 if ((CpuSaveState->x64.AutoHALTRestart & BIT0) != 0) {\r
171 CpuSaveState->x64.AutoHALTRestart &= ~BIT0;\r
172 }\r
173 }\r
174 return OriginalInstructionPointer;\r
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175}\r
176\r
177/**\r
178 Hook point in normal execution mode that allows the one CPU that was elected\r
179 as monarch during System Management Mode initialization to perform additional\r
180 initialization actions immediately after all of the CPUs have processed their\r
181 first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE\r
182 into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().\r
183**/\r
184VOID\r
185EFIAPI\r
186SmmCpuFeaturesSmmRelocationComplete (\r
187 VOID\r
188 )\r
189{\r
190}\r
191\r
192/**\r
193 Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is\r
194 returned, then a custom SMI handler is not provided by this library,\r
195 and the default SMI handler must be used.\r
196\r
197 @retval 0 Use the default SMI handler.\r
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198 @retval > 0 Use the SMI handler installed by\r
199 SmmCpuFeaturesInstallSmiHandler(). The caller is required to\r
200 allocate enough SMRAM for each CPU to support the size of the\r
201 custom SMI handler.\r
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202**/\r
203UINTN\r
204EFIAPI\r
205SmmCpuFeaturesGetSmiHandlerSize (\r
206 VOID\r
207 )\r
208{\r
209 return 0;\r
210}\r
211\r
212/**\r
b1bfdd65
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213 Install a custom SMI handler for the CPU specified by CpuIndex. This\r
214 function is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size\r
215 is greater than zero and is called by the CPU that was elected as monarch\r
216 during System Management Mode initialization.\r
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217\r
218 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r
219 The value must be between 0 and the NumberOfCpus field\r
220 in the System Management System Table (SMST).\r
221 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r
222 @param[in] SmiStack The stack to use when an SMI is processed by the\r
223 the CPU specified by CpuIndex.\r
224 @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r
225 processed by the CPU specified by CpuIndex.\r
226 @param[in] GdtBase The base address of the GDT to use when an SMI is\r
227 processed by the CPU specified by CpuIndex.\r
228 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r
229 processed by the CPU specified by CpuIndex.\r
230 @param[in] IdtBase The base address of the IDT to use when an SMI is\r
231 processed by the CPU specified by CpuIndex.\r
232 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r
233 processed by the CPU specified by CpuIndex.\r
234 @param[in] Cr3 The base address of the page tables to use when an SMI\r
235 is processed by the CPU specified by CpuIndex.\r
236**/\r
237VOID\r
238EFIAPI\r
239SmmCpuFeaturesInstallSmiHandler (\r
240 IN UINTN CpuIndex,\r
241 IN UINT32 SmBase,\r
242 IN VOID *SmiStack,\r
243 IN UINTN StackSize,\r
244 IN UINTN GdtBase,\r
245 IN UINTN GdtSize,\r
246 IN UINTN IdtBase,\r
247 IN UINTN IdtSize,\r
248 IN UINT32 Cr3\r
249 )\r
250{\r
251}\r
252\r
253/**\r
254 Determines if MTRR registers must be configured to set SMRAM cache-ability\r
255 when executing in System Management Mode.\r
256\r
257 @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.\r
258 @retval FALSE MTRR registers do not need to be configured to set SMRAM\r
259 cache-ability.\r
260**/\r
261BOOLEAN\r
262EFIAPI\r
263SmmCpuFeaturesNeedConfigureMtrrs (\r
264 VOID\r
265 )\r
266{\r
d7e71b29 267 return FALSE;\r
86d71589
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268}\r
269\r
270/**\r
b1bfdd65
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271 Disable SMRR register if SMRR is supported and\r
272 SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.\r
86d71589
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273**/\r
274VOID\r
275EFIAPI\r
276SmmCpuFeaturesDisableSmrr (\r
277 VOID\r
278 )\r
279{\r
d7e71b29
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280 //\r
281 // No SMRR support, nothing to do\r
282 //\r
86d71589
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283}\r
284\r
285/**\r
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286 Enable SMRR register if SMRR is supported and\r
287 SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.\r
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288**/\r
289VOID\r
290EFIAPI\r
291SmmCpuFeaturesReenableSmrr (\r
292 VOID\r
293 )\r
294{\r
d7e71b29
PB
295 //\r
296 // No SMRR support, nothing to do\r
297 //\r
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298}\r
299\r
300/**\r
301 Processor specific hook point each time a CPU enters System Management Mode.\r
302\r
303 @param[in] CpuIndex The index of the CPU that has entered SMM. The value\r
304 must be between 0 and the NumberOfCpus field in the\r
305 System Management System Table (SMST).\r
306**/\r
307VOID\r
308EFIAPI\r
309SmmCpuFeaturesRendezvousEntry (\r
310 IN UINTN CpuIndex\r
311 )\r
312{\r
313 //\r
d7e71b29 314 // No SMRR support, nothing to do\r
86d71589 315 //\r
86d71589
PB
316}\r
317\r
318/**\r
319 Processor specific hook point each time a CPU exits System Management Mode.\r
320\r
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321 @param[in] CpuIndex The index of the CPU that is exiting SMM. The value\r
322 must be between 0 and the NumberOfCpus field in the\r
323 System Management System Table (SMST).\r
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324**/\r
325VOID\r
326EFIAPI\r
327SmmCpuFeaturesRendezvousExit (\r
328 IN UINTN CpuIndex\r
329 )\r
330{\r
331}\r
332\r
333/**\r
334 Check to see if an SMM register is supported by a specified CPU.\r
335\r
336 @param[in] CpuIndex The index of the CPU to check for SMM register support.\r
337 The value must be between 0 and the NumberOfCpus field\r
338 in the System Management System Table (SMST).\r
339 @param[in] RegName Identifies the SMM register to check for support.\r
340\r
341 @retval TRUE The SMM register specified by RegName is supported by the CPU\r
342 specified by CpuIndex.\r
343 @retval FALSE The SMM register specified by RegName is not supported by the\r
344 CPU specified by CpuIndex.\r
345**/\r
346BOOLEAN\r
347EFIAPI\r
348SmmCpuFeaturesIsSmmRegisterSupported (\r
349 IN UINTN CpuIndex,\r
350 IN SMM_REG_NAME RegName\r
351 )\r
352{\r
d7e71b29 353 ASSERT (RegName == SmmRegFeatureControl);\r
86d71589
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354 return FALSE;\r
355}\r
356\r
357/**\r
358 Returns the current value of the SMM register for the specified CPU.\r
359 If the SMM register is not supported, then 0 is returned.\r
360\r
361 @param[in] CpuIndex The index of the CPU to read the SMM register. The\r
362 value must be between 0 and the NumberOfCpus field in\r
363 the System Management System Table (SMST).\r
364 @param[in] RegName Identifies the SMM register to read.\r
365\r
366 @return The value of the SMM register specified by RegName from the CPU\r
367 specified by CpuIndex.\r
368**/\r
369UINT64\r
370EFIAPI\r
371SmmCpuFeaturesGetSmmRegister (\r
372 IN UINTN CpuIndex,\r
373 IN SMM_REG_NAME RegName\r
374 )\r
375{\r
d7e71b29
PB
376 //\r
377 // This is called for SmmRegSmmDelayed, SmmRegSmmBlocked, SmmRegSmmEnable.\r
378 // The last of these should actually be SmmRegSmmDisable, so we can just\r
379 // return FALSE.\r
380 //\r
86d71589
PB
381 return 0;\r
382}\r
383\r
384/**\r
385 Sets the value of an SMM register on a specified CPU.\r
386 If the SMM register is not supported, then no action is performed.\r
387\r
388 @param[in] CpuIndex The index of the CPU to write the SMM register. The\r
389 value must be between 0 and the NumberOfCpus field in\r
390 the System Management System Table (SMST).\r
391 @param[in] RegName Identifies the SMM register to write.\r
392 registers are read-only.\r
393 @param[in] Value The value to write to the SMM register.\r
394**/\r
395VOID\r
396EFIAPI\r
397SmmCpuFeaturesSetSmmRegister (\r
398 IN UINTN CpuIndex,\r
399 IN SMM_REG_NAME RegName,\r
400 IN UINT64 Value\r
401 )\r
402{\r
d7e71b29 403 ASSERT (FALSE);\r
86d71589
PB
404}\r
405\r
4036b4e5 406///\r
b1bfdd65
LE
407/// Macro used to simplify the lookup table entries of type\r
408/// CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
4036b4e5 409///\r
c1fcd80b 410#define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)\r
4036b4e5
PB
411\r
412///\r
b1bfdd65
LE
413/// Macro used to simplify the lookup table entries of type\r
414/// CPU_SMM_SAVE_STATE_REGISTER_RANGE\r
4036b4e5
PB
415///\r
416#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }\r
417\r
418///\r
419/// Structure used to describe a range of registers\r
420///\r
421typedef struct {\r
422 EFI_SMM_SAVE_STATE_REGISTER Start;\r
423 EFI_SMM_SAVE_STATE_REGISTER End;\r
424 UINTN Length;\r
425} CPU_SMM_SAVE_STATE_REGISTER_RANGE;\r
426\r
427///\r
428/// Structure used to build a lookup table to retrieve the widths and offsets\r
429/// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value\r
430///\r
431\r
432#define SMM_SAVE_STATE_REGISTER_FIRST_INDEX 1\r
433\r
434typedef struct {\r
435 UINT8 Width32;\r
436 UINT8 Width64;\r
437 UINT16 Offset32;\r
438 UINT16 Offset64Lo;\r
439 UINT16 Offset64Hi;\r
440 BOOLEAN Writeable;\r
441} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;\r
442\r
443///\r
b1bfdd65 444/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER\r
4036b4e5
PB
445/// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
446///\r
ea992760 447STATIC CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {\r
b1bfdd65
LE
448 SMM_REGISTER_RANGE (\r
449 EFI_SMM_SAVE_STATE_REGISTER_GDTBASE,\r
450 EFI_SMM_SAVE_STATE_REGISTER_LDTINFO\r
451 ),\r
452 SMM_REGISTER_RANGE (\r
453 EFI_SMM_SAVE_STATE_REGISTER_ES,\r
454 EFI_SMM_SAVE_STATE_REGISTER_RIP\r
455 ),\r
456 SMM_REGISTER_RANGE (\r
457 EFI_SMM_SAVE_STATE_REGISTER_RFLAGS,\r
458 EFI_SMM_SAVE_STATE_REGISTER_CR4\r
459 ),\r
4036b4e5
PB
460 { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }\r
461};\r
462\r
463///\r
b1bfdd65
LE
464/// Lookup table used to retrieve the widths and offsets associated with each\r
465/// supported EFI_SMM_SAVE_STATE_REGISTER value\r
4036b4e5 466///\r
ea992760 467STATIC CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {\r
b1bfdd65
LE
468 {\r
469 0, // Width32\r
470 0, // Width64\r
471 0, // Offset32\r
472 0, // Offset64Lo\r
473 0, // Offset64Hi\r
474 FALSE // Writeable\r
475 }, // Reserved\r
4036b4e5
PB
476\r
477 //\r
478 // CPU Save State registers defined in PI SMM CPU Protocol.\r
479 //\r
b1bfdd65
LE
480 {\r
481 0, // Width32\r
482 8, // Width64\r
483 0, // Offset32\r
484 SMM_CPU_OFFSET (x64._GDTRBase), // Offset64Lo\r
485 SMM_CPU_OFFSET (x64._GDTRBase) + 4, // Offset64Hi\r
486 FALSE // Writeable\r
487 }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4\r
488\r
489 {\r
490 0, // Width32\r
491 8, // Width64\r
492 0, // Offset32\r
493 SMM_CPU_OFFSET (x64._IDTRBase), // Offset64Lo\r
494 SMM_CPU_OFFSET (x64._IDTRBase) + 4, // Offset64Hi\r
495 FALSE // Writeable\r
496 }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5\r
497\r
498 {\r
499 0, // Width32\r
500 8, // Width64\r
501 0, // Offset32\r
502 SMM_CPU_OFFSET (x64._LDTRBase), // Offset64Lo\r
503 SMM_CPU_OFFSET (x64._LDTRBase) + 4, // Offset64Hi\r
504 FALSE // Writeable\r
505 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6\r
506\r
507 {\r
508 0, // Width32\r
509 0, // Width64\r
510 0, // Offset32\r
511 SMM_CPU_OFFSET (x64._GDTRLimit), // Offset64Lo\r
512 SMM_CPU_OFFSET (x64._GDTRLimit) + 4, // Offset64Hi\r
513 FALSE // Writeable\r
514 }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7\r
515\r
516 {\r
517 0, // Width32\r
518 0, // Width64\r
519 0, // Offset32\r
520 SMM_CPU_OFFSET (x64._IDTRLimit), // Offset64Lo\r
521 SMM_CPU_OFFSET (x64._IDTRLimit) + 4, // Offset64Hi\r
522 FALSE // Writeable\r
523 }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8\r
524\r
525 {\r
526 0, // Width32\r
527 0, // Width64\r
528 0, // Offset32\r
529 SMM_CPU_OFFSET (x64._LDTRLimit), // Offset64Lo\r
530 SMM_CPU_OFFSET (x64._LDTRLimit) + 4, // Offset64Hi\r
531 FALSE // Writeable\r
532 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9\r
533\r
534 {\r
535 0, // Width32\r
536 0, // Width64\r
537 0, // Offset32\r
538 0, // Offset64Lo\r
539 0 + 4, // Offset64Hi\r
540 FALSE // Writeable\r
541 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10\r
542\r
543 {\r
544 4, // Width32\r
545 4, // Width64\r
546 SMM_CPU_OFFSET (x86._ES), // Offset32\r
547 SMM_CPU_OFFSET (x64._ES), // Offset64Lo\r
548 0, // Offset64Hi\r
549 FALSE // Writeable\r
550 }, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20\r
551\r
552 {\r
553 4, // Width32\r
554 4, // Width64\r
555 SMM_CPU_OFFSET (x86._CS), // Offset32\r
556 SMM_CPU_OFFSET (x64._CS), // Offset64Lo\r
557 0, // Offset64Hi\r
558 FALSE // Writeable\r
559 }, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21\r
560\r
561 {\r
562 4, // Width32\r
563 4, // Width64\r
564 SMM_CPU_OFFSET (x86._SS), // Offset32\r
565 SMM_CPU_OFFSET (x64._SS), // Offset64Lo\r
566 0, // Offset64Hi\r
567 FALSE // Writeable\r
568 }, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22\r
569\r
570 {\r
571 4, // Width32\r
572 4, // Width64\r
573 SMM_CPU_OFFSET (x86._DS), // Offset32\r
574 SMM_CPU_OFFSET (x64._DS), // Offset64Lo\r
575 0, // Offset64Hi\r
576 FALSE // Writeable\r
577 }, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23\r
578\r
579 {\r
580 4, // Width32\r
581 4, // Width64\r
582 SMM_CPU_OFFSET (x86._FS), // Offset32\r
583 SMM_CPU_OFFSET (x64._FS), // Offset64Lo\r
584 0, // Offset64Hi\r
585 FALSE // Writeable\r
586 }, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24\r
587\r
588 {\r
589 4, // Width32\r
590 4, // Width64\r
591 SMM_CPU_OFFSET (x86._GS), // Offset32\r
592 SMM_CPU_OFFSET (x64._GS), // Offset64Lo\r
593 0, // Offset64Hi\r
594 FALSE // Writeable\r
595 }, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25\r
596\r
597 {\r
598 0, // Width32\r
599 4, // Width64\r
600 0, // Offset32\r
601 SMM_CPU_OFFSET (x64._LDTR), // Offset64Lo\r
602 0, // Offset64Hi\r
603 FALSE // Writeable\r
604 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26\r
605\r
606 {\r
607 4, // Width32\r
608 4, // Width64\r
609 SMM_CPU_OFFSET (x86._TR), // Offset32\r
610 SMM_CPU_OFFSET (x64._TR), // Offset64Lo\r
611 0, // Offset64Hi\r
612 FALSE // Writeable\r
613 }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27\r
614\r
615 {\r
616 4, // Width32\r
617 8, // Width64\r
618 SMM_CPU_OFFSET (x86._DR7), // Offset32\r
619 SMM_CPU_OFFSET (x64._DR7), // Offset64Lo\r
620 SMM_CPU_OFFSET (x64._DR7) + 4, // Offset64Hi\r
621 FALSE // Writeable\r
622 }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28\r
623\r
624 {\r
625 4, // Width32\r
626 8, // Width64\r
627 SMM_CPU_OFFSET (x86._DR6), // Offset32\r
628 SMM_CPU_OFFSET (x64._DR6), // Offset64Lo\r
629 SMM_CPU_OFFSET (x64._DR6) + 4, // Offset64Hi\r
630 FALSE // Writeable\r
631 }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29\r
632\r
633 {\r
634 0, // Width32\r
635 8, // Width64\r
636 0, // Offset32\r
637 SMM_CPU_OFFSET (x64._R8), // Offset64Lo\r
638 SMM_CPU_OFFSET (x64._R8) + 4, // Offset64Hi\r
639 TRUE // Writeable\r
640 }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30\r
641\r
642 {\r
643 0, // Width32\r
644 8, // Width64\r
645 0, // Offset32\r
646 SMM_CPU_OFFSET (x64._R9), // Offset64Lo\r
647 SMM_CPU_OFFSET (x64._R9) + 4, // Offset64Hi\r
648 TRUE // Writeable\r
649 }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31\r
650\r
651 {\r
652 0, // Width32\r
653 8, // Width64\r
654 0, // Offset32\r
655 SMM_CPU_OFFSET (x64._R10), // Offset64Lo\r
656 SMM_CPU_OFFSET (x64._R10) + 4, // Offset64Hi\r
657 TRUE // Writeable\r
658 }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32\r
659\r
660 {\r
661 0, // Width32\r
662 8, // Width64\r
663 0, // Offset32\r
664 SMM_CPU_OFFSET (x64._R11), // Offset64Lo\r
665 SMM_CPU_OFFSET (x64._R11) + 4, // Offset64Hi\r
666 TRUE // Writeable\r
667 }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33\r
668\r
669 {\r
670 0, // Width32\r
671 8, // Width64\r
672 0, // Offset32\r
673 SMM_CPU_OFFSET (x64._R12), // Offset64Lo\r
674 SMM_CPU_OFFSET (x64._R12) + 4, // Offset64Hi\r
675 TRUE // Writeable\r
676 }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34\r
677\r
678 {\r
679 0, // Width32\r
680 8, // Width64\r
681 0, // Offset32\r
682 SMM_CPU_OFFSET (x64._R13), // Offset64Lo\r
683 SMM_CPU_OFFSET (x64._R13) + 4, // Offset64Hi\r
684 TRUE // Writeable\r
685 }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35\r
686\r
687 {\r
688 0, // Width32\r
689 8, // Width64\r
690 0, // Offset32\r
691 SMM_CPU_OFFSET (x64._R14), // Offset64Lo\r
692 SMM_CPU_OFFSET (x64._R14) + 4, // Offset64Hi\r
693 TRUE // Writeable\r
694 }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36\r
695\r
696 {\r
697 0, // Width32\r
698 8, // Width64\r
699 0, // Offset32\r
700 SMM_CPU_OFFSET (x64._R15), // Offset64Lo\r
701 SMM_CPU_OFFSET (x64._R15) + 4, // Offset64Hi\r
702 TRUE // Writeable\r
703 }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37\r
704\r
705 {\r
706 4, // Width32\r
707 8, // Width64\r
708 SMM_CPU_OFFSET (x86._EAX), // Offset32\r
709 SMM_CPU_OFFSET (x64._RAX), // Offset64Lo\r
710 SMM_CPU_OFFSET (x64._RAX) + 4, // Offset64Hi\r
711 TRUE // Writeable\r
712 }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38\r
713\r
714 {\r
715 4, // Width32\r
716 8, // Width64\r
717 SMM_CPU_OFFSET (x86._EBX), // Offset32\r
718 SMM_CPU_OFFSET (x64._RBX), // Offset64Lo\r
719 SMM_CPU_OFFSET (x64._RBX) + 4, // Offset64Hi\r
720 TRUE // Writeable\r
721 }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39\r
722\r
723 {\r
724 4, // Width32\r
725 8, // Width64\r
726 SMM_CPU_OFFSET (x86._ECX), // Offset32\r
727 SMM_CPU_OFFSET (x64._RCX), // Offset64Lo\r
728 SMM_CPU_OFFSET (x64._RCX) + 4, // Offset64Hi\r
729 TRUE // Writeable\r
730 }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40\r
731\r
732 {\r
733 4, // Width32\r
734 8, // Width64\r
735 SMM_CPU_OFFSET (x86._EDX), // Offset32\r
736 SMM_CPU_OFFSET (x64._RDX), // Offset64Lo\r
737 SMM_CPU_OFFSET (x64._RDX) + 4, // Offset64Hi\r
738 TRUE // Writeable\r
739 }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41\r
740\r
741 {\r
742 4, // Width32\r
743 8, // Width64\r
744 SMM_CPU_OFFSET (x86._ESP), // Offset32\r
745 SMM_CPU_OFFSET (x64._RSP), // Offset64Lo\r
746 SMM_CPU_OFFSET (x64._RSP) + 4, // Offset64Hi\r
747 TRUE // Writeable\r
748 }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42\r
749\r
750 {\r
751 4, // Width32\r
752 8, // Width64\r
753 SMM_CPU_OFFSET (x86._EBP), // Offset32\r
754 SMM_CPU_OFFSET (x64._RBP), // Offset64Lo\r
755 SMM_CPU_OFFSET (x64._RBP) + 4, // Offset64Hi\r
756 TRUE // Writeable\r
757 }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43\r
758\r
759 {\r
760 4, // Width32\r
761 8, // Width64\r
762 SMM_CPU_OFFSET (x86._ESI), // Offset32\r
763 SMM_CPU_OFFSET (x64._RSI), // Offset64Lo\r
764 SMM_CPU_OFFSET (x64._RSI) + 4, // Offset64Hi\r
765 TRUE // Writeable\r
766 }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44\r
767\r
768 {\r
769 4, // Width32\r
770 8, // Width64\r
771 SMM_CPU_OFFSET (x86._EDI), // Offset32\r
772 SMM_CPU_OFFSET (x64._RDI), // Offset64Lo\r
773 SMM_CPU_OFFSET (x64._RDI) + 4, // Offset64Hi\r
774 TRUE // Writeable\r
775 }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45\r
776\r
777 {\r
778 4, // Width32\r
779 8, // Width64\r
780 SMM_CPU_OFFSET (x86._EIP), // Offset32\r
781 SMM_CPU_OFFSET (x64._RIP), // Offset64Lo\r
782 SMM_CPU_OFFSET (x64._RIP) + 4, // Offset64Hi\r
783 TRUE // Writeable\r
784 }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46\r
785\r
786 {\r
787 4, // Width32\r
788 8, // Width64\r
789 SMM_CPU_OFFSET (x86._EFLAGS), // Offset32\r
790 SMM_CPU_OFFSET (x64._RFLAGS), // Offset64Lo\r
791 SMM_CPU_OFFSET (x64._RFLAGS) + 4, // Offset64Hi\r
792 TRUE // Writeable\r
793 }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51\r
794\r
795 {\r
796 4, // Width32\r
797 8, // Width64\r
798 SMM_CPU_OFFSET (x86._CR0), // Offset32\r
799 SMM_CPU_OFFSET (x64._CR0), // Offset64Lo\r
800 SMM_CPU_OFFSET (x64._CR0) + 4, // Offset64Hi\r
801 FALSE // Writeable\r
802 }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52\r
803\r
804 {\r
805 4, // Width32\r
806 8, // Width64\r
807 SMM_CPU_OFFSET (x86._CR3), // Offset32\r
808 SMM_CPU_OFFSET (x64._CR3), // Offset64Lo\r
809 SMM_CPU_OFFSET (x64._CR3) + 4, // Offset64Hi\r
810 FALSE // Writeable\r
811 }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53\r
812\r
813 {\r
814 0, // Width32\r
815 4, // Width64\r
816 0, // Offset32\r
817 SMM_CPU_OFFSET (x64._CR4), // Offset64Lo\r
818 SMM_CPU_OFFSET (x64._CR4) + 4, // Offset64Hi\r
819 FALSE // Writeable\r
820 }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54\r
4036b4e5
PB
821};\r
822\r
823//\r
824// No support for I/O restart\r
825//\r
826\r
827/**\r
828 Read information from the CPU save state.\r
829\r
830 @param Register Specifies the CPU register to read form the save state.\r
831\r
832 @retval 0 Register is not valid\r
833 @retval >0 Index into mSmmCpuWidthOffset[] associated with Register\r
834\r
835**/\r
ea992760
LE
836STATIC\r
837UINTN\r
4036b4e5
PB
838GetRegisterIndex (\r
839 IN EFI_SMM_SAVE_STATE_REGISTER Register\r
840 )\r
841{\r
842 UINTN Index;\r
843 UINTN Offset;\r
844\r
b1bfdd65
LE
845 for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX;\r
846 mSmmCpuRegisterRanges[Index].Length != 0;\r
847 Index++) {\r
848 if (Register >= mSmmCpuRegisterRanges[Index].Start &&\r
849 Register <= mSmmCpuRegisterRanges[Index].End) {\r
4036b4e5
PB
850 return Register - mSmmCpuRegisterRanges[Index].Start + Offset;\r
851 }\r
852 Offset += mSmmCpuRegisterRanges[Index].Length;\r
853 }\r
854 return 0;\r
855}\r
856\r
857/**\r
858 Read a CPU Save State register on the target processor.\r
859\r
b1bfdd65
LE
860 This function abstracts the differences that whether the CPU Save State\r
861 register is in the IA32 CPU Save State Map or X64 CPU Save State Map.\r
4036b4e5 862\r
b1bfdd65
LE
863 This function supports reading a CPU Save State register in SMBase relocation\r
864 handler.\r
4036b4e5 865\r
b1bfdd65
LE
866 @param[in] CpuIndex Specifies the zero-based index of the CPU save\r
867 state.\r
4036b4e5 868 @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
b1bfdd65
LE
869 @param[in] Width The number of bytes to read from the CPU save\r
870 state.\r
871 @param[out] Buffer Upon return, this holds the CPU register value\r
872 read from the save state.\r
4036b4e5
PB
873\r
874 @retval EFI_SUCCESS The register was read from Save State.\r
b1bfdd65
LE
875 @retval EFI_NOT_FOUND The register is not defined for the Save State\r
876 of Processor.\r
4036b4e5
PB
877 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
878\r
879**/\r
ea992760
LE
880STATIC\r
881EFI_STATUS\r
4036b4e5
PB
882ReadSaveStateRegisterByIndex (\r
883 IN UINTN CpuIndex,\r
884 IN UINTN RegisterIndex,\r
885 IN UINTN Width,\r
886 OUT VOID *Buffer\r
887 )\r
888{\r
c1fcd80b 889 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
4036b4e5 890\r
c1fcd80b 891 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
4036b4e5
PB
892\r
893 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
894 //\r
b1bfdd65
LE
895 // If 32-bit mode width is zero, then the specified register can not be\r
896 // accessed\r
4036b4e5
PB
897 //\r
898 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {\r
899 return EFI_NOT_FOUND;\r
900 }\r
901\r
902 //\r
b1bfdd65
LE
903 // If Width is bigger than the 32-bit mode width, then the specified\r
904 // register can not be accessed\r
4036b4e5
PB
905 //\r
906 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r
907 return EFI_INVALID_PARAMETER;\r
908 }\r
909\r
910 //\r
911 // Write return buffer\r
912 //\r
913 ASSERT(CpuSaveState != NULL);\r
b1bfdd65
LE
914 CopyMem (\r
915 Buffer,\r
916 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,\r
917 Width\r
918 );\r
4036b4e5
PB
919 } else {\r
920 //\r
b1bfdd65
LE
921 // If 64-bit mode width is zero, then the specified register can not be\r
922 // accessed\r
4036b4e5
PB
923 //\r
924 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {\r
925 return EFI_NOT_FOUND;\r
926 }\r
927\r
928 //\r
b1bfdd65
LE
929 // If Width is bigger than the 64-bit mode width, then the specified\r
930 // register can not be accessed\r
4036b4e5
PB
931 //\r
932 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {\r
933 return EFI_INVALID_PARAMETER;\r
934 }\r
935\r
936 //\r
937 // Write lower 32-bits of return buffer\r
938 //\r
b1bfdd65
LE
939 CopyMem (\r
940 Buffer,\r
941 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,\r
942 MIN (4, Width)\r
943 );\r
4036b4e5
PB
944 if (Width >= 4) {\r
945 //\r
946 // Write upper 32-bits of return buffer\r
947 //\r
b1bfdd65
LE
948 CopyMem (\r
949 (UINT8 *)Buffer + 4,\r
950 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,\r
951 Width - 4\r
952 );\r
4036b4e5
PB
953 }\r
954 }\r
955 return EFI_SUCCESS;\r
956}\r
957\r
86d71589
PB
958/**\r
959 Read an SMM Save State register on the target processor. If this function\r
960 returns EFI_UNSUPPORTED, then the caller is responsible for reading the\r
961 SMM Save Sate register.\r
962\r
963 @param[in] CpuIndex The index of the CPU to read the SMM Save State. The\r
964 value must be between 0 and the NumberOfCpus field in\r
965 the System Management System Table (SMST).\r
966 @param[in] Register The SMM Save State register to read.\r
967 @param[in] Width The number of bytes to read from the CPU save state.\r
968 @param[out] Buffer Upon return, this holds the CPU register value read\r
969 from the save state.\r
970\r
971 @retval EFI_SUCCESS The register was read from Save State.\r
972 @retval EFI_INVALID_PARAMTER Buffer is NULL.\r
b1bfdd65
LE
973 @retval EFI_UNSUPPORTED This function does not support reading\r
974 Register.\r
86d71589
PB
975**/\r
976EFI_STATUS\r
977EFIAPI\r
978SmmCpuFeaturesReadSaveStateRegister (\r
979 IN UINTN CpuIndex,\r
980 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
981 IN UINTN Width,\r
982 OUT VOID *Buffer\r
983 )\r
984{\r
c1fcd80b
PB
985 UINTN RegisterIndex;\r
986 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
4036b4e5
PB
987\r
988 //\r
989 // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA\r
990 //\r
991 if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {\r
992 //\r
993 // Only byte access is supported for this register\r
994 //\r
995 if (Width != 1) {\r
996 return EFI_INVALID_PARAMETER;\r
997 }\r
998\r
c1fcd80b 999 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
4036b4e5
PB
1000\r
1001 //\r
1002 // Check CPU mode\r
1003 //\r
1004 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
1005 *(UINT8 *)Buffer = 32;\r
1006 } else {\r
1007 *(UINT8 *)Buffer = 64;\r
1008 }\r
1009\r
1010 return EFI_SUCCESS;\r
1011 }\r
1012\r
1013 //\r
1014 // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO\r
1015 //\r
1016 if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {\r
1017 return EFI_NOT_FOUND;\r
1018 }\r
1019\r
1020 //\r
1021 // Convert Register to a register lookup table index. Let\r
1022 // PiSmmCpuDxeSmm implement other special registers (currently\r
1023 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).\r
1024 //\r
1025 RegisterIndex = GetRegisterIndex (Register);\r
1026 if (RegisterIndex == 0) {\r
b1bfdd65
LE
1027 return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?\r
1028 EFI_NOT_FOUND :\r
1029 EFI_UNSUPPORTED);\r
4036b4e5
PB
1030 }\r
1031\r
1032 return ReadSaveStateRegisterByIndex (CpuIndex, RegisterIndex, Width, Buffer);\r
86d71589
PB
1033}\r
1034\r
1035/**\r
1036 Writes an SMM Save State register on the target processor. If this function\r
1037 returns EFI_UNSUPPORTED, then the caller is responsible for writing the\r
1038 SMM Save Sate register.\r
1039\r
1040 @param[in] CpuIndex The index of the CPU to write the SMM Save State. The\r
1041 value must be between 0 and the NumberOfCpus field in\r
1042 the System Management System Table (SMST).\r
1043 @param[in] Register The SMM Save State register to write.\r
1044 @param[in] Width The number of bytes to write to the CPU save state.\r
1045 @param[in] Buffer Upon entry, this holds the new CPU register value.\r
1046\r
1047 @retval EFI_SUCCESS The register was written to Save State.\r
1048 @retval EFI_INVALID_PARAMTER Buffer is NULL.\r
b1bfdd65
LE
1049 @retval EFI_UNSUPPORTED This function does not support writing\r
1050 Register.\r
86d71589
PB
1051**/\r
1052EFI_STATUS\r
1053EFIAPI\r
1054SmmCpuFeaturesWriteSaveStateRegister (\r
1055 IN UINTN CpuIndex,\r
1056 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
1057 IN UINTN Width,\r
1058 IN CONST VOID *Buffer\r
1059 )\r
1060{\r
c1fcd80b
PB
1061 UINTN RegisterIndex;\r
1062 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
4036b4e5
PB
1063\r
1064 //\r
1065 // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored\r
1066 //\r
1067 if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {\r
1068 return EFI_SUCCESS;\r
1069 }\r
1070\r
1071 //\r
1072 // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported\r
1073 //\r
1074 if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {\r
1075 return EFI_NOT_FOUND;\r
1076 }\r
1077\r
1078 //\r
1079 // Convert Register to a register lookup table index. Let\r
1080 // PiSmmCpuDxeSmm implement other special registers (currently\r
1081 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).\r
1082 //\r
1083 RegisterIndex = GetRegisterIndex (Register);\r
1084 if (RegisterIndex == 0) {\r
b1bfdd65
LE
1085 return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?\r
1086 EFI_NOT_FOUND :\r
1087 EFI_UNSUPPORTED);\r
4036b4e5
PB
1088 }\r
1089\r
c1fcd80b 1090 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
4036b4e5
PB
1091\r
1092 //\r
1093 // Do not write non-writable SaveState, because it will cause exception.\r
b1bfdd65 1094 //\r
4036b4e5
PB
1095 if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {\r
1096 return EFI_UNSUPPORTED;\r
1097 }\r
1098\r
1099 //\r
1100 // Check CPU mode\r
1101 //\r
1102 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
1103 //\r
b1bfdd65
LE
1104 // If 32-bit mode width is zero, then the specified register can not be\r
1105 // accessed\r
4036b4e5
PB
1106 //\r
1107 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {\r
1108 return EFI_NOT_FOUND;\r
1109 }\r
1110\r
1111 //\r
b1bfdd65
LE
1112 // If Width is bigger than the 32-bit mode width, then the specified\r
1113 // register can not be accessed\r
4036b4e5
PB
1114 //\r
1115 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r
1116 return EFI_INVALID_PARAMETER;\r
1117 }\r
1118 //\r
1119 // Write SMM State register\r
1120 //\r
1121 ASSERT (CpuSaveState != NULL);\r
b1bfdd65
LE
1122 CopyMem (\r
1123 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,\r
1124 Buffer,\r
1125 Width\r
1126 );\r
4036b4e5
PB
1127 } else {\r
1128 //\r
b1bfdd65
LE
1129 // If 64-bit mode width is zero, then the specified register can not be\r
1130 // accessed\r
4036b4e5
PB
1131 //\r
1132 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {\r
1133 return EFI_NOT_FOUND;\r
1134 }\r
1135\r
1136 //\r
b1bfdd65
LE
1137 // If Width is bigger than the 64-bit mode width, then the specified\r
1138 // register can not be accessed\r
4036b4e5
PB
1139 //\r
1140 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {\r
1141 return EFI_INVALID_PARAMETER;\r
1142 }\r
1143\r
1144 //\r
1145 // Write lower 32-bits of SMM State register\r
1146 //\r
b1bfdd65
LE
1147 CopyMem (\r
1148 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,\r
1149 Buffer,\r
1150 MIN (4, Width)\r
1151 );\r
4036b4e5
PB
1152 if (Width >= 4) {\r
1153 //\r
1154 // Write upper 32-bits of SMM State register\r
1155 //\r
b1bfdd65
LE
1156 CopyMem (\r
1157 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,\r
1158 (UINT8 *)Buffer + 4,\r
1159 Width - 4\r
1160 );\r
4036b4e5
PB
1161 }\r
1162 }\r
1163 return EFI_SUCCESS;\r
86d71589
PB
1164}\r
1165\r
1166/**\r
1167 This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r
1168 notification is completely processed.\r
1169**/\r
1170VOID\r
1171EFIAPI\r
1172SmmCpuFeaturesCompleteSmmReadyToLock (\r
1173 VOID\r
1174 )\r
1175{\r
1176}\r
1177\r
1178/**\r
b1bfdd65
LE
1179 This API provides a method for a CPU to allocate a specific region for\r
1180 storing page tables.\r
86d71589
PB
1181\r
1182 This API can be called more once to allocate memory for page tables.\r
1183\r
b1bfdd65
LE
1184 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns\r
1185 a pointer to the allocated buffer. The buffer returned is aligned on a 4KB\r
1186 boundary. If Pages is 0, then NULL is returned. If there is not enough\r
1187 memory remaining to satisfy the request, then NULL is returned.\r
86d71589 1188\r
b1bfdd65
LE
1189 This function can also return NULL if there is no preference on where the\r
1190 page tables are allocated in SMRAM.\r
86d71589
PB
1191\r
1192 @param Pages The number of 4 KB pages to allocate.\r
1193\r
1194 @return A pointer to the allocated buffer for page tables.\r
1195 @retval NULL Fail to allocate a specific region for storing page tables,\r
b1bfdd65
LE
1196 Or there is no preference on where the page tables are\r
1197 allocated in SMRAM.\r
86d71589
PB
1198\r
1199**/\r
1200VOID *\r
1201EFIAPI\r
1202SmmCpuFeaturesAllocatePageTableMemory (\r
1203 IN UINTN Pages\r
1204 )\r
1205{\r
1206 return NULL;\r
1207}\r
1208\r