[mirror_edk2.git] / OvmfPkg / Library / SmmCpuFeaturesLib / SmmCpuFeaturesLib.c

/** @file\r
  The CPU specific programming for PiSmmCpuDxeSmm module.\r
\r
  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
**/\r
\r
#include <IndustryStandard/Q35MchIch9.h>\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/MemEncryptSevLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/SafeIntLib.h>\r
#include <Library/SmmCpuFeaturesLib.h>\r
#include <Library/SmmServicesTableLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Pcd/CpuHotEjectData.h>\r
#include <PiSmm.h>\r
#include <Register/Intel/SmramSaveStateMap.h>\r
#include <Register/QemuSmramSaveStateMap.h>\r
\r
//\r
// EFER register LMA bit\r
//\r
#define LMA BIT10\r
\r
/**\r
  The constructor function\r
\r
  @param[in]  ImageHandle  The firmware allocated handle for the EFI image.\r
  @param[in]  SystemTable  A pointer to the EFI System Table.\r
\r
  @retval EFI_SUCCESS      The constructor always returns EFI_SUCCESS.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmCpuFeaturesLibConstructor (\r
  IN EFI_HANDLE        ImageHandle,\r
  IN EFI_SYSTEM_TABLE  *SystemTable\r
  )\r
{\r
  //\r
  // No need to program SMRRs on our virtual platform.\r
  //\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Called during the very first SMI into System Management Mode to initialize\r
  CPU features, including SMBASE, for the currently executing CPU.  Since this\r
  is the first SMI, the SMRAM Save State Map is at the default address of\r
  SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET.  The currently executing\r
  CPU is specified by CpuIndex and CpuIndex can be used to access information\r
  about the currently executing CPU in the ProcessorInfo array and the\r
  HotPlugCpuData data structure.\r
\r
  @param[in] CpuIndex        The index of the CPU to initialize.  The value\r
                             must be between 0 and the NumberOfCpus field in\r
                             the System Management System Table (SMST).\r
  @param[in] IsMonarch       TRUE if the CpuIndex is the index of the CPU that\r
                             was elected as monarch during System Management\r
                             Mode initialization.\r
                             FALSE if the CpuIndex is not the index of the CPU\r
                             that was elected as monarch during System\r
                             Management Mode initialization.\r
  @param[in] ProcessorInfo   Pointer to an array of EFI_PROCESSOR_INFORMATION\r
                             structures.  ProcessorInfo[CpuIndex] contains the\r
                             information for the currently executing CPU.\r
  @param[in] CpuHotPlugData  Pointer to the CPU_HOT_PLUG_DATA structure that\r
                             contains the ApidId and SmBase arrays.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesInitializeProcessor (\r
  IN UINTN                      CpuIndex,\r
  IN BOOLEAN                    IsMonarch,\r
  IN EFI_PROCESSOR_INFORMATION  *ProcessorInfo,\r
  IN CPU_HOT_PLUG_DATA          *CpuHotPlugData\r
  )\r
{\r
  QEMU_SMRAM_SAVE_STATE_MAP  *CpuState;\r
\r
  //\r
  // Configure SMBASE.\r
  //\r
  CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(\r
                                            SMM_DEFAULT_SMBASE +\r
                                            SMRAM_SAVE_STATE_MAP_OFFSET\r
                                            );\r
  if ((CpuState->x86.SMMRevId & 0xFFFF) == 0) {\r
    CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
  } else {\r
    CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
  }\r
\r
  //\r
  // No need to program SMRRs on our virtual platform.\r
  //\r
}\r
\r
/**\r
  This function updates the SMRAM save state on the currently executing CPU\r
  to resume execution at a specific address after an RSM instruction.  This\r
  function must evaluate the SMRAM save state to determine the execution mode\r
  the RSM instruction resumes and update the resume execution address with\r
  either NewInstructionPointer32 or NewInstructionPoint.  The auto HALT restart\r
  flag in the SMRAM save state must always be cleared.  This function returns\r
  the value of the instruction pointer from the SMRAM save state that was\r
  replaced.  If this function returns 0, then the SMRAM save state was not\r
  modified.\r
\r
  This function is called during the very first SMI on each CPU after\r
  SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode\r
  to signal that the SMBASE of each CPU has been updated before the default\r
  SMBASE address is used for the first SMI to the next CPU.\r
\r
  @param[in] CpuIndex                 The index of the CPU to hook.  The value\r
                                      must be between 0 and the NumberOfCpus\r
                                      field in the System Management System\r
                                      Table (SMST).\r
  @param[in] CpuState                 Pointer to SMRAM Save State Map for the\r
                                      currently executing CPU.\r
  @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to\r
                                      32-bit execution mode from 64-bit SMM.\r
  @param[in] NewInstructionPointer    Instruction pointer to use if resuming to\r
                                      same execution mode as SMM.\r
\r
  @retval 0    This function did modify the SMRAM save state.\r
  @retval > 0  The original instruction pointer value from the SMRAM save state\r
               before it was replaced.\r
**/\r
UINT64\r
EFIAPI\r
SmmCpuFeaturesHookReturnFromSmm (\r
  IN UINTN                 CpuIndex,\r
  IN SMRAM_SAVE_STATE_MAP  *CpuState,\r
  IN UINT64                NewInstructionPointer32,\r
  IN UINT64                NewInstructionPointer\r
  )\r
{\r
  UINT64                      OriginalInstructionPointer;\r
  QEMU_SMRAM_SAVE_STATE_MAP   *CpuSaveState;\r
\r
  CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState;\r
  if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
    OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP;\r
    CpuSaveState->x86._EIP = (UINT32)NewInstructionPointer;\r
    //\r
    // Clear the auto HALT restart flag so the RSM instruction returns\r
    // program control to the instruction following the HLT instruction.\r
    //\r
    if ((CpuSaveState->x86.AutoHALTRestart & BIT0) != 0) {\r
      CpuSaveState->x86.AutoHALTRestart &= ~BIT0;\r
    }\r
  } else {\r
    OriginalInstructionPointer = CpuSaveState->x64._RIP;\r
    if ((CpuSaveState->x64.IA32_EFER & LMA) == 0) {\r
      CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer32;\r
    } else {\r
      CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer;\r
    }\r
    //\r
    // Clear the auto HALT restart flag so the RSM instruction returns\r
    // program control to the instruction following the HLT instruction.\r
    //\r
    if ((CpuSaveState->x64.AutoHALTRestart & BIT0) != 0) {\r
      CpuSaveState->x64.AutoHALTRestart &= ~BIT0;\r
    }\r
  }\r
  return OriginalInstructionPointer;\r
}\r
\r
STATIC CPU_HOT_EJECT_DATA *mCpuHotEjectData = NULL;\r
\r
/**\r
  Initialize mCpuHotEjectData if PcdCpuMaxLogicalProcessorNumber > 1.\r
\r
  Also setup the corresponding PcdCpuHotEjectDataAddress.\r
**/\r
STATIC\r
VOID\r
InitCpuHotEjectData (\r
  VOID\r
  )\r
{\r
  UINTN          Size;\r
  UINT32         Idx;\r
  UINT32         MaxNumberOfCpus;\r
  RETURN_STATUS  PcdStatus;\r
\r
  MaxNumberOfCpus = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
  if (MaxNumberOfCpus == 1) {\r
    return;\r
  }\r
\r
  //\r
  // We allocate CPU_HOT_EJECT_DATA and CPU_HOT_EJECT_DATA->QemuSelectorMap[]\r
  // in a single allocation, and explicitly align the QemuSelectorMap[] (which\r
  // is a UINT64 array) at its natural boundary.\r
  // Accordingly, allocate:\r
  //   sizeof(*mCpuHotEjectData) + (MaxNumberOfCpus * sizeof(UINT64))\r
  // and, add sizeof(UINT64) - 1 to use as padding if needed.\r
  //\r
\r
  if (RETURN_ERROR (SafeUintnMult (MaxNumberOfCpus, sizeof (UINT64), &Size)) ||\r
      RETURN_ERROR (SafeUintnAdd (Size, sizeof (*mCpuHotEjectData), &Size)) ||\r
      RETURN_ERROR (SafeUintnAdd (Size, sizeof (UINT64) - 1, &Size))) {\r
    DEBUG ((DEBUG_ERROR, "%a: invalid CPU_HOT_EJECT_DATA\n", __FUNCTION__));\r
    goto Fatal;\r
  }\r
\r
  mCpuHotEjectData = AllocatePool (Size);\r
  if (mCpuHotEjectData == NULL) {\r
    ASSERT (mCpuHotEjectData != NULL);\r
    goto Fatal;\r
  }\r
\r
  mCpuHotEjectData->Handler = NULL;\r
  mCpuHotEjectData->ArrayLength = MaxNumberOfCpus;\r
\r
  mCpuHotEjectData->QemuSelectorMap = ALIGN_POINTER (mCpuHotEjectData + 1,\r
                                        sizeof (UINT64));\r
  //\r
  // We use mCpuHotEjectData->QemuSelectorMap to map\r
  // ProcessorNum -> QemuSelector. Initialize to invalid values.\r
  //\r
  for (Idx = 0; Idx < mCpuHotEjectData->ArrayLength; Idx++) {\r
    mCpuHotEjectData->QemuSelectorMap[Idx] = CPU_EJECT_QEMU_SELECTOR_INVALID;\r
  }\r
\r
  //\r
  // Expose address of CPU Hot eject Data structure\r
  //\r
  PcdStatus = PcdSet64S (PcdCpuHotEjectDataAddress,\r
                (UINTN)(VOID *)mCpuHotEjectData);\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
\r
  return;\r
\r
Fatal:\r
  CpuDeadLoop ();\r
}\r
\r
/**\r
  Hook point in normal execution mode that allows the one CPU that was elected\r
  as monarch during System Management Mode initialization to perform additional\r
  initialization actions immediately after all of the CPUs have processed their\r
  first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE\r
  into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesSmmRelocationComplete (\r
  VOID\r
  )\r
{\r
  EFI_STATUS Status;\r
  UINTN      MapPagesBase;\r
  UINTN      MapPagesCount;\r
\r
\r
  InitCpuHotEjectData ();\r
\r
  if (!MemEncryptSevIsEnabled ()) {\r
    return;\r
  }\r
\r
  //\r
  // Now that SMBASE relocation is complete, re-encrypt the original SMRAM save\r
  // state map's container pages, and release the pages to DXE. (The pages were\r
  // allocated in PlatformPei.)\r
  //\r
  Status = MemEncryptSevLocateInitialSmramSaveStateMapPages (\r
             &MapPagesBase,\r
             &MapPagesCount\r
             );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  Status = MemEncryptSevSetPageEncMask (\r
             0,             // Cr3BaseAddress -- use current CR3\r
             MapPagesBase,  // BaseAddress\r
             MapPagesCount, // NumPages\r
             TRUE           // Flush\r
             );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "%a: MemEncryptSevSetPageEncMask(): %r\n",\r
      __FUNCTION__, Status));\r
    ASSERT (FALSE);\r
    CpuDeadLoop ();\r
  }\r
\r
  ZeroMem ((VOID *)MapPagesBase, EFI_PAGES_TO_SIZE (MapPagesCount));\r
\r
  if (PcdGetBool (PcdQ35SmramAtDefaultSmbase)) {\r
    //\r
    // The initial SMRAM Save State Map has been covered as part of a larger\r
    // reserved memory allocation in PlatformPei's InitializeRamRegions(). That\r
    // allocation is supposed to survive into OS runtime; we must not release\r
    // any part of it. Only re-assert the containment here.\r
    //\r
    ASSERT (SMM_DEFAULT_SMBASE <= MapPagesBase);\r
    ASSERT (\r
      (MapPagesBase + EFI_PAGES_TO_SIZE (MapPagesCount) <=\r
       SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE)\r
      );\r
  } else {\r
    Status = gBS->FreePages (MapPagesBase, MapPagesCount);\r
    ASSERT_EFI_ERROR (Status);\r
  }\r
}\r
\r
/**\r
  Return the size, in bytes, of a custom SMI Handler in bytes.  If 0 is\r
  returned, then a custom SMI handler is not provided by this library,\r
  and the default SMI handler must be used.\r
\r
  @retval 0    Use the default SMI handler.\r
  @retval > 0  Use the SMI handler installed by\r
               SmmCpuFeaturesInstallSmiHandler(). The caller is required to\r
               allocate enough SMRAM for each CPU to support the size of the\r
               custom SMI handler.\r
**/\r
UINTN\r
EFIAPI\r
SmmCpuFeaturesGetSmiHandlerSize (\r
  VOID\r
  )\r
{\r
  return 0;\r
}\r
\r
/**\r
  Install a custom SMI handler for the CPU specified by CpuIndex.  This\r
  function is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size\r
  is greater than zero and is called by the CPU that was elected as monarch\r
  during System Management Mode initialization.\r
\r
  @param[in] CpuIndex   The index of the CPU to install the custom SMI handler.\r
                        The value must be between 0 and the NumberOfCpus field\r
                        in the System Management System Table (SMST).\r
  @param[in] SmBase     The SMBASE address for the CPU specified by CpuIndex.\r
  @param[in] SmiStack   The stack to use when an SMI is processed by the\r
                        the CPU specified by CpuIndex.\r
  @param[in] StackSize  The size, in bytes, if the stack used when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] GdtBase    The base address of the GDT to use when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] GdtSize    The size, in bytes, of the GDT used when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] IdtBase    The base address of the IDT to use when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] IdtSize    The size, in bytes, of the IDT used when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] Cr3        The base address of the page tables to use when an SMI\r
                        is processed by the CPU specified by CpuIndex.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesInstallSmiHandler (\r
  IN UINTN   CpuIndex,\r
  IN UINT32  SmBase,\r
  IN VOID    *SmiStack,\r
  IN UINTN   StackSize,\r
  IN UINTN   GdtBase,\r
  IN UINTN   GdtSize,\r
  IN UINTN   IdtBase,\r
  IN UINTN   IdtSize,\r
  IN UINT32  Cr3\r
  )\r
{\r
}\r
\r
/**\r
  Determines if MTRR registers must be configured to set SMRAM cache-ability\r
  when executing in System Management Mode.\r
\r
  @retval TRUE   MTRR registers must be configured to set SMRAM cache-ability.\r
  @retval FALSE  MTRR registers do not need to be configured to set SMRAM\r
                 cache-ability.\r
**/\r
BOOLEAN\r
EFIAPI\r
SmmCpuFeaturesNeedConfigureMtrrs (\r
  VOID\r
  )\r
{\r
  return FALSE;\r
}\r
\r
/**\r
  Disable SMRR register if SMRR is supported and\r
  SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesDisableSmrr (\r
  VOID\r
  )\r
{\r
  //\r
  // No SMRR support, nothing to do\r
  //\r
}\r
\r
/**\r
  Enable SMRR register if SMRR is supported and\r
  SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesReenableSmrr (\r
  VOID\r
  )\r
{\r
  //\r
  // No SMRR support, nothing to do\r
  //\r
}\r
\r
/**\r
  Processor specific hook point each time a CPU enters System Management Mode.\r
\r
  @param[in] CpuIndex  The index of the CPU that has entered SMM.  The value\r
                       must be between 0 and the NumberOfCpus field in the\r
                       System Management System Table (SMST).\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesRendezvousEntry (\r
  IN UINTN  CpuIndex\r
  )\r
{\r
  //\r
  // No SMRR support, nothing to do\r
  //\r
}\r
\r
/**\r
  Processor specific hook point each time a CPU exits System Management Mode.\r
\r
  @param[in] CpuIndex  The index of the CPU that is exiting SMM.  The value\r
                       must be between 0 and the NumberOfCpus field in the\r
                       System Management System Table (SMST).\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesRendezvousExit (\r
  IN UINTN  CpuIndex\r
  )\r
{\r
  //\r
  // We only call the Handler if CPU hot-eject is enabled\r
  // (PcdCpuMaxLogicalProcessorNumber > 1), and hot-eject is needed\r
  // in this SMI exit (otherwise mCpuHotEjectData->Handler is not armed.)\r
  //\r
\r
  if (mCpuHotEjectData != NULL) {\r
    CPU_HOT_EJECT_HANDLER Handler;\r
\r
    //\r
    // As the comment above mentions, mCpuHotEjectData->Handler might be\r
    // written to on the BSP as part of handling of the CPU-ejection.\r
    //\r
    // We know that any initial assignment to mCpuHotEjectData->Handler\r
    // (on the BSP, in the CpuHotplugMmi() context) is ordered-before the\r
    // load below, since it is guaranteed to happen before the\r
    // control-dependency of the BSP's SMI exit signal -- by way of a store\r
    // to AllCpusInSync (on the BSP, in BspHandler()) and the corresponding\r
    // AllCpusInSync loop (on the APs, in SmiRendezvous()) which depends on\r
    // that store.\r
    //\r
    // This guarantees that these pieces of code can never execute\r
    // simultaneously. In addition, we ensure that the following load is\r
    // ordered-after the AllCpusInSync loop by using a MemoryFence() with\r
    // acquire semantics.\r
    //\r
    MemoryFence();\r
\r
    Handler = mCpuHotEjectData->Handler;\r
\r
    if (Handler != NULL) {\r
      Handler (CpuIndex);\r
    }\r
  }\r
}\r
\r
/**\r
  Check to see if an SMM register is supported by a specified CPU.\r
\r
  @param[in] CpuIndex  The index of the CPU to check for SMM register support.\r
                       The value must be between 0 and the NumberOfCpus field\r
                       in the System Management System Table (SMST).\r
  @param[in] RegName   Identifies the SMM register to check for support.\r
\r
  @retval TRUE   The SMM register specified by RegName is supported by the CPU\r
                 specified by CpuIndex.\r
  @retval FALSE  The SMM register specified by RegName is not supported by the\r
                 CPU specified by CpuIndex.\r
**/\r
BOOLEAN\r
EFIAPI\r
SmmCpuFeaturesIsSmmRegisterSupported (\r
  IN UINTN         CpuIndex,\r
  IN SMM_REG_NAME  RegName\r
  )\r
{\r
  ASSERT (RegName == SmmRegFeatureControl);\r
  return FALSE;\r
}\r
\r
/**\r
  Returns the current value of the SMM register for the specified CPU.\r
  If the SMM register is not supported, then 0 is returned.\r
\r
  @param[in] CpuIndex  The index of the CPU to read the SMM register.  The\r
                       value must be between 0 and the NumberOfCpus field in\r
                       the System Management System Table (SMST).\r
  @param[in] RegName   Identifies the SMM register to read.\r
\r
  @return  The value of the SMM register specified by RegName from the CPU\r
           specified by CpuIndex.\r
**/\r
UINT64\r
EFIAPI\r
SmmCpuFeaturesGetSmmRegister (\r
  IN UINTN         CpuIndex,\r
  IN SMM_REG_NAME  RegName\r
  )\r
{\r
  //\r
  // This is called for SmmRegSmmDelayed, SmmRegSmmBlocked, SmmRegSmmEnable.\r
  // The last of these should actually be SmmRegSmmDisable, so we can just\r
  // return FALSE.\r
  //\r
  return 0;\r
}\r
\r
/**\r
  Sets the value of an SMM register on a specified CPU.\r
  If the SMM register is not supported, then no action is performed.\r
\r
  @param[in] CpuIndex  The index of the CPU to write the SMM register.  The\r
                       value must be between 0 and the NumberOfCpus field in\r
                       the System Management System Table (SMST).\r
  @param[in] RegName   Identifies the SMM register to write.\r
                       registers are read-only.\r
  @param[in] Value     The value to write to the SMM register.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesSetSmmRegister (\r
  IN UINTN         CpuIndex,\r
  IN SMM_REG_NAME  RegName,\r
  IN UINT64        Value\r
  )\r
{\r
  ASSERT (FALSE);\r
}\r
\r
///\r
/// Macro used to simplify the lookup table entries of type\r
/// CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
///\r
#define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)\r
\r
///\r
/// Macro used to simplify the lookup table entries of type\r
/// CPU_SMM_SAVE_STATE_REGISTER_RANGE\r
///\r
#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }\r
\r
///\r
/// Structure used to describe a range of registers\r
///\r
typedef struct {\r
  EFI_SMM_SAVE_STATE_REGISTER  Start;\r
  EFI_SMM_SAVE_STATE_REGISTER  End;\r
  UINTN                        Length;\r
} CPU_SMM_SAVE_STATE_REGISTER_RANGE;\r
\r
///\r
/// Structure used to build a lookup table to retrieve the widths and offsets\r
/// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value\r
///\r
\r
#define SMM_SAVE_STATE_REGISTER_FIRST_INDEX             1\r
\r
typedef struct {\r
  UINT8   Width32;\r
  UINT8   Width64;\r
  UINT16  Offset32;\r
  UINT16  Offset64Lo;\r
  UINT16  Offset64Hi;\r
  BOOLEAN Writeable;\r
} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;\r
\r
///\r
/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER\r
/// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
///\r
STATIC CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {\r
  SMM_REGISTER_RANGE (\r
    EFI_SMM_SAVE_STATE_REGISTER_GDTBASE,\r
    EFI_SMM_SAVE_STATE_REGISTER_LDTINFO\r
    ),\r
  SMM_REGISTER_RANGE (\r
    EFI_SMM_SAVE_STATE_REGISTER_ES,\r
    EFI_SMM_SAVE_STATE_REGISTER_RIP\r
    ),\r
  SMM_REGISTER_RANGE (\r
    EFI_SMM_SAVE_STATE_REGISTER_RFLAGS,\r
    EFI_SMM_SAVE_STATE_REGISTER_CR4\r
    ),\r
  { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }\r
};\r
\r
///\r
/// Lookup table used to retrieve the widths and offsets associated with each\r
/// supported EFI_SMM_SAVE_STATE_REGISTER value\r
///\r
STATIC CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {\r
  {\r
    0,                                    // Width32\r
    0,                                    // Width64\r
    0,                                    // Offset32\r
    0,                                    // Offset64Lo\r
    0,                                    // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // Reserved\r
\r
  //\r
  // CPU Save State registers defined in PI SMM CPU Protocol.\r
  //\r
  {\r
    0,                                    // Width32\r
    8,                                    // Width64\r
    0,                                    // Offset32\r
    SMM_CPU_OFFSET (x64._GDTRBase),       // Offset64Lo\r
    SMM_CPU_OFFSET (x64._GDTRBase) + 4,   // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4\r
\r
  {\r
    0,                                    // Width32\r
    8,                                    // Width64\r
    0,                                    // Offset32\r
    SMM_CPU_OFFSET (x64._IDTRBase),       // Offset64Lo\r
    SMM_CPU_OFFSET (x64._IDTRBase) + 4,   // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5\r
\r
  {\r
    0,                                    // Width32\r
    8,                                    // Width64\r
    0,                                    // Offset32\r
    SMM_CPU_OFFSET (x64._LDTRBase),       // Offset64Lo\r
    SMM_CPU_OFFSET (x64._LDTRBase) + 4,   // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6\r
\r
  {\r
    0,                                    // Width32\r
    0,                                    // Width64\r
    0,                                    // Offset32\r
    SMM_CPU_OFFSET (x64._GDTRLimit),      // Offset64Lo\r
    SMM_CPU_OFFSET (x64._GDTRLimit) + 4,  // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7\r
\r
  {\r
    0,                                    // Width32\r
    0,                                    // Width64\r
    0,                                    // Offset32\r
    SMM_CPU_OFFSET (x64._IDTRLimit),      // Offset64Lo\r
    SMM_CPU_OFFSET (x64._IDTRLimit) + 4,  // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8\r
\r
  {\r
    0,                                    // Width32\r
    0,                                    // Width64\r
    0,                                    // Offset32\r
    SMM_CPU_OFFSET (x64._LDTRLimit),      // Offset64Lo\r
    SMM_CPU_OFFSET (x64._LDTRLimit) + 4,  // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9\r
\r
  {\r
    0,                                    // Width32\r
    0,                                    // Width64\r
    0,                                    // Offset32\r
    0,                                    // Offset64Lo\r
    0 + 4,                                // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10\r
\r
  {\r
    4,                                    // Width32\r
    4,                                    // Width64\r
    SMM_CPU_OFFSET (x86._ES),             // Offset32\r
    SMM_CPU_OFFSET (x64._ES),             // Offset64Lo\r
    0,                                    // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20\r
\r
  {\r
    4,                                    // Width32\r
    4,                                    // Width64\r
    SMM_CPU_OFFSET (x86._CS),             // Offset32\r
    SMM_CPU_OFFSET (x64._CS),             // Offset64Lo\r
    0,                                    // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21\r
\r
  {\r
    4,                                    // Width32\r
    4,                                    // Width64\r
    SMM_CPU_OFFSET (x86._SS),             // Offset32\r
    SMM_CPU_OFFSET (x64._SS),             // Offset64Lo\r
    0,                                    // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22\r
\r
  {\r
    4,                                    // Width32\r
    4,                                    // Width64\r
    SMM_CPU_OFFSET (x86._DS),             // Offset32\r
    SMM_CPU_OFFSET (x64._DS),             // Offset64Lo\r
    0,                                    // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23\r
\r
  {\r
    4,                                    // Width32\r
    4,                                    // Width64\r
    SMM_CPU_OFFSET (x86._FS),             // Offset32\r
    SMM_CPU_OFFSET (x64._FS),             // Offset64Lo\r
    0,                                    // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24\r
\r
  {\r
    4,                                    // Width32\r
    4,                                    // Width64\r
    SMM_CPU_OFFSET (x86._GS),             // Offset32\r
    SMM_CPU_OFFSET (x64._GS),             // Offset64Lo\r
    0,                                    // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25\r
\r
  {\r
    0,                                    // Width32\r
    4,                                    // Width64\r
    0,                                    // Offset32\r
    SMM_CPU_OFFSET (x64._LDTR),           // Offset64Lo\r
    0,                                    // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26\r
\r
  {\r
    4,                                    // Width32\r
    4,                                    // Width64\r
    SMM_CPU_OFFSET (x86._TR),             // Offset32\r
    SMM_CPU_OFFSET (x64._TR),             // Offset64Lo\r
    0,                                    // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27\r
\r
  {\r
    4,                                    // Width32\r
    8,                                    // Width64\r
    SMM_CPU_OFFSET (x86._DR7),            // Offset32\r
    SMM_CPU_OFFSET (x64._DR7),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._DR7) + 4,        // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28\r
\r
  {\r
    4,                                    // Width32\r
    8,                                    // Width64\r
    SMM_CPU_OFFSET (x86._DR6),            // Offset32\r
    SMM_CPU_OFFSET (x64._DR6),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._DR6) + 4,        // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29\r
\r
  {\r
    0,                                    // Width32\r
    8,                                    // Width64\r
    0,                                    // Offset32\r
    SMM_CPU_OFFSET (x64._R8),             // Offset64Lo\r
    SMM_CPU_OFFSET (x64._R8) + 4,         // Offset64Hi\r
    TRUE                                  // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30\r
\r
  {\r
    0,                                    // Width32\r
    8,                                    // Width64\r
    0,                                    // Offset32\r
    SMM_CPU_OFFSET (x64._R9),             // Offset64Lo\r
    SMM_CPU_OFFSET (x64._R9) + 4,         // Offset64Hi\r
    TRUE                                  // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31\r
\r
  {\r
    0,                                    // Width32\r
    8,                                    // Width64\r
    0,                                    // Offset32\r
    SMM_CPU_OFFSET (x64._R10),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._R10) + 4,        // Offset64Hi\r
    TRUE                                  // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32\r
\r
  {\r
    0,                                    // Width32\r
    8,                                    // Width64\r
    0,                                    // Offset32\r
    SMM_CPU_OFFSET (x64._R11),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._R11) + 4,        // Offset64Hi\r
    TRUE                                  // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33\r
\r
  {\r
    0,                                    // Width32\r
    8,                                    // Width64\r
    0,                                    // Offset32\r
    SMM_CPU_OFFSET (x64._R12),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._R12) + 4,        // Offset64Hi\r
    TRUE                                  // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34\r
\r
  {\r
    0,                                    // Width32\r
    8,                                    // Width64\r
    0,                                    // Offset32\r
    SMM_CPU_OFFSET (x64._R13),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._R13) + 4,        // Offset64Hi\r
    TRUE                                  // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35\r
\r
  {\r
    0,                                    // Width32\r
    8,                                    // Width64\r
    0,                                    // Offset32\r
    SMM_CPU_OFFSET (x64._R14),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._R14) + 4,        // Offset64Hi\r
    TRUE                                  // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36\r
\r
  {\r
    0,                                    // Width32\r
    8,                                    // Width64\r
    0,                                    // Offset32\r
    SMM_CPU_OFFSET (x64._R15),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._R15) + 4,        // Offset64Hi\r
    TRUE                                  // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37\r
\r
  {\r
    4,                                    // Width32\r
    8,                                    // Width64\r
    SMM_CPU_OFFSET (x86._EAX),            // Offset32\r
    SMM_CPU_OFFSET (x64._RAX),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._RAX) + 4,        // Offset64Hi\r
    TRUE                                  // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38\r
\r
  {\r
    4,                                    // Width32\r
    8,                                    // Width64\r
    SMM_CPU_OFFSET (x86._EBX),            // Offset32\r
    SMM_CPU_OFFSET (x64._RBX),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._RBX) + 4,        // Offset64Hi\r
    TRUE                                  // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39\r
\r
  {\r
    4,                                    // Width32\r
    8,                                    // Width64\r
    SMM_CPU_OFFSET (x86._ECX),            // Offset32\r
    SMM_CPU_OFFSET (x64._RCX),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._RCX) + 4,        // Offset64Hi\r
    TRUE                                  // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40\r
\r
  {\r
    4,                                    // Width32\r
    8,                                    // Width64\r
    SMM_CPU_OFFSET (x86._EDX),            // Offset32\r
    SMM_CPU_OFFSET (x64._RDX),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._RDX) + 4,        // Offset64Hi\r
    TRUE                                  // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41\r
\r
  {\r
    4,                                    // Width32\r
    8,                                    // Width64\r
    SMM_CPU_OFFSET (x86._ESP),            // Offset32\r
    SMM_CPU_OFFSET (x64._RSP),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._RSP) + 4,        // Offset64Hi\r
    TRUE                                  // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42\r
\r
  {\r
    4,                                    // Width32\r
    8,                                    // Width64\r
    SMM_CPU_OFFSET (x86._EBP),            // Offset32\r
    SMM_CPU_OFFSET (x64._RBP),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._RBP) + 4,        // Offset64Hi\r
    TRUE                                  // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43\r
\r
  {\r
    4,                                    // Width32\r
    8,                                    // Width64\r
    SMM_CPU_OFFSET (x86._ESI),            // Offset32\r
    SMM_CPU_OFFSET (x64._RSI),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._RSI) + 4,        // Offset64Hi\r
    TRUE                                  // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44\r
\r
  {\r
    4,                                    // Width32\r
    8,                                    // Width64\r
    SMM_CPU_OFFSET (x86._EDI),            // Offset32\r
    SMM_CPU_OFFSET (x64._RDI),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._RDI) + 4,        // Offset64Hi\r
    TRUE                                  // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45\r
\r
  {\r
    4,                                    // Width32\r
    8,                                    // Width64\r
    SMM_CPU_OFFSET (x86._EIP),            // Offset32\r
    SMM_CPU_OFFSET (x64._RIP),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._RIP) + 4,        // Offset64Hi\r
    TRUE                                  // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46\r
\r
  {\r
    4,                                    // Width32\r
    8,                                    // Width64\r
    SMM_CPU_OFFSET (x86._EFLAGS),         // Offset32\r
    SMM_CPU_OFFSET (x64._RFLAGS),         // Offset64Lo\r
    SMM_CPU_OFFSET (x64._RFLAGS) + 4,     // Offset64Hi\r
    TRUE                                  // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51\r
\r
  {\r
    4,                                    // Width32\r
    8,                                    // Width64\r
    SMM_CPU_OFFSET (x86._CR0),            // Offset32\r
    SMM_CPU_OFFSET (x64._CR0),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._CR0) + 4,        // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52\r
\r
  {\r
    4,                                    // Width32\r
    8,                                    // Width64\r
    SMM_CPU_OFFSET (x86._CR3),            // Offset32\r
    SMM_CPU_OFFSET (x64._CR3),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._CR3) + 4,        // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53\r
\r
  {\r
    0,                                    // Width32\r
    4,                                    // Width64\r
    0,                                    // Offset32\r
    SMM_CPU_OFFSET (x64._CR4),            // Offset64Lo\r
    SMM_CPU_OFFSET (x64._CR4) + 4,        // Offset64Hi\r
    FALSE                                 // Writeable\r
  }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54\r
};\r
\r
//\r
// No support for I/O restart\r
//\r
\r
/**\r
  Read information from the CPU save state.\r
\r
  @param  Register  Specifies the CPU register to read form the save state.\r
\r
  @retval 0   Register is not valid\r
  @retval >0  Index into mSmmCpuWidthOffset[] associated with Register\r
\r
**/\r
STATIC\r
UINTN\r
GetRegisterIndex (\r
  IN EFI_SMM_SAVE_STATE_REGISTER  Register\r
  )\r
{\r
  UINTN  Index;\r
  UINTN  Offset;\r
\r
  for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX;\r
       mSmmCpuRegisterRanges[Index].Length != 0;\r
       Index++) {\r
    if (Register >= mSmmCpuRegisterRanges[Index].Start &&\r
        Register <= mSmmCpuRegisterRanges[Index].End) {\r
      return Register - mSmmCpuRegisterRanges[Index].Start + Offset;\r
    }\r
    Offset += mSmmCpuRegisterRanges[Index].Length;\r
  }\r
  return 0;\r
}\r
\r
/**\r
  Read a CPU Save State register on the target processor.\r
\r
  This function abstracts the differences that whether the CPU Save State\r
  register is in the IA32 CPU Save State Map or X64 CPU Save State Map.\r
\r
  This function supports reading a CPU Save State register in SMBase relocation\r
  handler.\r
\r
  @param[in]  CpuIndex       Specifies the zero-based index of the CPU save\r
                             state.\r
  @param[in]  RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.\r
  @param[in]  Width          The number of bytes to read from the CPU save\r
                             state.\r
  @param[out] Buffer         Upon return, this holds the CPU register value\r
                             read from the save state.\r
\r
  @retval EFI_SUCCESS           The register was read from Save State.\r
  @retval EFI_NOT_FOUND         The register is not defined for the Save State\r
                                of Processor.\r
  @retval EFI_INVALID_PARAMTER  This or Buffer is NULL.\r
\r
**/\r
STATIC\r
EFI_STATUS\r
ReadSaveStateRegisterByIndex (\r
  IN UINTN   CpuIndex,\r
  IN UINTN   RegisterIndex,\r
  IN UINTN   Width,\r
  OUT VOID   *Buffer\r
  )\r
{\r
  QEMU_SMRAM_SAVE_STATE_MAP  *CpuSaveState;\r
\r
  CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
\r
  if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
    //\r
    // If 32-bit mode width is zero, then the specified register can not be\r
    // accessed\r
    //\r
    if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {\r
      return EFI_NOT_FOUND;\r
    }\r
\r
    //\r
    // If Width is bigger than the 32-bit mode width, then the specified\r
    // register can not be accessed\r
    //\r
    if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r
      return EFI_INVALID_PARAMETER;\r
    }\r
\r
    //\r
    // Write return buffer\r
    //\r
    ASSERT(CpuSaveState != NULL);\r
    CopyMem (\r
      Buffer,\r
      (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,\r
      Width\r
      );\r
  } else {\r
    //\r
    // If 64-bit mode width is zero, then the specified register can not be\r
    // accessed\r
    //\r
    if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {\r
      return EFI_NOT_FOUND;\r
    }\r
\r
    //\r
    // If Width is bigger than the 64-bit mode width, then the specified\r
    // register can not be accessed\r
    //\r
    if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {\r
      return EFI_INVALID_PARAMETER;\r
    }\r
\r
    //\r
    // Write lower 32-bits of return buffer\r
    //\r
    CopyMem (\r
      Buffer,\r
      (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,\r
      MIN (4, Width)\r
      );\r
    if (Width >= 4) {\r
      //\r
      // Write upper 32-bits of return buffer\r
      //\r
      CopyMem (\r
        (UINT8 *)Buffer + 4,\r
        (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,\r
        Width - 4\r
        );\r
    }\r
  }\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Read an SMM Save State register on the target processor.  If this function\r
  returns EFI_UNSUPPORTED, then the caller is responsible for reading the\r
  SMM Save Sate register.\r
\r
  @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The\r
                        value must be between 0 and the NumberOfCpus field in\r
                        the System Management System Table (SMST).\r
  @param[in]  Register  The SMM Save State register to read.\r
  @param[in]  Width     The number of bytes to read from the CPU save state.\r
  @param[out] Buffer    Upon return, this holds the CPU register value read\r
                        from the save state.\r
\r
  @retval EFI_SUCCESS           The register was read from Save State.\r
  @retval EFI_INVALID_PARAMTER  Buffer is NULL.\r
  @retval EFI_UNSUPPORTED       This function does not support reading\r
                                Register.\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmCpuFeaturesReadSaveStateRegister (\r
  IN  UINTN                        CpuIndex,\r
  IN  EFI_SMM_SAVE_STATE_REGISTER  Register,\r
  IN  UINTN                        Width,\r
  OUT VOID                         *Buffer\r
  )\r
{\r
  UINTN                       RegisterIndex;\r
  QEMU_SMRAM_SAVE_STATE_MAP  *CpuSaveState;\r
\r
  //\r
  // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA\r
  //\r
  if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {\r
    //\r
    // Only byte access is supported for this register\r
    //\r
    if (Width != 1) {\r
      return EFI_INVALID_PARAMETER;\r
    }\r
\r
    CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
\r
    //\r
    // Check CPU mode\r
    //\r
    if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
      *(UINT8 *)Buffer = 32;\r
    } else {\r
      *(UINT8 *)Buffer = 64;\r
    }\r
\r
    return EFI_SUCCESS;\r
  }\r
\r
  //\r
  // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO\r
  //\r
  if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {\r
    return EFI_NOT_FOUND;\r
  }\r
\r
  //\r
  // Convert Register to a register lookup table index.  Let\r
  // PiSmmCpuDxeSmm implement other special registers (currently\r
  // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).\r
  //\r
  RegisterIndex = GetRegisterIndex (Register);\r
  if (RegisterIndex == 0) {\r
    return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?\r
            EFI_NOT_FOUND :\r
            EFI_UNSUPPORTED);\r
  }\r
\r
  return ReadSaveStateRegisterByIndex (CpuIndex, RegisterIndex, Width, Buffer);\r
}\r
\r
/**\r
  Writes an SMM Save State register on the target processor.  If this function\r
  returns EFI_UNSUPPORTED, then the caller is responsible for writing the\r
  SMM Save Sate register.\r
\r
  @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The\r
                       value must be between 0 and the NumberOfCpus field in\r
                       the System Management System Table (SMST).\r
  @param[in] Register  The SMM Save State register to write.\r
  @param[in] Width     The number of bytes to write to the CPU save state.\r
  @param[in] Buffer    Upon entry, this holds the new CPU register value.\r
\r
  @retval EFI_SUCCESS           The register was written to Save State.\r
  @retval EFI_INVALID_PARAMTER  Buffer is NULL.\r
  @retval EFI_UNSUPPORTED       This function does not support writing\r
                                Register.\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmCpuFeaturesWriteSaveStateRegister (\r
  IN UINTN                        CpuIndex,\r
  IN EFI_SMM_SAVE_STATE_REGISTER  Register,\r
  IN UINTN                        Width,\r
  IN CONST VOID                   *Buffer\r
  )\r
{\r
  UINTN                       RegisterIndex;\r
  QEMU_SMRAM_SAVE_STATE_MAP  *CpuSaveState;\r
\r
  //\r
  // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored\r
  //\r
  if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  //\r
  // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported\r
  //\r
  if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {\r
    return EFI_NOT_FOUND;\r
  }\r
\r
  //\r
  // Convert Register to a register lookup table index.  Let\r
  // PiSmmCpuDxeSmm implement other special registers (currently\r
  // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).\r
  //\r
  RegisterIndex = GetRegisterIndex (Register);\r
  if (RegisterIndex == 0) {\r
    return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?\r
            EFI_NOT_FOUND :\r
            EFI_UNSUPPORTED);\r
  }\r
\r
  CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
\r
  //\r
  // Do not write non-writable SaveState, because it will cause exception.\r
  //\r
  if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  //\r
  // Check CPU mode\r
  //\r
  if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
    //\r
    // If 32-bit mode width is zero, then the specified register can not be\r
    // accessed\r
    //\r
    if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {\r
      return EFI_NOT_FOUND;\r
    }\r
\r
    //\r
    // If Width is bigger than the 32-bit mode width, then the specified\r
    // register can not be accessed\r
    //\r
    if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r
      return EFI_INVALID_PARAMETER;\r
    }\r
    //\r
    // Write SMM State register\r
    //\r
    ASSERT (CpuSaveState != NULL);\r
    CopyMem (\r
      (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,\r
      Buffer,\r
      Width\r
      );\r
  } else {\r
    //\r
    // If 64-bit mode width is zero, then the specified register can not be\r
    // accessed\r
    //\r
    if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {\r
      return EFI_NOT_FOUND;\r
    }\r
\r
    //\r
    // If Width is bigger than the 64-bit mode width, then the specified\r
    // register can not be accessed\r
    //\r
    if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {\r
      return EFI_INVALID_PARAMETER;\r
    }\r
\r
    //\r
    // Write lower 32-bits of SMM State register\r
    //\r
    CopyMem (\r
      (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,\r
      Buffer,\r
      MIN (4, Width)\r
      );\r
    if (Width >= 4) {\r
      //\r
      // Write upper 32-bits of SMM State register\r
      //\r
      CopyMem (\r
        (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,\r
        (UINT8 *)Buffer + 4,\r
        Width - 4\r
        );\r
    }\r
  }\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r
  notification is completely processed.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesCompleteSmmReadyToLock (\r
  VOID\r
  )\r
{\r
}\r
\r
/**\r
  This API provides a method for a CPU to allocate a specific region for\r
  storing page tables.\r
\r
  This API can be called more once to allocate memory for page tables.\r
\r
  Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns\r
  a pointer to the allocated buffer.  The buffer returned is aligned on a 4KB\r
  boundary.  If Pages is 0, then NULL is returned.  If there is not enough\r
  memory remaining to satisfy the request, then NULL is returned.\r
\r
  This function can also return NULL if there is no preference on where the\r
  page tables are allocated in SMRAM.\r
\r
  @param  Pages                 The number of 4 KB pages to allocate.\r
\r
  @return A pointer to the allocated buffer for page tables.\r
  @retval NULL      Fail to allocate a specific region for storing page tables,\r
                    Or there is no preference on where the page tables are\r
                    allocated in SMRAM.\r
\r
**/\r
VOID *\r
EFIAPI\r
SmmCpuFeaturesAllocatePageTableMemory (\r
  IN UINTN           Pages\r
  )\r
{\r
  return NULL;\r
}\r
\r