OvmfPkg: SmmCpuFeaturesLib: customize state save map format
[mirror_edk2.git] / OvmfPkg / Library / SmmCpuFeaturesLib / SmmCpuFeaturesLib.c
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1/** @file\r
2The CPU specific programming for PiSmmCpuDxeSmm module.\r
3\r
4Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
5This program and the accompanying materials\r
6are licensed and made available under the terms and conditions of the BSD License\r
7which accompanies this distribution. The full text of the license may be found at\r
8http://opensource.org/licenses/bsd-license.php\r
9\r
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include <PiSmm.h>\r
16#include <Library/SmmCpuFeaturesLib.h>\r
17#include <Library/BaseLib.h>\r
4036b4e5 18#include <Library/BaseMemoryLib.h>\r
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19#include <Library/PcdLib.h>\r
20#include <Library/MemoryAllocationLib.h>\r
4036b4e5 21#include <Library/SmmServicesTableLib.h>\r
86d71589 22#include <Library/DebugLib.h>\r
c1fcd80b 23#include <Register/QemuSmramSaveStateMap.h>\r
86d71589 24\r
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25//\r
26// EFER register LMA bit\r
27//\r
28#define LMA BIT10\r
29\r
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30/**\r
31 The constructor function\r
32\r
33 @param[in] ImageHandle The firmware allocated handle for the EFI image.\r
34 @param[in] SystemTable A pointer to the EFI System Table.\r
35\r
36 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r
37\r
38**/\r
39EFI_STATUS\r
40EFIAPI\r
41SmmCpuFeaturesLibConstructor (\r
42 IN EFI_HANDLE ImageHandle,\r
43 IN EFI_SYSTEM_TABLE *SystemTable\r
44 )\r
45{\r
86d71589 46 //\r
d7e71b29 47 // No need to program SMRRs on our virtual platform.\r
86d71589 48 //\r
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49 return EFI_SUCCESS;\r
50}\r
51\r
52/**\r
53 Called during the very first SMI into System Management Mode to initialize\r
54 CPU features, including SMBASE, for the currently executing CPU. Since this\r
55 is the first SMI, the SMRAM Save State Map is at the default address of\r
56 SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing\r
57 CPU is specified by CpuIndex and CpuIndex can be used to access information\r
58 about the currently executing CPU in the ProcessorInfo array and the\r
59 HotPlugCpuData data structure.\r
60\r
61 @param[in] CpuIndex The index of the CPU to initialize. The value\r
62 must be between 0 and the NumberOfCpus field in\r
63 the System Management System Table (SMST).\r
64 @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that\r
65 was elected as monarch during System Management\r
66 Mode initialization.\r
67 FALSE if the CpuIndex is not the index of the CPU\r
68 that was elected as monarch during System\r
69 Management Mode initialization.\r
70 @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION\r
71 structures. ProcessorInfo[CpuIndex] contains the\r
72 information for the currently executing CPU.\r
73 @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that\r
74 contains the ApidId and SmBase arrays.\r
75**/\r
76VOID\r
77EFIAPI\r
78SmmCpuFeaturesInitializeProcessor (\r
79 IN UINTN CpuIndex,\r
80 IN BOOLEAN IsMonarch,\r
81 IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,\r
82 IN CPU_HOT_PLUG_DATA *CpuHotPlugData\r
83 )\r
84{\r
c1fcd80b 85 QEMU_SMRAM_SAVE_STATE_MAP *CpuState;\r
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86\r
87 //\r
88 // Configure SMBASE.\r
89 //\r
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90 CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
91 if ((CpuState->x86.SMMRevId & 0xFFFF) == 0) {\r
92 CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
93 } else {\r
94 CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
95 }\r
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96\r
97 //\r
d7e71b29 98 // No need to program SMRRs on our virtual platform.\r
86d71589 99 //\r
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100}\r
101\r
102/**\r
103 This function updates the SMRAM save state on the currently executing CPU\r
104 to resume execution at a specific address after an RSM instruction. This\r
105 function must evaluate the SMRAM save state to determine the execution mode\r
106 the RSM instruction resumes and update the resume execution address with\r
107 either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart\r
108 flag in the SMRAM save state must always be cleared. This function returns\r
109 the value of the instruction pointer from the SMRAM save state that was\r
110 replaced. If this function returns 0, then the SMRAM save state was not\r
111 modified.\r
112\r
113 This function is called during the very first SMI on each CPU after\r
114 SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode\r
115 to signal that the SMBASE of each CPU has been updated before the default\r
116 SMBASE address is used for the first SMI to the next CPU.\r
117\r
118 @param[in] CpuIndex The index of the CPU to hook. The value\r
119 must be between 0 and the NumberOfCpus\r
120 field in the System Management System Table\r
121 (SMST).\r
122 @param[in] CpuState Pointer to SMRAM Save State Map for the\r
123 currently executing CPU.\r
124 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
125 32-bit execution mode from 64-bit SMM.\r
126 @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r
127 same execution mode as SMM.\r
128\r
129 @retval 0 This function did modify the SMRAM save state.\r
130 @retval > 0 The original instruction pointer value from the SMRAM save state\r
131 before it was replaced.\r
132**/\r
133UINT64\r
134EFIAPI\r
135SmmCpuFeaturesHookReturnFromSmm (\r
136 IN UINTN CpuIndex,\r
137 IN SMRAM_SAVE_STATE_MAP *CpuState,\r
138 IN UINT64 NewInstructionPointer32,\r
139 IN UINT64 NewInstructionPointer\r
140 )\r
141{\r
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142 UINT64 OriginalInstructionPointer;\r
143 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState;\r
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144\r
145 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
146 OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP;\r
147 CpuSaveState->x86._EIP = (UINT32)NewInstructionPointer;\r
148 //\r
149 // Clear the auto HALT restart flag so the RSM instruction returns\r
150 // program control to the instruction following the HLT instruction.\r
151 //\r
152 if ((CpuSaveState->x86.AutoHALTRestart & BIT0) != 0) {\r
153 CpuSaveState->x86.AutoHALTRestart &= ~BIT0;\r
154 }\r
155 } else {\r
156 OriginalInstructionPointer = CpuSaveState->x64._RIP;\r
157 if ((CpuSaveState->x64.IA32_EFER & LMA) == 0) {\r
158 CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer32;\r
159 } else {\r
160 CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer;\r
161 }\r
162 //\r
163 // Clear the auto HALT restart flag so the RSM instruction returns\r
164 // program control to the instruction following the HLT instruction.\r
165 //\r
166 if ((CpuSaveState->x64.AutoHALTRestart & BIT0) != 0) {\r
167 CpuSaveState->x64.AutoHALTRestart &= ~BIT0;\r
168 }\r
169 }\r
170 return OriginalInstructionPointer;\r
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171}\r
172\r
173/**\r
174 Hook point in normal execution mode that allows the one CPU that was elected\r
175 as monarch during System Management Mode initialization to perform additional\r
176 initialization actions immediately after all of the CPUs have processed their\r
177 first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE\r
178 into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().\r
179**/\r
180VOID\r
181EFIAPI\r
182SmmCpuFeaturesSmmRelocationComplete (\r
183 VOID\r
184 )\r
185{\r
186}\r
187\r
188/**\r
189 Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is\r
190 returned, then a custom SMI handler is not provided by this library,\r
191 and the default SMI handler must be used.\r
192\r
193 @retval 0 Use the default SMI handler.\r
194 @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()\r
195 The caller is required to allocate enough SMRAM for each CPU to\r
196 support the size of the custom SMI handler.\r
197**/\r
198UINTN\r
199EFIAPI\r
200SmmCpuFeaturesGetSmiHandlerSize (\r
201 VOID\r
202 )\r
203{\r
204 return 0;\r
205}\r
206\r
207/**\r
208 Install a custom SMI handler for the CPU specified by CpuIndex. This function\r
209 is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater\r
210 than zero and is called by the CPU that was elected as monarch during System\r
211 Management Mode initialization.\r
212\r
213 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r
214 The value must be between 0 and the NumberOfCpus field\r
215 in the System Management System Table (SMST).\r
216 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r
217 @param[in] SmiStack The stack to use when an SMI is processed by the\r
218 the CPU specified by CpuIndex.\r
219 @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r
220 processed by the CPU specified by CpuIndex.\r
221 @param[in] GdtBase The base address of the GDT to use when an SMI is\r
222 processed by the CPU specified by CpuIndex.\r
223 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r
224 processed by the CPU specified by CpuIndex.\r
225 @param[in] IdtBase The base address of the IDT to use when an SMI is\r
226 processed by the CPU specified by CpuIndex.\r
227 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r
228 processed by the CPU specified by CpuIndex.\r
229 @param[in] Cr3 The base address of the page tables to use when an SMI\r
230 is processed by the CPU specified by CpuIndex.\r
231**/\r
232VOID\r
233EFIAPI\r
234SmmCpuFeaturesInstallSmiHandler (\r
235 IN UINTN CpuIndex,\r
236 IN UINT32 SmBase,\r
237 IN VOID *SmiStack,\r
238 IN UINTN StackSize,\r
239 IN UINTN GdtBase,\r
240 IN UINTN GdtSize,\r
241 IN UINTN IdtBase,\r
242 IN UINTN IdtSize,\r
243 IN UINT32 Cr3\r
244 )\r
245{\r
246}\r
247\r
248/**\r
249 Determines if MTRR registers must be configured to set SMRAM cache-ability\r
250 when executing in System Management Mode.\r
251\r
252 @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.\r
253 @retval FALSE MTRR registers do not need to be configured to set SMRAM\r
254 cache-ability.\r
255**/\r
256BOOLEAN\r
257EFIAPI\r
258SmmCpuFeaturesNeedConfigureMtrrs (\r
259 VOID\r
260 )\r
261{\r
d7e71b29 262 return FALSE;\r
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263}\r
264\r
265/**\r
266 Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
267 returns TRUE.\r
268**/\r
269VOID\r
270EFIAPI\r
271SmmCpuFeaturesDisableSmrr (\r
272 VOID\r
273 )\r
274{\r
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275 //\r
276 // No SMRR support, nothing to do\r
277 //\r
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278}\r
279\r
280/**\r
281 Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
282 returns TRUE.\r
283**/\r
284VOID\r
285EFIAPI\r
286SmmCpuFeaturesReenableSmrr (\r
287 VOID\r
288 )\r
289{\r
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290 //\r
291 // No SMRR support, nothing to do\r
292 //\r
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293}\r
294\r
295/**\r
296 Processor specific hook point each time a CPU enters System Management Mode.\r
297\r
298 @param[in] CpuIndex The index of the CPU that has entered SMM. The value\r
299 must be between 0 and the NumberOfCpus field in the\r
300 System Management System Table (SMST).\r
301**/\r
302VOID\r
303EFIAPI\r
304SmmCpuFeaturesRendezvousEntry (\r
305 IN UINTN CpuIndex\r
306 )\r
307{\r
308 //\r
d7e71b29 309 // No SMRR support, nothing to do\r
86d71589 310 //\r
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311}\r
312\r
313/**\r
314 Processor specific hook point each time a CPU exits System Management Mode.\r
315\r
316 @param[in] CpuIndex The index of the CPU that is exiting SMM. The value must\r
317 be between 0 and the NumberOfCpus field in the System\r
318 Management System Table (SMST).\r
319**/\r
320VOID\r
321EFIAPI\r
322SmmCpuFeaturesRendezvousExit (\r
323 IN UINTN CpuIndex\r
324 )\r
325{\r
326}\r
327\r
328/**\r
329 Check to see if an SMM register is supported by a specified CPU.\r
330\r
331 @param[in] CpuIndex The index of the CPU to check for SMM register support.\r
332 The value must be between 0 and the NumberOfCpus field\r
333 in the System Management System Table (SMST).\r
334 @param[in] RegName Identifies the SMM register to check for support.\r
335\r
336 @retval TRUE The SMM register specified by RegName is supported by the CPU\r
337 specified by CpuIndex.\r
338 @retval FALSE The SMM register specified by RegName is not supported by the\r
339 CPU specified by CpuIndex.\r
340**/\r
341BOOLEAN\r
342EFIAPI\r
343SmmCpuFeaturesIsSmmRegisterSupported (\r
344 IN UINTN CpuIndex,\r
345 IN SMM_REG_NAME RegName\r
346 )\r
347{\r
d7e71b29 348 ASSERT (RegName == SmmRegFeatureControl);\r
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349 return FALSE;\r
350}\r
351\r
352/**\r
353 Returns the current value of the SMM register for the specified CPU.\r
354 If the SMM register is not supported, then 0 is returned.\r
355\r
356 @param[in] CpuIndex The index of the CPU to read the SMM register. The\r
357 value must be between 0 and the NumberOfCpus field in\r
358 the System Management System Table (SMST).\r
359 @param[in] RegName Identifies the SMM register to read.\r
360\r
361 @return The value of the SMM register specified by RegName from the CPU\r
362 specified by CpuIndex.\r
363**/\r
364UINT64\r
365EFIAPI\r
366SmmCpuFeaturesGetSmmRegister (\r
367 IN UINTN CpuIndex,\r
368 IN SMM_REG_NAME RegName\r
369 )\r
370{\r
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371 //\r
372 // This is called for SmmRegSmmDelayed, SmmRegSmmBlocked, SmmRegSmmEnable.\r
373 // The last of these should actually be SmmRegSmmDisable, so we can just\r
374 // return FALSE.\r
375 //\r
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376 return 0;\r
377}\r
378\r
379/**\r
380 Sets the value of an SMM register on a specified CPU.\r
381 If the SMM register is not supported, then no action is performed.\r
382\r
383 @param[in] CpuIndex The index of the CPU to write the SMM register. The\r
384 value must be between 0 and the NumberOfCpus field in\r
385 the System Management System Table (SMST).\r
386 @param[in] RegName Identifies the SMM register to write.\r
387 registers are read-only.\r
388 @param[in] Value The value to write to the SMM register.\r
389**/\r
390VOID\r
391EFIAPI\r
392SmmCpuFeaturesSetSmmRegister (\r
393 IN UINTN CpuIndex,\r
394 IN SMM_REG_NAME RegName,\r
395 IN UINT64 Value\r
396 )\r
397{\r
d7e71b29 398 ASSERT (FALSE);\r
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399}\r
400\r
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401///\r
402/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
403///\r
c1fcd80b 404#define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)\r
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405\r
406///\r
407/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE\r
408///\r
409#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }\r
410\r
411///\r
412/// Structure used to describe a range of registers\r
413///\r
414typedef struct {\r
415 EFI_SMM_SAVE_STATE_REGISTER Start;\r
416 EFI_SMM_SAVE_STATE_REGISTER End;\r
417 UINTN Length;\r
418} CPU_SMM_SAVE_STATE_REGISTER_RANGE;\r
419\r
420///\r
421/// Structure used to build a lookup table to retrieve the widths and offsets\r
422/// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value\r
423///\r
424\r
425#define SMM_SAVE_STATE_REGISTER_FIRST_INDEX 1\r
426\r
427typedef struct {\r
428 UINT8 Width32;\r
429 UINT8 Width64;\r
430 UINT16 Offset32;\r
431 UINT16 Offset64Lo;\r
432 UINT16 Offset64Hi;\r
433 BOOLEAN Writeable;\r
434} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;\r
435\r
436///\r
437/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER \r
438/// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
439///\r
440static CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {\r
441 SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO),\r
442 SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_STATE_REGISTER_RIP),\r
443 SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_STATE_REGISTER_CR4),\r
444 { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }\r
445};\r
446\r
447///\r
448/// Lookup table used to retrieve the widths and offsets associated with each \r
449/// supported EFI_SMM_SAVE_STATE_REGISTER value \r
450///\r
451static CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {\r
452 {0, 0, 0, 0, 0, FALSE}, // Reserved\r
453\r
454 //\r
455 // CPU Save State registers defined in PI SMM CPU Protocol.\r
456 //\r
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457 {0, 8, 0 , SMM_CPU_OFFSET (x64._GDTRBase) , SMM_CPU_OFFSET (x64._GDTRBase) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4\r
458 {0, 8, 0 , SMM_CPU_OFFSET (x64._IDTRBase) , SMM_CPU_OFFSET (x64._IDTRBase) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5\r
459 {0, 8, 0 , SMM_CPU_OFFSET (x64._LDTRBase) , SMM_CPU_OFFSET (x64._LDTRBase) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6\r
460 {0, 0, 0 , SMM_CPU_OFFSET (x64._GDTRLimit), SMM_CPU_OFFSET (x64._GDTRLimit) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7\r
461 {0, 0, 0 , SMM_CPU_OFFSET (x64._IDTRLimit), SMM_CPU_OFFSET (x64._IDTRLimit) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8\r
462 {0, 0, 0 , SMM_CPU_OFFSET (x64._LDTRLimit), SMM_CPU_OFFSET (x64._LDTRLimit) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9\r
463 {0, 0, 0 , 0 , 0 + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10\r
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464\r
465 {4, 4, SMM_CPU_OFFSET (x86._ES) , SMM_CPU_OFFSET (x64._ES) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20\r
466 {4, 4, SMM_CPU_OFFSET (x86._CS) , SMM_CPU_OFFSET (x64._CS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21\r
467 {4, 4, SMM_CPU_OFFSET (x86._SS) , SMM_CPU_OFFSET (x64._SS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22\r
468 {4, 4, SMM_CPU_OFFSET (x86._DS) , SMM_CPU_OFFSET (x64._DS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23\r
469 {4, 4, SMM_CPU_OFFSET (x86._FS) , SMM_CPU_OFFSET (x64._FS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24\r
470 {4, 4, SMM_CPU_OFFSET (x86._GS) , SMM_CPU_OFFSET (x64._GS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25\r
471 {0, 4, 0 , SMM_CPU_OFFSET (x64._LDTR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26\r
472 {4, 4, SMM_CPU_OFFSET (x86._TR) , SMM_CPU_OFFSET (x64._TR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27\r
473 {4, 8, SMM_CPU_OFFSET (x86._DR7) , SMM_CPU_OFFSET (x64._DR7) , SMM_CPU_OFFSET (x64._DR7) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28\r
474 {4, 8, SMM_CPU_OFFSET (x86._DR6) , SMM_CPU_OFFSET (x64._DR6) , SMM_CPU_OFFSET (x64._DR6) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29\r
475 {0, 8, 0 , SMM_CPU_OFFSET (x64._R8) , SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30\r
476 {0, 8, 0 , SMM_CPU_OFFSET (x64._R9) , SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31\r
477 {0, 8, 0 , SMM_CPU_OFFSET (x64._R10) , SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32\r
478 {0, 8, 0 , SMM_CPU_OFFSET (x64._R11) , SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33\r
479 {0, 8, 0 , SMM_CPU_OFFSET (x64._R12) , SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34\r
480 {0, 8, 0 , SMM_CPU_OFFSET (x64._R13) , SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35\r
481 {0, 8, 0 , SMM_CPU_OFFSET (x64._R14) , SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36\r
482 {0, 8, 0 , SMM_CPU_OFFSET (x64._R15) , SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37\r
483 {4, 8, SMM_CPU_OFFSET (x86._EAX) , SMM_CPU_OFFSET (x64._RAX) , SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38\r
484 {4, 8, SMM_CPU_OFFSET (x86._EBX) , SMM_CPU_OFFSET (x64._RBX) , SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39\r
485 {4, 8, SMM_CPU_OFFSET (x86._ECX) , SMM_CPU_OFFSET (x64._RCX) , SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40\r
486 {4, 8, SMM_CPU_OFFSET (x86._EDX) , SMM_CPU_OFFSET (x64._RDX) , SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41\r
487 {4, 8, SMM_CPU_OFFSET (x86._ESP) , SMM_CPU_OFFSET (x64._RSP) , SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42\r
488 {4, 8, SMM_CPU_OFFSET (x86._EBP) , SMM_CPU_OFFSET (x64._RBP) , SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43\r
489 {4, 8, SMM_CPU_OFFSET (x86._ESI) , SMM_CPU_OFFSET (x64._RSI) , SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44\r
490 {4, 8, SMM_CPU_OFFSET (x86._EDI) , SMM_CPU_OFFSET (x64._RDI) , SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45\r
491 {4, 8, SMM_CPU_OFFSET (x86._EIP) , SMM_CPU_OFFSET (x64._RIP) , SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46\r
492\r
493 {4, 8, SMM_CPU_OFFSET (x86._EFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51\r
494 {4, 8, SMM_CPU_OFFSET (x86._CR0) , SMM_CPU_OFFSET (x64._CR0) , SMM_CPU_OFFSET (x64._CR0) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52\r
495 {4, 8, SMM_CPU_OFFSET (x86._CR3) , SMM_CPU_OFFSET (x64._CR3) , SMM_CPU_OFFSET (x64._CR3) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53\r
c1fcd80b 496 {0, 4, 0 , SMM_CPU_OFFSET (x64._CR4) , SMM_CPU_OFFSET (x64._CR4) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54\r
4036b4e5
PB
497};\r
498\r
499//\r
500// No support for I/O restart\r
501//\r
502\r
503/**\r
504 Read information from the CPU save state.\r
505\r
506 @param Register Specifies the CPU register to read form the save state.\r
507\r
508 @retval 0 Register is not valid\r
509 @retval >0 Index into mSmmCpuWidthOffset[] associated with Register\r
510\r
511**/\r
512static UINTN\r
513GetRegisterIndex (\r
514 IN EFI_SMM_SAVE_STATE_REGISTER Register\r
515 )\r
516{\r
517 UINTN Index;\r
518 UINTN Offset;\r
519\r
520 for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX; mSmmCpuRegisterRanges[Index].Length != 0; Index++) {\r
521 if (Register >= mSmmCpuRegisterRanges[Index].Start && Register <= mSmmCpuRegisterRanges[Index].End) {\r
522 return Register - mSmmCpuRegisterRanges[Index].Start + Offset;\r
523 }\r
524 Offset += mSmmCpuRegisterRanges[Index].Length;\r
525 }\r
526 return 0;\r
527}\r
528\r
529/**\r
530 Read a CPU Save State register on the target processor.\r
531\r
532 This function abstracts the differences that whether the CPU Save State register is in the \r
533 IA32 CPU Save State Map or X64 CPU Save State Map.\r
534\r
535 This function supports reading a CPU Save State register in SMBase relocation handler.\r
536\r
537 @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
538 @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
539 @param[in] Width The number of bytes to read from the CPU save state.\r
540 @param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r
541\r
542 @retval EFI_SUCCESS The register was read from Save State.\r
543 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
544 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
545\r
546**/\r
547static EFI_STATUS\r
548ReadSaveStateRegisterByIndex (\r
549 IN UINTN CpuIndex,\r
550 IN UINTN RegisterIndex,\r
551 IN UINTN Width,\r
552 OUT VOID *Buffer\r
553 )\r
554{\r
c1fcd80b 555 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
4036b4e5 556\r
c1fcd80b 557 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
4036b4e5
PB
558\r
559 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
560 //\r
561 // If 32-bit mode width is zero, then the specified register can not be accessed\r
562 //\r
563 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {\r
564 return EFI_NOT_FOUND;\r
565 }\r
566\r
567 //\r
568 // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed\r
569 //\r
570 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r
571 return EFI_INVALID_PARAMETER;\r
572 }\r
573\r
574 //\r
575 // Write return buffer\r
576 //\r
577 ASSERT(CpuSaveState != NULL);\r
578 CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);\r
579 } else {\r
580 //\r
581 // If 64-bit mode width is zero, then the specified register can not be accessed\r
582 //\r
583 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {\r
584 return EFI_NOT_FOUND;\r
585 }\r
586\r
587 //\r
588 // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed\r
589 //\r
590 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {\r
591 return EFI_INVALID_PARAMETER;\r
592 }\r
593\r
594 //\r
595 // Write lower 32-bits of return buffer\r
596 //\r
597 CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN(4, Width));\r
598 if (Width >= 4) {\r
599 //\r
600 // Write upper 32-bits of return buffer\r
601 //\r
602 CopyMem((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);\r
603 }\r
604 }\r
605 return EFI_SUCCESS;\r
606}\r
607\r
86d71589
PB
608/**\r
609 Read an SMM Save State register on the target processor. If this function\r
610 returns EFI_UNSUPPORTED, then the caller is responsible for reading the\r
611 SMM Save Sate register.\r
612\r
613 @param[in] CpuIndex The index of the CPU to read the SMM Save State. The\r
614 value must be between 0 and the NumberOfCpus field in\r
615 the System Management System Table (SMST).\r
616 @param[in] Register The SMM Save State register to read.\r
617 @param[in] Width The number of bytes to read from the CPU save state.\r
618 @param[out] Buffer Upon return, this holds the CPU register value read\r
619 from the save state.\r
620\r
621 @retval EFI_SUCCESS The register was read from Save State.\r
622 @retval EFI_INVALID_PARAMTER Buffer is NULL.\r
623 @retval EFI_UNSUPPORTED This function does not support reading Register.\r
624\r
625**/\r
626EFI_STATUS\r
627EFIAPI\r
628SmmCpuFeaturesReadSaveStateRegister (\r
629 IN UINTN CpuIndex,\r
630 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
631 IN UINTN Width,\r
632 OUT VOID *Buffer\r
633 )\r
634{\r
c1fcd80b
PB
635 UINTN RegisterIndex;\r
636 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
4036b4e5
PB
637\r
638 //\r
639 // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA\r
640 //\r
641 if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {\r
642 //\r
643 // Only byte access is supported for this register\r
644 //\r
645 if (Width != 1) {\r
646 return EFI_INVALID_PARAMETER;\r
647 }\r
648\r
c1fcd80b 649 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
4036b4e5
PB
650\r
651 //\r
652 // Check CPU mode\r
653 //\r
654 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
655 *(UINT8 *)Buffer = 32;\r
656 } else {\r
657 *(UINT8 *)Buffer = 64;\r
658 }\r
659\r
660 return EFI_SUCCESS;\r
661 }\r
662\r
663 //\r
664 // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO\r
665 //\r
666 if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {\r
667 return EFI_NOT_FOUND;\r
668 }\r
669\r
670 //\r
671 // Convert Register to a register lookup table index. Let\r
672 // PiSmmCpuDxeSmm implement other special registers (currently\r
673 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).\r
674 //\r
675 RegisterIndex = GetRegisterIndex (Register);\r
676 if (RegisterIndex == 0) {\r
677 return Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? EFI_NOT_FOUND : EFI_UNSUPPORTED;\r
678 }\r
679\r
680 return ReadSaveStateRegisterByIndex (CpuIndex, RegisterIndex, Width, Buffer);\r
86d71589
PB
681}\r
682\r
683/**\r
684 Writes an SMM Save State register on the target processor. If this function\r
685 returns EFI_UNSUPPORTED, then the caller is responsible for writing the\r
686 SMM Save Sate register.\r
687\r
688 @param[in] CpuIndex The index of the CPU to write the SMM Save State. The\r
689 value must be between 0 and the NumberOfCpus field in\r
690 the System Management System Table (SMST).\r
691 @param[in] Register The SMM Save State register to write.\r
692 @param[in] Width The number of bytes to write to the CPU save state.\r
693 @param[in] Buffer Upon entry, this holds the new CPU register value.\r
694\r
695 @retval EFI_SUCCESS The register was written to Save State.\r
696 @retval EFI_INVALID_PARAMTER Buffer is NULL.\r
697 @retval EFI_UNSUPPORTED This function does not support writing Register.\r
698**/\r
699EFI_STATUS\r
700EFIAPI\r
701SmmCpuFeaturesWriteSaveStateRegister (\r
702 IN UINTN CpuIndex,\r
703 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
704 IN UINTN Width,\r
705 IN CONST VOID *Buffer\r
706 )\r
707{\r
c1fcd80b
PB
708 UINTN RegisterIndex;\r
709 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
4036b4e5
PB
710\r
711 //\r
712 // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored\r
713 //\r
714 if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {\r
715 return EFI_SUCCESS;\r
716 }\r
717\r
718 //\r
719 // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported\r
720 //\r
721 if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {\r
722 return EFI_NOT_FOUND;\r
723 }\r
724\r
725 //\r
726 // Convert Register to a register lookup table index. Let\r
727 // PiSmmCpuDxeSmm implement other special registers (currently\r
728 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).\r
729 //\r
730 RegisterIndex = GetRegisterIndex (Register);\r
731 if (RegisterIndex == 0) {\r
732 return Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? EFI_NOT_FOUND : EFI_UNSUPPORTED;\r
733 }\r
734\r
c1fcd80b 735 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
4036b4e5
PB
736\r
737 //\r
738 // Do not write non-writable SaveState, because it will cause exception.\r
739 // \r
740 if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {\r
741 return EFI_UNSUPPORTED;\r
742 }\r
743\r
744 //\r
745 // Check CPU mode\r
746 //\r
747 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
748 //\r
749 // If 32-bit mode width is zero, then the specified register can not be accessed\r
750 //\r
751 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {\r
752 return EFI_NOT_FOUND;\r
753 }\r
754\r
755 //\r
756 // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed\r
757 //\r
758 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r
759 return EFI_INVALID_PARAMETER;\r
760 }\r
761 //\r
762 // Write SMM State register\r
763 //\r
764 ASSERT (CpuSaveState != NULL);\r
765 CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);\r
766 } else {\r
767 //\r
768 // If 64-bit mode width is zero, then the specified register can not be accessed\r
769 //\r
770 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {\r
771 return EFI_NOT_FOUND;\r
772 }\r
773\r
774 //\r
775 // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed\r
776 //\r
777 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {\r
778 return EFI_INVALID_PARAMETER;\r
779 }\r
780\r
781 //\r
782 // Write lower 32-bits of SMM State register\r
783 //\r
784 CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));\r
785 if (Width >= 4) {\r
786 //\r
787 // Write upper 32-bits of SMM State register\r
788 //\r
789 CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);\r
790 }\r
791 }\r
792 return EFI_SUCCESS;\r
86d71589
PB
793}\r
794\r
795/**\r
796 This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r
797 notification is completely processed.\r
798**/\r
799VOID\r
800EFIAPI\r
801SmmCpuFeaturesCompleteSmmReadyToLock (\r
802 VOID\r
803 )\r
804{\r
805}\r
806\r
807/**\r
808 This API provides a method for a CPU to allocate a specific region for storing page tables.\r
809\r
810 This API can be called more once to allocate memory for page tables.\r
811\r
812 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
813 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r
814 is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r
815 returned.\r
816\r
817 This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.\r
818\r
819 @param Pages The number of 4 KB pages to allocate.\r
820\r
821 @return A pointer to the allocated buffer for page tables.\r
822 @retval NULL Fail to allocate a specific region for storing page tables,\r
823 Or there is no preference on where the page tables are allocated in SMRAM.\r
824\r
825**/\r
826VOID *\r
827EFIAPI\r
828SmmCpuFeaturesAllocatePageTableMemory (\r
829 IN UINTN Pages\r
830 )\r
831{\r
832 return NULL;\r
833}\r
834\r