]> git.proxmox.com Git - mirror_edk2.git/blame - OvmfPkg/QemuVideoDxe/Initialize.c
projects / mirror_edk2.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
OvmfPkg/QemuVideoDxe: child handles should have open parent protocol BY_CHILD_CONTROLLER
[mirror_edk2.git] / OvmfPkg / QemuVideoDxe / Initialize.c
CommitLineData
eaf4f336 1/** @file\r
2 Graphics Output Protocol functions for the QEMU video controller.\r
3\r
4 Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>\r
5\r
6 This program and the accompanying materials\r
7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#include "Qemu.h"\r
17\r
18\r
19///\r
20/// Generic Attribute Controller Register Settings\r
21///\r
22UINT8 AttributeController[21] = {\r
23 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,\r
24 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,\r
25 0x41, 0x00, 0x0F, 0x00, 0x00\r
26};\r
27\r
28///\r
29/// Generic Graphics Controller Register Settings\r
30///\r
31UINT8 GraphicsController[9] = {\r
32 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, 0xFF\r
33};\r
34\r
35//\r
36// 640 x 480 x 256 color @ 60 Hertz\r
37//\r
38UINT8 Crtc_640_480_256_60[28] = {\r
39 0x5d, 0x4f, 0x50, 0x82, 0x53, 0x9f, 0x00, 0x3e,\r
40 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
41 0xe1, 0x83, 0xdf, 0x50, 0x00, 0xe7, 0x04, 0xe3,\r
42 0xff, 0x00, 0x00, 0x22\r
43};\r
44\r
45UINT8 Crtc_640_480_32bpp_60[28] = {\r
46 0x5d, 0x4f, 0x50, 0x82, 0x53, 0x9f, 0x00, 0x3e,\r
47 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
48 0xe1, 0x83, 0xdf, 0x40, 0x00, 0xe7, 0x04, 0xe3,\r
49 0xff, 0x00, 0x00, 0x32\r
50};\r
51\r
52UINT16 Seq_640_480_256_60[15] = {\r
53 0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1107, 0x0008, 0x4a0b,\r
54 0x5b0c, 0x450d, 0x7e0e, 0x2b1b, 0x2f1c, 0x301d, 0x331e\r
55};\r
56\r
57UINT16 Seq_640_480_32bpp_60[15] = {\r
58 0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1907, 0x0008, 0x4a0b,\r
59 0x5b0c, 0x450d, 0x7e0e, 0x2b1b, 0x2f1c, 0x301d, 0x331e\r
60};\r
61\r
62//\r
63// 800 x 600 x 256 color @ 60 Hertz\r
64//\r
65UINT8 Crtc_800_600_256_60[28] = {\r
66 0x7F, 0x63, 0x64, 0x80, 0x6B, 0x1B, 0x72, 0xF0,\r
67 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
68 0x58, 0x8C, 0x57, 0x64, 0x00, 0x5F, 0x91, 0xE3,\r
69 0xFF, 0x00, 0x00, 0x22\r
70};\r
71\r
72UINT8 Crtc_800_600_32bpp_60[28] = {\r
73 0x7F, 0x63, 0x64, 0x80, 0x6B, 0x1B, 0x72, 0xF0,\r
74 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
75 0x58, 0x8C, 0x57, 0x90, 0x00, 0x5F, 0x91, 0xE3,\r
76 0xFF, 0x00, 0x00, 0x32\r
77};\r
78\r
79UINT16 Seq_800_600_256_60[15] = {\r
80 0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1107, 0x0008, 0x4a0b,\r
81 0x5b0c, 0x450d, 0x510e, 0x2b1b, 0x2f1c, 0x301d, 0x3a1e\r
82};\r
83\r
84UINT16 Seq_800_600_32bpp_60[15] = {\r
85 0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1907, 0x0008, 0x4a0b,\r
86 0x5b0c, 0x450d, 0x510e, 0x2b1b, 0x2f1c, 0x301d, 0x3a1e\r
87};\r
88\r
89UINT8 Crtc_960_720_32bpp_60[28] = {\r
90 0xA3, 0x77, 0x80, 0x86, 0x85, 0x96, 0x24, 0xFD,\r
91 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
92 0x02, 0x88, 0xCF, 0xe0, 0x00, 0x00, 0x64, 0xE3,\r
93 0xFF, 0x4A, 0x00, 0x32\r
94};\r
95\r
96UINT16 Seq_960_720_32bpp_60[15] = {\r
97 0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1907, 0x0008, 0x4a0b,\r
98 0x5b0c, 0x450d, 0x760e, 0x2b1b, 0x2f1c, 0x301d, 0x341e\r
99};\r
100\r
101//\r
102// 1024 x 768 x 256 color @ 60 Hertz\r
103//\r
104UINT8 Crtc_1024_768_256_60[28] = {\r
105 0xA3, 0x7F, 0x80, 0x86, 0x85, 0x96, 0x24, 0xFD,\r
106 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
107 0x02, 0x88, 0xFF, 0x80, 0x00, 0x00, 0x24, 0xE3,\r
108 0xFF, 0x4A, 0x00, 0x22\r
109};\r
110\r
111UINT16 Seq_1024_768_256_60[15] = {\r
112 0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1107, 0x0008, 0x4a0b,\r
113 0x5b0c, 0x450d, 0x760e, 0x2b1b, 0x2f1c, 0x301d, 0x341e\r
114};\r
115\r
116//\r
117// 1024 x 768 x 24-bit color @ 60 Hertz\r
118//\r
119UINT8 Crtc_1024_768_24bpp_60[28] = {\r
120 0xA3, 0x7F, 0x80, 0x86, 0x85, 0x96, 0x24, 0xFD,\r
121 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
122 0x02, 0x88, 0xFF, 0x80, 0x00, 0x00, 0x24, 0xE3,\r
123 0xFF, 0x4A, 0x00, 0x32\r
124};\r
125\r
126UINT16 Seq_1024_768_24bpp_60[15] = {\r
127 0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1507, 0x0008, 0x4a0b,\r
128 0x5b0c, 0x450d, 0x760e, 0x2b1b, 0x2f1c, 0x301d, 0x341e\r
129};\r
130\r
131UINT8 Crtc_1024_768_32bpp_60[28] = {\r
132 0xA3, 0x7F, 0x80, 0x86, 0x85, 0x96, 0x24, 0xFD,\r
133 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
134 0x02, 0x88, 0xFF, 0xe0, 0x00, 0x00, 0x64, 0xE3,\r
135 0xFF, 0x4A, 0x00, 0x32\r
136};\r
137\r
138UINT16 Seq_1024_768_32bpp_60[15] = {\r
139 0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1907, 0x0008, 0x4a0b,\r
140 0x5b0c, 0x450d, 0x760e, 0x2b1b, 0x2f1c, 0x301d, 0x341e\r
141};\r
142\r
143///\r
144/// Table of supported video modes\r
145///\r
212aac55 146QEMU_VIDEO_CIRRUS_MODES QemuVideoCirrusModes[] = {\r
eaf4f336 147// { 640, 480, 8, 60, Crtc_640_480_256_60, Seq_640_480_256_60, 0xe3 },\r
148// { 800, 600, 8, 60, Crtc_800_600_256_60, Seq_800_600_256_60, 0xef },\r
149 { 640, 480, 32, 60, Crtc_640_480_32bpp_60, Seq_640_480_32bpp_60, 0xef },\r
150 { 800, 600, 32, 60, Crtc_800_600_32bpp_60, Seq_800_600_32bpp_60, 0xef },\r
151// { 1024, 768, 8, 60, Crtc_1024_768_256_60, Seq_1024_768_256_60, 0xef }\r
152 { 1024, 768, 24, 60, Crtc_1024_768_24bpp_60, Seq_1024_768_24bpp_60, 0xef }\r
153// { 1024, 768, 32, 60, Crtc_1024_768_32bpp_60, Seq_1024_768_32bpp_60, 0xef }\r
154// { 960, 720, 32, 60, Crtc_960_720_32bpp_60, Seq_1024_768_32bpp_60, 0xef }\r
155};\r
156\r
212aac55 157#define QEMU_VIDEO_CIRRUS_MODE_COUNT \\r
158 (sizeof (QemuVideoCirrusModes) / sizeof (QemuVideoCirrusModes[0]))\r
eaf4f336 159\r
160/**\r
161 Construct the valid video modes for QemuVideo.\r
162\r
163**/\r
164EFI_STATUS\r
212aac55 165QemuVideoCirrusModeSetup (\r
eaf4f336 166 QEMU_VIDEO_PRIVATE_DATA *Private\r
167 )\r
168{\r
169 UINT32 Index;\r
170 QEMU_VIDEO_MODE_DATA *ModeData;\r
212aac55 171 QEMU_VIDEO_CIRRUS_MODES *VideoMode;\r
eaf4f336 172\r
173 //\r
174 // Setup Video Modes\r
175 //\r
176 Private->ModeData = AllocatePool (\r
212aac55 177 sizeof (Private->ModeData[0]) * QEMU_VIDEO_CIRRUS_MODE_COUNT\r
eaf4f336 178 );\r
179 ModeData = Private->ModeData;\r
212aac55 180 VideoMode = &QemuVideoCirrusModes[0];\r
181 for (Index = 0; Index < QEMU_VIDEO_CIRRUS_MODE_COUNT; Index ++) {\r
eaf4f336 182 ModeData->ModeNumber = Index;\r
183 ModeData->HorizontalResolution = VideoMode->Width;\r
184 ModeData->VerticalResolution = VideoMode->Height;\r
185 ModeData->ColorDepth = VideoMode->ColorDepth;\r
186 ModeData->RefreshRate = VideoMode->RefreshRate;\r
187 DEBUG ((EFI_D_INFO,\r
212aac55 188 "Adding Cirrus Video Mode %d: %dx%d, %d-bit, %d Hz\n",\r
eaf4f336 189 ModeData->ModeNumber,\r
190 ModeData->HorizontalResolution,\r
191 ModeData->VerticalResolution,\r
192 ModeData->ColorDepth,\r
193 ModeData->RefreshRate\r
194 ));\r
195\r
196 ModeData ++ ;\r
197 VideoMode ++;\r
198 }\r
212aac55 199 Private->MaxMode = QEMU_VIDEO_CIRRUS_MODE_COUNT;\r
eaf4f336 200\r
201 return EFI_SUCCESS;\r
202}\r
203\r
54f9b9ac 204///\r
205/// Table of supported video modes\r
206///\r
207QEMU_VIDEO_BOCHS_MODES QemuVideoBochsModes[] = {\r
208 { 640, 480, 32 },\r
209 { 800, 600, 32 },\r
210 { 1024, 768, 24 },\r
211};\r
212\r
213#define QEMU_VIDEO_BOCHS_MODE_COUNT \\r
214 (sizeof (QemuVideoBochsModes) / sizeof (QemuVideoBochsModes[0]))\r
215\r
216EFI_STATUS\r
217QemuVideoBochsModeSetup (\r
218 QEMU_VIDEO_PRIVATE_DATA *Private\r
219 )\r
220{\r
221 UINT32 Index;\r
222 QEMU_VIDEO_MODE_DATA *ModeData;\r
223 QEMU_VIDEO_BOCHS_MODES *VideoMode;\r
224\r
225 //\r
226 // Setup Video Modes\r
227 //\r
228 Private->ModeData = AllocatePool (\r
229 sizeof (Private->ModeData[0]) * QEMU_VIDEO_BOCHS_MODE_COUNT\r
230 );\r
231 ModeData = Private->ModeData;\r
232 VideoMode = &QemuVideoBochsModes[0];\r
233 for (Index = 0; Index < QEMU_VIDEO_BOCHS_MODE_COUNT; Index ++) {\r
234 ModeData->ModeNumber = Index;\r
235 ModeData->HorizontalResolution = VideoMode->Width;\r
236 ModeData->VerticalResolution = VideoMode->Height;\r
237 ModeData->ColorDepth = VideoMode->ColorDepth;\r
238 ModeData->RefreshRate = 60;\r
239 DEBUG ((EFI_D_INFO,\r
240 "Adding Bochs Video Mode %d: %dx%d, %d-bit, %d Hz\n",\r
241 ModeData->ModeNumber,\r
242 ModeData->HorizontalResolution,\r
243 ModeData->VerticalResolution,\r
244 ModeData->ColorDepth,\r
245 ModeData->RefreshRate\r
246 ));\r
247\r
248 ModeData ++ ;\r
249 VideoMode ++;\r
250 }\r
251 Private->MaxMode = QEMU_VIDEO_BOCHS_MODE_COUNT;\r
252\r
253 return EFI_SUCCESS;\r
254}\r
255\r
EFI Development Kit II mirror for PVE