PcAtChipsetPkg: Replace BSD License with BSD+Patent License

[mirror_edk2.git] / PcAtChipsetPkg / Include / Register / Hpet.h

/** @file\r
  HPET register definitions from the IA-PC HPET (High Precision Event Timers)\r
  Specification, Revision 1.0a, October 2004.\r
\r
  Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef __HPET_REGISTER_H__\r
#define __HPET_REGISTER_H__\r
\r
///\r
/// HPET General Register Offsets\r
///\r
#define HPET_GENERAL_CAPABILITIES_ID_OFFSET   0x000\r
#define HPET_GENERAL_CONFIGURATION_OFFSET     0x010\r
#define HPET_GENERAL_INTERRUPT_STATUS_OFFSET  0x020\r
\r
///\r
/// HPET Timer Register Offsets\r
///\r
#define HPET_MAIN_COUNTER_OFFSET              0x0F0\r
#define HPET_TIMER_CONFIGURATION_OFFSET       0x100\r
#define HPET_TIMER_COMPARATOR_OFFSET          0x108\r
#define HPET_TIMER_MSI_ROUTE_OFFSET           0x110\r
\r
///\r
/// Stride between sets of HPET Timer Registers\r
///\r
#define HPET_TIMER_STRIDE         0x20\r
\r
#pragma pack(1)\r
\r
///\r
/// HPET General Capabilities and ID Register\r
///\r
typedef union {\r
  struct {\r
    UINT32  Revision:8;\r
    UINT32  NumberOfTimers:5;\r
    UINT32  CounterSize:1;\r
    UINT32  Reserved0:1;\r
    UINT32  LegacyRoute:1;\r
    UINT32  VendorId:16;\r
    UINT32  CounterClockPeriod:32;\r
  } Bits;\r
  UINT64  Uint64;\r
} HPET_GENERAL_CAPABILITIES_ID_REGISTER;\r
\r
///\r
/// HPET General Configuration Register\r
///\r
typedef union {\r
  struct {\r
    UINT32  MainCounterEnable:1;\r
    UINT32  LegacyRouteEnable:1;\r
    UINT32  Reserved0:30;\r
    UINT32  Reserved1:32;\r
  } Bits;\r
  UINT64  Uint64;\r
} HPET_GENERAL_CONFIGURATION_REGISTER;\r
\r
///\r
/// HPET Timer Configuration Register\r
///\r
typedef union {\r
  struct {\r
    UINT32  Reserved0:1;\r
    UINT32  LevelTriggeredInterrupt:1;\r
    UINT32  InterruptEnable:1;\r
    UINT32  PeriodicInterruptEnable:1;\r
    UINT32  PeriodicInterruptCapablity:1;\r
    UINT32  CounterSizeCapablity:1;\r
    UINT32  ValueSetEnable:1;\r
    UINT32  Reserved1:1;\r
    UINT32  CounterSizeEnable:1;\r
    UINT32  InterruptRoute:5;\r
    UINT32  MsiInterruptEnable:1;\r
    UINT32  MsiInterruptCapablity:1;\r
    UINT32  Reserved2:16;\r
    UINT32  InterruptRouteCapability;\r
  } Bits;\r
  UINT64  Uint64;\r
} HPET_TIMER_CONFIGURATION_REGISTER;\r
\r
///\r
/// HPET Timer MSI Route Register\r
///\r
typedef union {\r
  struct {\r
    UINT32  Value:32;\r
    UINT32  Address:32;\r
  } Bits;\r
  UINT64  Uint64;\r
} HPET_TIMER_MSI_ROUTE_REGISTER;\r
\r
#pragma pack()\r
\r
#endif\r