PcAtChipsetPkg/Include/Register/Hpet.h

   1 /** @file
   2   HPET register definitions from the IA-PC HPET (High Precision Event Timers)
   3   Specification, Revision 1.0a, October 2004.
   4
   5   Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #ifndef __HPET_REGISTER_H__
  11 #define __HPET_REGISTER_H__
  12
  13 ///
  14 /// HPET General Register Offsets
  15 ///
  16 #define HPET_GENERAL_CAPABILITIES_ID_OFFSET   0x000
  17 #define HPET_GENERAL_CONFIGURATION_OFFSET     0x010
  18 #define HPET_GENERAL_INTERRUPT_STATUS_OFFSET  0x020
  19
  20 ///
  21 /// HPET Timer Register Offsets
  22 ///
  23 #define HPET_MAIN_COUNTER_OFFSET              0x0F0
  24 #define HPET_TIMER_CONFIGURATION_OFFSET       0x100
  25 #define HPET_TIMER_COMPARATOR_OFFSET          0x108
  26 #define HPET_TIMER_MSI_ROUTE_OFFSET           0x110
  27
  28 ///
  29 /// Stride between sets of HPET Timer Registers
  30 ///
  31 #define HPET_TIMER_STRIDE         0x20
  32
  33 #pragma pack(1)
  34
  35 ///
  36 /// HPET General Capabilities and ID Register
  37 ///
  38 typedef union {
  39   struct {
  40     UINT32  Revision:8;
  41     UINT32  NumberOfTimers:5;
  42     UINT32  CounterSize:1;
  43     UINT32  Reserved0:1;
  44     UINT32  LegacyRoute:1;
  45     UINT32  VendorId:16;
  46     UINT32  CounterClockPeriod:32;
  47   } Bits;
  48   UINT64  Uint64;
  49 } HPET_GENERAL_CAPABILITIES_ID_REGISTER;
  50
  51 ///
  52 /// HPET General Configuration Register
  53 ///
  54 typedef union {
  55   struct {
  56     UINT32  MainCounterEnable:1;
  57     UINT32  LegacyRouteEnable:1;
  58     UINT32  Reserved0:30;
  59     UINT32  Reserved1:32;
  60   } Bits;
  61   UINT64  Uint64;
  62 } HPET_GENERAL_CONFIGURATION_REGISTER;
  63
  64 ///
  65 /// HPET Timer Configuration Register
  66 ///
  67 typedef union {
  68   struct {
  69     UINT32  Reserved0:1;
  70     UINT32  LevelTriggeredInterrupt:1;
  71     UINT32  InterruptEnable:1;
  72     UINT32  PeriodicInterruptEnable:1;
  73     UINT32  PeriodicInterruptCapablity:1;
  74     UINT32  CounterSizeCapablity:1;
  75     UINT32  ValueSetEnable:1;
  76     UINT32  Reserved1:1;
  77     UINT32  CounterSizeEnable:1;
  78     UINT32  InterruptRoute:5;
  79     UINT32  MsiInterruptEnable:1;
  80     UINT32  MsiInterruptCapablity:1;
  81     UINT32  Reserved2:16;
  82     UINT32  InterruptRouteCapability;
  83   } Bits;
  84   UINT64  Uint64;
  85 } HPET_TIMER_CONFIGURATION_REGISTER;
  86
  87 ///
  88 /// HPET Timer MSI Route Register
  89 ///
  90 typedef union {
  91   struct {
  92     UINT32  Value:32;
  93     UINT32  Address:32;
  94   } Bits;
  95   UINT64  Uint64;
  96 } HPET_TIMER_MSI_ROUTE_REGISTER;
  97
  98 #pragma pack()
  99
 100 #endif