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1 | /** @file\r |
2 | Platform Pcie Helper Lib.\r | |
3 | \r | |
4 | Copyright (c) 2013 Intel Corporation.\r | |
5 | \r | |
6 | This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include "CommonHeader.h"\r | |
17 | \r | |
18 | //\r | |
19 | // Routines local to this source module.\r | |
20 | //\r | |
21 | VOID\r | |
22 | LegacyGpioSetLevel (\r | |
23 | IN CONST UINT32 LevelRegOffset,\r | |
24 | IN CONST UINT32 GpioNum,\r | |
25 | IN CONST BOOLEAN HighLevel\r | |
26 | )\r | |
27 | {\r | |
28 | UINT32 RegValue;\r | |
29 | UINT32 GpioBaseAddress;\r | |
30 | UINT32 GpioNumMask;\r | |
31 | \r | |
32 | GpioBaseAddress = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK;\r | |
33 | ASSERT (GpioBaseAddress > 0);\r | |
34 | \r | |
35 | RegValue = IoRead32 (GpioBaseAddress + LevelRegOffset);\r | |
36 | GpioNumMask = (1 << GpioNum);\r | |
37 | if (HighLevel) {\r | |
38 | RegValue |= (GpioNumMask);\r | |
39 | } else {\r | |
40 | RegValue &= ~(GpioNumMask);\r | |
41 | }\r | |
42 | IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGLVL_RESUME_WELL, RegValue);\r | |
43 | }\r | |
44 | \r | |
45 | //\r | |
46 | // Routines exported by this component.\r | |
47 | //\r | |
48 | \r | |
49 | /**\r | |
50 | Platform assert PCI express PERST# signal.\r | |
51 | \r | |
52 | @param PlatformType See EFI_PLATFORM_TYPE enum definitions.\r | |
53 | \r | |
54 | **/\r | |
55 | VOID\r | |
56 | EFIAPI\r | |
57 | PlatformPERSTAssert (\r | |
58 | IN CONST EFI_PLATFORM_TYPE PlatformType\r | |
59 | )\r | |
60 | {\r | |
61 | if (PlatformType == GalileoGen2) {\r | |
62 | LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO, FALSE);\r | |
63 | } else {\r | |
64 | LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, PCIEXP_PERST_RESUMEWELL_GPIO, FALSE);\r | |
65 | }\r | |
66 | }\r | |
67 | \r | |
68 | /**\r | |
69 | Platform de assert PCI express PERST# signal.\r | |
70 | \r | |
71 | @param PlatformType See EFI_PLATFORM_TYPE enum definitions.\r | |
72 | \r | |
73 | **/\r | |
74 | VOID\r | |
75 | EFIAPI\r | |
76 | PlatformPERSTDeAssert (\r | |
77 | IN CONST EFI_PLATFORM_TYPE PlatformType\r | |
78 | )\r | |
79 | {\r | |
80 | if (PlatformType == GalileoGen2) {\r | |
81 | LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO, TRUE);\r | |
82 | } else {\r | |
83 | LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, PCIEXP_PERST_RESUMEWELL_GPIO, TRUE);\r | |
84 | }\r | |
85 | }\r | |
86 | \r | |
87 | /** Early initialisation of the PCIe controller.\r | |
88 | \r | |
89 | @param PlatformType See EFI_PLATFORM_TYPE enum definitions.\r | |
90 | \r | |
91 | @retval EFI_SUCCESS Operation success.\r | |
92 | \r | |
93 | **/\r | |
94 | EFI_STATUS\r | |
95 | EFIAPI\r | |
96 | PlatformPciExpressEarlyInit (\r | |
97 | IN CONST EFI_PLATFORM_TYPE PlatformType\r | |
98 | )\r | |
99 | {\r | |
100 | \r | |
101 | //\r | |
102 | // Release and wait for PCI controller to come out of reset.\r | |
103 | //\r | |
104 | SocUnitReleasePcieControllerPreWaitPllLock (PlatformType);\r | |
105 | MicroSecondDelay (PCIEXP_DELAY_US_WAIT_PLL_LOCK);\r | |
106 | SocUnitReleasePcieControllerPostPllLock (PlatformType);\r | |
107 | \r | |
108 | //\r | |
109 | // Early PCIe initialisation\r | |
110 | //\r | |
111 | SocUnitEarlyInitialisation ();\r | |
112 | \r | |
113 | //\r | |
114 | // Do North cluster early PCIe init.\r | |
115 | //\r | |
116 | PciExpressEarlyInit ();\r | |
117 | \r | |
118 | return EFI_SUCCESS;\r | |
119 | }\r | |
120 | \r |