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1 | /** @file\r |
2 | System On Chip Unit (SOCUnit) routines.\r | |
3 | \r | |
4 | Copyright (c) 2013-2015 Intel Corporation.\r | |
5 | \r | |
6 | This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include "CommonHeader.h"\r | |
17 | \r | |
18 | /** Early initialisation of the SOC Unit\r | |
19 | \r | |
20 | @retval EFI_SUCCESS Operation success.\r | |
21 | \r | |
22 | **/\r | |
23 | EFI_STATUS\r | |
24 | EFIAPI\r | |
25 | SocUnitEarlyInitialisation (\r | |
26 | VOID\r | |
27 | )\r | |
28 | {\r | |
29 | UINT32 NewValue;\r | |
30 | \r | |
31 | //\r | |
32 | // Set the mixer load resistance\r | |
33 | //\r | |
34 | NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0);\r | |
35 | NewValue &= OCFGPIMIXLOAD_1_0_MASK;\r | |
36 | QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0, NewValue);\r | |
37 | \r | |
38 | NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1);\r | |
39 | NewValue &= OCFGPIMIXLOAD_1_0_MASK;\r | |
40 | QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1, NewValue);\r | |
41 | \r | |
42 | return EFI_SUCCESS;\r | |
43 | }\r | |
44 | \r | |
45 | /** Tasks to release PCI controller from reset pre wait for PLL Lock.\r | |
46 | \r | |
47 | @retval EFI_SUCCESS Operation success.\r | |
48 | \r | |
49 | **/\r | |
50 | EFI_STATUS\r | |
51 | EFIAPI\r | |
52 | SocUnitReleasePcieControllerPreWaitPllLock (\r | |
53 | IN CONST EFI_PLATFORM_TYPE PlatformType\r | |
54 | )\r | |
55 | {\r | |
56 | UINT32 NewValue;\r | |
57 | \r | |
58 | //\r | |
59 | // Assert PERST# and validate time assertion time.\r | |
60 | //\r | |
61 | PlatformPERSTAssert (PlatformType);\r | |
62 | ASSERT (PCIEXP_PERST_MIN_ASSERT_US <= (PCIEXP_DELAY_US_POST_CMNRESET_RESET + PCIEXP_DELAY_US_WAIT_PLL_LOCK + PCIEXP_DELAY_US_POST_SBI_RESET));\r | |
63 | \r | |
64 | //\r | |
65 | // PHY Common lane reset.\r | |
66 | //\r | |
67 | NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);\r | |
68 | NewValue |= SOCCLKEN_CONFIG_PHY_I_CMNRESET_L;\r | |
69 | QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);\r | |
70 | \r | |
71 | //\r | |
72 | // Wait post common lane reset.\r | |
73 | //\r | |
74 | MicroSecondDelay (PCIEXP_DELAY_US_POST_CMNRESET_RESET);\r | |
75 | \r | |
76 | //\r | |
77 | // PHY Sideband interface reset.\r | |
78 | // Controller main reset\r | |
79 | //\r | |
80 | NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);\r | |
81 | NewValue |= (SOCCLKEN_CONFIG_SBI_RST_100_CORE_B | SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L);\r | |
82 | QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);\r | |
83 | \r | |
84 | return EFI_SUCCESS;\r | |
85 | }\r | |
86 | \r | |
87 | /** Tasks to release PCI controller from reset after PLL has locked\r | |
88 | \r | |
89 | @retval EFI_SUCCESS Operation success.\r | |
90 | \r | |
91 | **/\r | |
92 | EFI_STATUS\r | |
93 | EFIAPI\r | |
94 | SocUnitReleasePcieControllerPostPllLock (\r | |
95 | IN CONST EFI_PLATFORM_TYPE PlatformType\r | |
96 | )\r | |
97 | {\r | |
98 | UINT32 NewValue;\r | |
99 | \r | |
100 | //\r | |
101 | // Controller sideband interface reset.\r | |
102 | //\r | |
103 | NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);\r | |
104 | NewValue |= SOCCLKEN_CONFIG_SBI_BB_RST_B;\r | |
105 | QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);\r | |
106 | \r | |
107 | //\r | |
108 | // Wait post sideband interface reset.\r | |
109 | //\r | |
110 | MicroSecondDelay (PCIEXP_DELAY_US_POST_SBI_RESET);\r | |
111 | \r | |
112 | //\r | |
113 | // Deassert PERST#.\r | |
114 | //\r | |
115 | PlatformPERSTDeAssert (PlatformType);\r | |
116 | \r | |
117 | //\r | |
118 | // Wait post de assert PERST#.\r | |
119 | //\r | |
120 | MicroSecondDelay (PCIEXP_DELAY_US_POST_PERST_DEASSERT);\r | |
121 | \r | |
122 | //\r | |
123 | // Controller primary interface reset.\r | |
124 | //\r | |
125 | NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);\r | |
126 | NewValue |= SOCCLKEN_CONFIG_BB_RST_B;\r | |
127 | QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);\r | |
128 | \r | |
129 | return EFI_SUCCESS;\r | |
130 | }\r | |
131 | \r |