[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / Include / DdrMemoryController.h

/** @file\r
Memory controller configuration.\r
\r
Copyright (c) 2013-2015 Intel Corporation.\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
#ifndef __DDR_MEMORY_CONTROLLER_H__\r
#define __DDR_MEMORY_CONTROLLER_H__\r
\r
//\r
// DDR timing data definitions.\r
// These are used to create bitmaps of valid timing configurations.\r
//\r
\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_FREQUENCY_UNKNOWN    0xFF\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_REFRESH_RATE_UNKNOWN 0xFF\r
\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_20    0x01\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_25    0x00\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_30    0x02\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_ALL   0x03\r
\r
\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_02   0x02\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_03   0x01\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_04   0x00\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_ALL  0x03\r
\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_02    0x02\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_03    0x01\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_04    0x00\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_ALL   0x03\r
\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_05   0x05\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_06   0x04\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_07   0x03\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_08   0x02\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_09   0x01\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_10   0x00\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_ALL  0x07\r
\r
#define DUAL_CHANNEL_DDR_DATA_TYPE_REGISTERED    0x01\r
#define DUAL_CHANNEL_DDR_DATA_TYPE_UNREGISTERED  0x02\r
#define DUAL_CHANNEL_DDR_DATA_TYPE_BUFFERED      0x04\r
#define DUAL_CHANNEL_DDR_DATA_TYPE_UNBUFFERED    0x08\r
#define DUAL_CHANNEL_DDR_DATA_TYPE_SDR           0x10\r
#define DUAL_CHANNEL_DDR_DATA_TYPE_DDR           0x20\r
\r
\r
//\r
// Maximum number of SDRAM channels supported by the memory controller\r
//\r
#define MAX_CHANNELS 1\r
\r
//\r
// Maximum number of DIMM sockets supported by the memory controller\r
//\r
#define MAX_SOCKETS 1\r
\r
//\r
// Maximum number of sides supported per DIMM\r
//\r
#define   MAX_SIDES                         2\r
\r
//\r
// Maximum number of "Socket Sets", where a "Socket Set is a set of matching\r
// DIMM's from the various channels\r
//\r
#define   MAX_SOCKET_SETS                   2\r
\r
//\r
// Maximum number of rows supported by the memory controller\r
//\r
#define MAX_ROWS (MAX_SIDES * MAX_SOCKETS)\r
\r
//\r
// Maximum number of memory ranges supported by the memory controller\r
//\r
#define MAX_RANGES (MAX_ROWS + 5)\r
\r
//\r
// Maximum Number of Log entries\r
//\r
#define   MEMORY_LOG_MAX_INDEX          16\r
\r
\r
typedef struct _MEMORY_LOG_ENTRY {\r
  EFI_STATUS_CODE_VALUE                     Event;\r
  EFI_STATUS_CODE_TYPE                      Severity;\r
  UINT8                                     Data;\r
} MEMORY_LOG_ENTRY;\r
\r
typedef struct _MEMORY_LOG {\r
  UINT8                                     Index;\r
  MEMORY_LOG_ENTRY                      Entry[MEMORY_LOG_MAX_INDEX];\r
} MEMORY_LOG;\r
\r
\r
\r
//\r
// Defined ECC types\r
//\r
#define DUAL_CHANNEL_DDR_ECC_TYPE_NONE             0x01   // No error checking\r
#define DUAL_CHANNEL_DDR_ECC_TYPE_EC               0x02   // Error checking only\r
#define DUAL_CHANNEL_DDR_ECC_TYPE_SECC             0x04   // Software Scrubbing ECC\r
#define DUAL_CHANNEL_DDR_ECC_TYPE_HECC             0x08   // Hardware Scrubbing ECC\r
#define DUAL_CHANNEL_DDR_ECC_TYPE_CKECC            0x10   // Chip Kill ECC\r
\r
//\r
// Row configuration status values\r
//\r
#define DUAL_CHANNEL_DDR_ROW_CONFIG_SUCCESS        0x00  // No error\r
#define DUAL_CHANNEL_DDR_ROW_CONFIG_UNKNOWN        0x01  // Pattern mismatch, no memory\r
#define DUAL_CHANNEL_DDR_ROW_CONFIG_UNSUPPORTED    0x02  // Memory type not supported\r
#define DUAL_CHANNEL_DDR_ROW_CONFIG_ADDRESS_ERROR  0x03  // Row/Col/Bnk mismatch\r
#define DUAL_CHANNEL_DDR_ROW_CONFIG_ECC_ERROR      0x04  // Received ECC error\r
#define DUAL_CHANNEL_DDR_ROW_CONFIG_NOT_PRESENT    0x05  // Row is not present\r
#define DUAL_CHANNEL_DDR_ROW_CONFIG_DISABLED       0x06  // Row is disabled\r
\r
\r
//\r
// Memory range types\r
//\r
typedef enum {\r
  DualChannelDdrMainMemory,\r
  DualChannelDdrSmramCacheable,\r
  DualChannelDdrSmramNonCacheable,\r
  DualChannelDdrGraphicsMemoryCacheable,\r
  DualChannelDdrGraphicsMemoryNonCacheable,\r
  DualChannelDdrReservedMemory,\r
  DualChannelDdrMaxMemoryRangeType\r
} DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;\r
\r
//\r
// Memory map range information\r
//\r
typedef struct {\r
  EFI_PHYSICAL_ADDRESS                          PhysicalAddress;\r
  EFI_PHYSICAL_ADDRESS                          CpuAddress;\r
  EFI_PHYSICAL_ADDRESS                          RangeLength;\r
  DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE                 Type;\r
} DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;\r
typedef struct {\r
    unsigned    dramType        :1;                 /**< Type: 0 = RESERVED; 1 = DDR2 */\r
    unsigned    dramWidth       :1;                 /**< Width: 0 = x8; 1 = x16 */\r
    unsigned    dramDensity     :2;                 /**< Density: 00b = 2Gb; 01b = 1Gb; 10b = 512Mb; 11b = 256Mb */\r
    unsigned    dramSpeed       :1;                 /**< Speed Grade: 0 = RESERVED; 1 = 800MT/s;*/\r
    unsigned    dramTimings     :3;                 /**< Timings: 4-4-4, 5-5-5, 6-6-6 */\r
    unsigned    dramRanks       :1;                 /**< Ranks: 0 = Single Rank; 1 = Dual Rank */\r
} DramGeometry;                                     /**< DRAM Geometry Descriptor */\r
\r
typedef union _RegDRP {\r
    UINT32    raw;\r
    struct {\r
        unsigned rank0Enabled       :1;     /**< Rank 0 Enable */\r
        unsigned rank0DevWidth      :2;     /**< DRAM Device Width (x8,x16) */\r
        unsigned rank0DevDensity    :2;     /**< DRAM Device Density (256Mb,512Mb,1Gb,2Gb) */\r
        unsigned reserved2          :1;\r
        unsigned rank1Enabled       :1;     /**< Rank 1 Enable */\r
        unsigned reserved3          :5;\r
        unsigned dramType           :1;     /**< DRAM Type (0=DDR2) */\r
        unsigned reserved4          :5;\r
        unsigned reserved5          :14;\r
      } field;\r
} RegDRP;                                   /**< DRAM Rank Population and Interface Register */\r
\r
\r
typedef union {\r
    UINT32    raw;\r
    struct {\r
        unsigned dramFrequency      :3;     /**< DRAM Frequency (000=RESERVED,010=667,011=800) */\r
        unsigned tRP                :2;     /**< Precharge to Activate Delay (3,4,5,6) */\r
        unsigned reserved1          :1;\r
        unsigned tRCD               :2;     /**< Activate to CAS Delay (3,4,5,6) */\r
        unsigned reserved2          :1;\r
        unsigned tCL                :2;     /**< CAS Latency (3,4,5,6) */\r
        unsigned reserved3          :21;\r
      } field;\r
} RegDTR0;                                  /**< DRAM Timing Register 0 */\r
\r
typedef union {\r
    UINT32    raw;\r
    struct {\r
        unsigned tWRRD_dly          :2;     /**< Additional Write to Read Delay (0,1,2,3) */\r
        unsigned reserved1          :1;\r
        unsigned tRDWR_dly          :2;     /**< Additional Read to Write Delay (0,1,2,3) */\r
        unsigned reserved2          :1;\r
        unsigned tRDRD_dr_dly       :1;     /**< Additional Read to Read Delay (1,2) */\r
        unsigned reserved3          :1;\r
        unsigned tRD_dly            :3;     /**< Additional Read Data Sampling Delay (0-7) */\r
        unsigned reserved4          :1;\r
        unsigned tRCVEN_halfclk_dly :4;     /**< Additional RCVEN Half Clock Delay Control */\r
        unsigned reserved5          :1;\r
        unsigned readDqDelay        :2;     /**< Read DQ Delay */\r
        unsigned reserved6          :13;\r
      } field;\r
} RegDTR1;                                  /**< DRAM Timing Register 1 */\r
\r
typedef union {\r
    UINT32    raw;\r
    struct {\r
        unsigned ckStaticDisable    :1;     /**< CK/CK# Static Disable */\r
        unsigned reserved1          :3;\r
        unsigned ckeStaticDisable   :2;     /**< CKE Static Disable */\r
        unsigned reserved2          :8;\r
        unsigned refreshPeriod      :2;     /**< Refresh Period (disabled,128clks,3.9us,7.8us) */\r
        unsigned refreshQueueDepth  :2;     /**< Refresh Queue Depth (1,2,4,8) */\r
        unsigned reserved5          :13;\r
        unsigned initComplete       :1;     /**< Initialization Complete */\r
      } field;\r
} RegDCO;\r
\r
//\r
// MRC Data Structure\r
//\r
typedef struct {\r
    RegDRP          drp;\r
    RegDTR0         dtr0;\r
    RegDTR1         dtr1;\r
    RegDCO          dco;\r
    UINT32          reg0104;\r
    UINT32          reg0120;\r
    UINT32          reg0121;\r
    UINT32          reg0123;\r
    UINT32          reg0111;\r
    UINT32          reg0130;\r
    UINT8           refreshPeriod;      /**< Placeholder for the chosen refresh\r
                                         *   period.  This value will NOT be\r
                                         *   programmed into DCO until all\r
                                         *   initialization is done.\r
                                         */\r
    UINT8           ddr2Odt;            /**< 0 = Disabled, 1 = 75 ohm, 2 = 150ohm, 3 = 50ohm */\r
    UINT8           sku;                /**< Detected QuarkNcSocId SKU */\r
    UINT8           capabilities;       /**< Capabilities Available on this part */\r
    UINT8           state;              /**< NORMAL_BOOT, S3_RESUME */\r
    UINT32          memSize;            /**< Memory size */\r
    UINT16          pmBase;             /**< PM Base */\r
    UINT16          mrcVersion;         /**< MRC Version */\r
    UINT32          hecbase;            /**< HECBASE shifted left 16 bits */\r
    DramGeometry    geometry;          /**< DRAM Geometry */\r
} MRC_DATA_STRUCTURE;             /**< QuarkNcSocId Memory Parameters for MRC */\r
\r
typedef struct _EFI_MEMINIT_CONFIG_DATA {\r
  MRC_DATA_STRUCTURE                        MrcData;\r
} EFI_MEMINIT_CONFIG_DATA;\r
\r
\r
\r
#endif\r
Commit	Line	Data
9b6bbcdb MK	1	/** @file\r
	2	Memory controller configuration.\r
	3	\r
	4	Copyright (c) 2013-2015 Intel Corporation.\r
	5	\r
c9f231d0	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
9b6bbcdb MK	7	\r
	8	**/\r
	9	#ifndef __DDR_MEMORY_CONTROLLER_H__\r
	10	#define __DDR_MEMORY_CONTROLLER_H__\r
	11	\r
	12	//\r
	13	// DDR timing data definitions.\r
	14	// These are used to create bitmaps of valid timing configurations.\r
	15	//\r
	16	\r
	17	#define DUAL_CHANNEL_DDR_TIMING_DATA_FREQUENCY_UNKNOWN 0xFF\r
	18	#define DUAL_CHANNEL_DDR_TIMING_DATA_REFRESH_RATE_UNKNOWN 0xFF\r
	19	\r
	20	#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_20 0x01\r
	21	#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_25 0x00\r
	22	#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_30 0x02\r
	23	#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_ALL 0x03\r
	24	\r
	25	\r
	26	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_02 0x02\r
	27	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_03 0x01\r
	28	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_04 0x00\r
	29	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_ALL 0x03\r
	30	\r
	31	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_02 0x02\r
	32	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_03 0x01\r
	33	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_04 0x00\r
	34	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_ALL 0x03\r
	35	\r
	36	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_05 0x05\r
	37	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_06 0x04\r
	38	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_07 0x03\r
	39	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_08 0x02\r
	40	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_09 0x01\r
	41	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_10 0x00\r
	42	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_ALL 0x07\r
	43	\r
	44	#define DUAL_CHANNEL_DDR_DATA_TYPE_REGISTERED 0x01\r
	45	#define DUAL_CHANNEL_DDR_DATA_TYPE_UNREGISTERED 0x02\r
	46	#define DUAL_CHANNEL_DDR_DATA_TYPE_BUFFERED 0x04\r
	47	#define DUAL_CHANNEL_DDR_DATA_TYPE_UNBUFFERED 0x08\r
	48	#define DUAL_CHANNEL_DDR_DATA_TYPE_SDR 0x10\r
	49	#define DUAL_CHANNEL_DDR_DATA_TYPE_DDR 0x20\r
	50	\r
	51	\r
	52	//\r
	53	// Maximum number of SDRAM channels supported by the memory controller\r
	54	//\r
	55	#define MAX_CHANNELS 1\r
	56	\r
	57	//\r
	58	// Maximum number of DIMM sockets supported by the memory controller\r
	59	//\r
	60	#define MAX_SOCKETS 1\r
	61	\r
	62	//\r
	63	// Maximum number of sides supported per DIMM\r
	64	//\r
	65	#define MAX_SIDES 2\r
	66	\r
	67	//\r
	68	// Maximum number of "Socket Sets", where a "Socket Set is a set of matching\r
	69	// DIMM's from the various channels\r
	70	//\r
71	#define MAX_SOCKET_SETS 2\r
72	\r
73	//\r
74	// Maximum number of rows supported by the memory controller\r
75	//\r
76	#define MAX_ROWS (MAX_SIDES * MAX_SOCKETS)\r
77	\r
78	//\r
79	// Maximum number of memory ranges supported by the memory controller\r
80	//\r
81	#define MAX_RANGES (MAX_ROWS + 5)\r
82	\r
83	//\r
84	// Maximum Number of Log entries\r
85	//\r
86	#define MEMORY_LOG_MAX_INDEX 16\r
87	\r
88	\r
89	typedef struct _MEMORY_LOG_ENTRY {\r
90	EFI_STATUS_CODE_VALUE Event;\r
91	EFI_STATUS_CODE_TYPE Severity;\r
92	UINT8 Data;\r
93	} MEMORY_LOG_ENTRY;\r
94	\r
95	typedef struct _MEMORY_LOG {\r
96	UINT8 Index;\r
97	MEMORY_LOG_ENTRY Entry[MEMORY_LOG_MAX_INDEX];\r
98	} MEMORY_LOG;\r
99	\r
100	\r
101	\r
102	//\r
103	// Defined ECC types\r
104	//\r
105	#define DUAL_CHANNEL_DDR_ECC_TYPE_NONE 0x01 // No error checking\r
106	#define DUAL_CHANNEL_DDR_ECC_TYPE_EC 0x02 // Error checking only\r
107	#define DUAL_CHANNEL_DDR_ECC_TYPE_SECC 0x04 // Software Scrubbing ECC\r
108	#define DUAL_CHANNEL_DDR_ECC_TYPE_HECC 0x08 // Hardware Scrubbing ECC\r
109	#define DUAL_CHANNEL_DDR_ECC_TYPE_CKECC 0x10 // Chip Kill ECC\r
110	\r
111	//\r
112	// Row configuration status values\r
113	//\r
114	#define DUAL_CHANNEL_DDR_ROW_CONFIG_SUCCESS 0x00 // No error\r
115	#define DUAL_CHANNEL_DDR_ROW_CONFIG_UNKNOWN 0x01 // Pattern mismatch, no memory\r
116	#define DUAL_CHANNEL_DDR_ROW_CONFIG_UNSUPPORTED 0x02 // Memory type not supported\r
117	#define DUAL_CHANNEL_DDR_ROW_CONFIG_ADDRESS_ERROR 0x03 // Row/Col/Bnk mismatch\r
118	#define DUAL_CHANNEL_DDR_ROW_CONFIG_ECC_ERROR 0x04 // Received ECC error\r
119	#define DUAL_CHANNEL_DDR_ROW_CONFIG_NOT_PRESENT 0x05 // Row is not present\r
120	#define DUAL_CHANNEL_DDR_ROW_CONFIG_DISABLED 0x06 // Row is disabled\r
121	\r
122	\r
123	//\r
124	// Memory range types\r
125	//\r
126	typedef enum {\r
127	DualChannelDdrMainMemory,\r
128	DualChannelDdrSmramCacheable,\r
129	DualChannelDdrSmramNonCacheable,\r
130	DualChannelDdrGraphicsMemoryCacheable,\r
131	DualChannelDdrGraphicsMemoryNonCacheable,\r
132	DualChannelDdrReservedMemory,\r
133	DualChannelDdrMaxMemoryRangeType\r
134	} DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;\r
135	\r
136	//\r
137	// Memory map range information\r
138	//\r
139	typedef struct {\r
140	EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
141	EFI_PHYSICAL_ADDRESS CpuAddress;\r
142	EFI_PHYSICAL_ADDRESS RangeLength;\r
143	DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE Type;\r
144	} DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;\r
145	typedef struct {\r
146	unsigned dramType :1; /*< Type: 0 = RESERVED; 1 = DDR2 /\r
147	unsigned dramWidth :1; /*< Width: 0 = x8; 1 = x16 /\r
148	unsigned dramDensity :2; /*< Density: 00b = 2Gb; 01b = 1Gb; 10b = 512Mb; 11b = 256Mb /\r
149	unsigned dramSpeed :1; /*< Speed Grade: 0 = RESERVED; 1 = 800MT/s;/\r
150	unsigned dramTimings :3; /*< Timings: 4-4-4, 5-5-5, 6-6-6 /\r
151	unsigned dramRanks :1; /*< Ranks: 0 = Single Rank; 1 = Dual Rank /\r
152	} DramGeometry; /*< DRAM Geometry Descriptor /\r
153	\r
154	typedef union _RegDRP {\r
155	UINT32 raw;\r
156	struct {\r
157	unsigned rank0Enabled :1; /*< Rank 0 Enable /\r
158	unsigned rank0DevWidth :2; /*< DRAM Device Width (x8,x16) /\r
159	unsigned rank0DevDensity :2; /*< DRAM Device Density (256Mb,512Mb,1Gb,2Gb) /\r
160	unsigned reserved2 :1;\r
161	unsigned rank1Enabled :1; /*< Rank 1 Enable /\r
162	unsigned reserved3 :5;\r
163	unsigned dramType :1; /*< DRAM Type (0=DDR2) /\r
164	unsigned reserved4 :5;\r
165	unsigned reserved5 :14;\r
166	} field;\r
167	} RegDRP; /*< DRAM Rank Population and Interface Register /\r
168	\r
169	\r
170	typedef union {\r
171	UINT32 raw;\r
172	struct {\r
173	unsigned dramFrequency :3; /*< DRAM Frequency (000=RESERVED,010=667,011=800) /\r
174	unsigned tRP :2; /*< Precharge to Activate Delay (3,4,5,6) /\r
175	unsigned reserved1 :1;\r
176	unsigned tRCD :2; /*< Activate to CAS Delay (3,4,5,6) /\r
177	unsigned reserved2 :1;\r
178	unsigned tCL :2; /*< CAS Latency (3,4,5,6) /\r
179	unsigned reserved3 :21;\r
180	} field;\r
181	} RegDTR0; /*< DRAM Timing Register 0 /\r
182	\r
183	typedef union {\r
184	UINT32 raw;\r
185	struct {\r
186	unsigned tWRRD_dly :2; /*< Additional Write to Read Delay (0,1,2,3) /\r
187	unsigned reserved1 :1;\r
188	unsigned tRDWR_dly :2; /*< Additional Read to Write Delay (0,1,2,3) /\r
189	unsigned reserved2 :1;\r
190	unsigned tRDRD_dr_dly :1; /*< Additional Read to Read Delay (1,2) /\r
191	unsigned reserved3 :1;\r
192	unsigned tRD_dly :3; /*< Additional Read Data Sampling Delay (0-7) /\r
193	unsigned reserved4 :1;\r
194	unsigned tRCVEN_halfclk_dly :4; /*< Additional RCVEN Half Clock Delay Control /\r
195	unsigned reserved5 :1;\r
196	unsigned readDqDelay :2; /*< Read DQ Delay /\r
197	unsigned reserved6 :13;\r
198	} field;\r
199	} RegDTR1; /*< DRAM Timing Register 1 /\r
200	\r
201	typedef union {\r
202	UINT32 raw;\r
203	struct {\r
204	unsigned ckStaticDisable :1; /*< CK/CK# Static Disable /\r
205	unsigned reserved1 :3;\r
206	unsigned ckeStaticDisable :2; /*< CKE Static Disable /\r
207	unsigned reserved2 :8;\r
208	unsigned refreshPeriod :2; /*< Refresh Period (disabled,128clks,3.9us,7.8us) /\r
209	unsigned refreshQueueDepth :2; /*< Refresh Queue Depth (1,2,4,8) /\r
210	unsigned reserved5 :13;\r
211	unsigned initComplete :1; /*< Initialization Complete /\r
212	} field;\r
213	} RegDCO;\r
214	\r
215	//\r
216	// MRC Data Structure\r
217	//\r
218	typedef struct {\r
219	RegDRP drp;\r
220	RegDTR0 dtr0;\r
221	RegDTR1 dtr1;\r
222	RegDCO dco;\r
223	UINT32 reg0104;\r
224	UINT32 reg0120;\r
225	UINT32 reg0121;\r
226	UINT32 reg0123;\r
227	UINT32 reg0111;\r
228	UINT32 reg0130;\r
229	UINT8 refreshPeriod; /**< Placeholder for the chosen refresh\r
230	* period. This value will NOT be\r
231	* programmed into DCO until all\r
232	* initialization is done.\r
233	*/\r
234	UINT8 ddr2Odt; /*< 0 = Disabled, 1 = 75 ohm, 2 = 150ohm, 3 = 50ohm /\r
235	UINT8 sku; /*< Detected QuarkNcSocId SKU /\r
236	UINT8 capabilities; /*< Capabilities Available on this part /\r
237	UINT8 state; /*< NORMAL_BOOT, S3_RESUME /\r
238	UINT32 memSize; /*< Memory size /\r
239	UINT16 pmBase; /*< PM Base /\r
240	UINT16 mrcVersion; /*< MRC Version /\r
241	UINT32 hecbase; /*< HECBASE shifted left 16 bits /\r
242	DramGeometry geometry; /*< DRAM Geometry /\r
243	} MRC_DATA_STRUCTURE; /*< QuarkNcSocId Memory Parameters for MRC /\r
244	\r
245	typedef struct _EFI_MEMINIT_CONFIG_DATA {\r
246	MRC_DATA_STRUCTURE MrcData;\r
247	} EFI_MEMINIT_CONFIG_DATA;\r
248	\r
249	\r
250	\r
251	#endif\r