QuarkSocPkg/QuarkNorthCluster/Include/DdrMemoryController.h

   1 /** @file
   2 Memory controller configuration.
   3
   4 Copyright (c) 2013-2015 Intel Corporation.
   5
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9 #ifndef __DDR_MEMORY_CONTROLLER_H__
  10 #define __DDR_MEMORY_CONTROLLER_H__
  11
  12 //
  13 // DDR timing data definitions.
  14 // These are used to create bitmaps of valid timing configurations.
  15 //
  16
  17 #define DUAL_CHANNEL_DDR_TIMING_DATA_FREQUENCY_UNKNOWN    0xFF
  18 #define DUAL_CHANNEL_DDR_TIMING_DATA_REFRESH_RATE_UNKNOWN 0xFF
  19
  20 #define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_20    0x01
  21 #define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_25    0x00
  22 #define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_30    0x02
  23 #define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_ALL   0x03
  24
  25
  26 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_02   0x02
  27 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_03   0x01
  28 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_04   0x00
  29 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_ALL  0x03
  30
  31 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_02    0x02
  32 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_03    0x01
  33 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_04    0x00
  34 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_ALL   0x03
  35
  36 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_05   0x05
  37 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_06   0x04
  38 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_07   0x03
  39 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_08   0x02
  40 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_09   0x01
  41 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_10   0x00
  42 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_ALL  0x07
  43
  44 #define DUAL_CHANNEL_DDR_DATA_TYPE_REGISTERED    0x01
  45 #define DUAL_CHANNEL_DDR_DATA_TYPE_UNREGISTERED  0x02
  46 #define DUAL_CHANNEL_DDR_DATA_TYPE_BUFFERED      0x04
  47 #define DUAL_CHANNEL_DDR_DATA_TYPE_UNBUFFERED    0x08
  48 #define DUAL_CHANNEL_DDR_DATA_TYPE_SDR           0x10
  49 #define DUAL_CHANNEL_DDR_DATA_TYPE_DDR           0x20
  50
  51
  52 //
  53 // Maximum number of SDRAM channels supported by the memory controller
  54 //
  55 #define MAX_CHANNELS 1
  56
  57 //
  58 // Maximum number of DIMM sockets supported by the memory controller
  59 //
  60 #define MAX_SOCKETS 1
  61
  62 //
  63 // Maximum number of sides supported per DIMM
  64 //
  65 #define   MAX_SIDES                         2
  66
  67 //
  68 // Maximum number of "Socket Sets", where a "Socket Set is a set of matching
  69 // DIMM's from the various channels
  70 //
  71 #define   MAX_SOCKET_SETS                   2
  72
  73 //
  74 // Maximum number of rows supported by the memory controller
  75 //
  76 #define MAX_ROWS (MAX_SIDES * MAX_SOCKETS)
  77
  78 //
  79 // Maximum number of memory ranges supported by the memory controller
  80 //
  81 #define MAX_RANGES (MAX_ROWS + 5)
  82
  83 //
  84 // Maximum Number of Log entries
  85 //
  86 #define   MEMORY_LOG_MAX_INDEX          16
  87
  88
  89 typedef struct _MEMORY_LOG_ENTRY {
  90   EFI_STATUS_CODE_VALUE                     Event;
  91   EFI_STATUS_CODE_TYPE                      Severity;
  92   UINT8                                     Data;
  93 } MEMORY_LOG_ENTRY;
  94
  95 typedef struct _MEMORY_LOG {
  96   UINT8                                     Index;
  97   MEMORY_LOG_ENTRY                      Entry[MEMORY_LOG_MAX_INDEX];
  98 } MEMORY_LOG;
  99
 100
 101
 102 //
 103 // Defined ECC types
 104 //
 105 #define DUAL_CHANNEL_DDR_ECC_TYPE_NONE             0x01   // No error checking
 106 #define DUAL_CHANNEL_DDR_ECC_TYPE_EC               0x02   // Error checking only
 107 #define DUAL_CHANNEL_DDR_ECC_TYPE_SECC             0x04   // Software Scrubbing ECC
 108 #define DUAL_CHANNEL_DDR_ECC_TYPE_HECC             0x08   // Hardware Scrubbing ECC
 109 #define DUAL_CHANNEL_DDR_ECC_TYPE_CKECC            0x10   // Chip Kill ECC
 110
 111 //
 112 // Row configuration status values
 113 //
 114 #define DUAL_CHANNEL_DDR_ROW_CONFIG_SUCCESS        0x00  // No error
 115 #define DUAL_CHANNEL_DDR_ROW_CONFIG_UNKNOWN        0x01  // Pattern mismatch, no memory
 116 #define DUAL_CHANNEL_DDR_ROW_CONFIG_UNSUPPORTED    0x02  // Memory type not supported
 117 #define DUAL_CHANNEL_DDR_ROW_CONFIG_ADDRESS_ERROR  0x03  // Row/Col/Bnk mismatch
 118 #define DUAL_CHANNEL_DDR_ROW_CONFIG_ECC_ERROR      0x04  // Received ECC error
 119 #define DUAL_CHANNEL_DDR_ROW_CONFIG_NOT_PRESENT    0x05  // Row is not present
 120 #define DUAL_CHANNEL_DDR_ROW_CONFIG_DISABLED       0x06  // Row is disabled
 121
 122
 123 //
 124 // Memory range types
 125 //
 126 typedef enum {
 127   DualChannelDdrMainMemory,
 128   DualChannelDdrSmramCacheable,
 129   DualChannelDdrSmramNonCacheable,
 130   DualChannelDdrGraphicsMemoryCacheable,
 131   DualChannelDdrGraphicsMemoryNonCacheable,
 132   DualChannelDdrReservedMemory,
 133   DualChannelDdrMaxMemoryRangeType
 134 } DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;
 135
 136 //
 137 // Memory map range information
 138 //
 139 typedef struct {
 140   EFI_PHYSICAL_ADDRESS                          PhysicalAddress;
 141   EFI_PHYSICAL_ADDRESS                          CpuAddress;
 142   EFI_PHYSICAL_ADDRESS                          RangeLength;
 143   DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE                 Type;
 144 } DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;
 145 typedef struct {
 146     unsigned    dramType        :1;                 /**< Type: 0 = RESERVED; 1 = DDR2 */
 147     unsigned    dramWidth       :1;                 /**< Width: 0 = x8; 1 = x16 */
 148     unsigned    dramDensity     :2;                 /**< Density: 00b = 2Gb; 01b = 1Gb; 10b = 512Mb; 11b = 256Mb */
 149     unsigned    dramSpeed       :1;                 /**< Speed Grade: 0 = RESERVED; 1 = 800MT/s;*/
 150     unsigned    dramTimings     :3;                 /**< Timings: 4-4-4, 5-5-5, 6-6-6 */
 151     unsigned    dramRanks       :1;                 /**< Ranks: 0 = Single Rank; 1 = Dual Rank */
 152 } DramGeometry;                                     /**< DRAM Geometry Descriptor */
 153
 154 typedef union _RegDRP {
 155     UINT32    raw;
 156     struct {
 157         unsigned rank0Enabled       :1;     /**< Rank 0 Enable */
 158         unsigned rank0DevWidth      :2;     /**< DRAM Device Width (x8,x16) */
 159         unsigned rank0DevDensity    :2;     /**< DRAM Device Density (256Mb,512Mb,1Gb,2Gb) */
 160         unsigned reserved2          :1;
 161         unsigned rank1Enabled       :1;     /**< Rank 1 Enable */
 162         unsigned reserved3          :5;
 163         unsigned dramType           :1;     /**< DRAM Type (0=DDR2) */
 164         unsigned reserved4          :5;
 165         unsigned reserved5          :14;
 166       } field;
 167 } RegDRP;                                   /**< DRAM Rank Population and Interface Register */
 168
 169
 170 typedef union {
 171     UINT32    raw;
 172     struct {
 173         unsigned dramFrequency      :3;     /**< DRAM Frequency (000=RESERVED,010=667,011=800) */
 174         unsigned tRP                :2;     /**< Precharge to Activate Delay (3,4,5,6) */
 175         unsigned reserved1          :1;
 176         unsigned tRCD               :2;     /**< Activate to CAS Delay (3,4,5,6) */
 177         unsigned reserved2          :1;
 178         unsigned tCL                :2;     /**< CAS Latency (3,4,5,6) */
 179         unsigned reserved3          :21;
 180       } field;
 181 } RegDTR0;                                  /**< DRAM Timing Register 0 */
 182
 183 typedef union {
 184     UINT32    raw;
 185     struct {
 186         unsigned tWRRD_dly          :2;     /**< Additional Write to Read Delay (0,1,2,3) */
 187         unsigned reserved1          :1;
 188         unsigned tRDWR_dly          :2;     /**< Additional Read to Write Delay (0,1,2,3) */
 189         unsigned reserved2          :1;
 190         unsigned tRDRD_dr_dly       :1;     /**< Additional Read to Read Delay (1,2) */
 191         unsigned reserved3          :1;
 192         unsigned tRD_dly            :3;     /**< Additional Read Data Sampling Delay (0-7) */
 193         unsigned reserved4          :1;
 194         unsigned tRCVEN_halfclk_dly :4;     /**< Additional RCVEN Half Clock Delay Control */
 195         unsigned reserved5          :1;
 196         unsigned readDqDelay        :2;     /**< Read DQ Delay */
 197         unsigned reserved6          :13;
 198       } field;
 199 } RegDTR1;                                  /**< DRAM Timing Register 1 */
 200
 201 typedef union {
 202     UINT32    raw;
 203     struct {
 204         unsigned ckStaticDisable    :1;     /**< CK/CK# Static Disable */
 205         unsigned reserved1          :3;
 206         unsigned ckeStaticDisable   :2;     /**< CKE Static Disable */
 207         unsigned reserved2          :8;
 208         unsigned refreshPeriod      :2;     /**< Refresh Period (disabled,128clks,3.9us,7.8us) */
 209         unsigned refreshQueueDepth  :2;     /**< Refresh Queue Depth (1,2,4,8) */
 210         unsigned reserved5          :13;
 211         unsigned initComplete       :1;     /**< Initialization Complete */
 212       } field;
 213 } RegDCO;
 214
 215 //
 216 // MRC Data Structure
 217 //
 218 typedef struct {
 219     RegDRP          drp;
 220     RegDTR0         dtr0;
 221     RegDTR1         dtr1;
 222     RegDCO          dco;
 223     UINT32          reg0104;
 224     UINT32          reg0120;
 225     UINT32          reg0121;
 226     UINT32          reg0123;
 227     UINT32          reg0111;
 228     UINT32          reg0130;
 229     UINT8           refreshPeriod;      /**< Placeholder for the chosen refresh
 230                                          *   period.  This value will NOT be
 231                                          *   programmed into DCO until all
 232                                          *   initialization is done.
 233                                          */
 234     UINT8           ddr2Odt;            /**< 0 = Disabled, 1 = 75 ohm, 2 = 150ohm, 3 = 50ohm */
 235     UINT8           sku;                /**< Detected QuarkNcSocId SKU */
 236     UINT8           capabilities;       /**< Capabilities Available on this part */
 237     UINT8           state;              /**< NORMAL_BOOT, S3_RESUME */
 238     UINT32          memSize;            /**< Memory size */
 239     UINT16          pmBase;             /**< PM Base */
 240     UINT16          mrcVersion;         /**< MRC Version */
 241     UINT32          hecbase;            /**< HECBASE shifted left 16 bits */
 242     DramGeometry    geometry;          /**< DRAM Geometry */
 243 } MRC_DATA_STRUCTURE;             /**< QuarkNcSocId Memory Parameters for MRC */
 244
 245 typedef struct _EFI_MEMINIT_CONFIG_DATA {
 246   MRC_DATA_STRUCTURE                        MrcData;
 247 } EFI_MEMINIT_CONFIG_DATA;
 248
 249
 250
 251 #endif