[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / Library / SmmCpuFeaturesLib / SmmCpuFeaturesLib.c

/** @file\r
The Quark CPU specific programming for PiSmmCpuDxeSmm module.\r
\r
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <PiSmm.h>\r
#include <Library/SmmCpuFeaturesLib.h>\r
#include <Register/SmramSaveStateMap.h>\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/QNCAccessLib.h>\r
\r
#define  EFI_MSR_SMRR_PHYS_MASK_VALID          BIT11\r
#define  EFI_MSR_SMRR_MASK                     0xFFFFF000\r
\r
/**\r
  Called during the very first SMI into System Management Mode to initialize\r
  CPU features, including SMBASE, for the currently executing CPU.  Since this\r
  is the first SMI, the SMRAM Save State Map is at the default address of\r
  SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET.  The currently executing\r
  CPU is specified by CpuIndex and CpuIndex can be used to access information\r
  about the currently executing CPU in the ProcessorInfo array and the\r
  HotPlugCpuData data structure.\r
\r
  @param[in] CpuIndex        The index of the CPU to initialize.  The value\r
                             must be between 0 and the NumberOfCpus field in\r
                             the System Management System Table (SMST).\r
  @param[in] IsMonarch       TRUE if the CpuIndex is the index of the CPU that\r
                             was elected as monarch during System Management\r
                             Mode initialization.\r
                             FALSE if the CpuIndex is not the index of the CPU\r
                             that was elected as monarch during System\r
                             Management Mode initialization.\r
  @param[in] ProcessorInfo   Pointer to an array of EFI_PROCESSOR_INFORMATION\r
                             structures.  ProcessorInfo[CpuIndex] contains the\r
                             information for the currently executing CPU.\r
  @param[in] CpuHotPlugData  Pointer to the CPU_HOT_PLUG_DATA structure that\r
                             contains the ApidId and SmBase arrays.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesInitializeProcessor (\r
  IN UINTN                      CpuIndex,\r
  IN BOOLEAN                    IsMonarch,\r
  IN EFI_PROCESSOR_INFORMATION  *ProcessorInfo,\r
  IN CPU_HOT_PLUG_DATA          *CpuHotPlugData\r
  )\r
{\r
  SMRAM_SAVE_STATE_MAP  *CpuState;\r
\r
  //\r
  // Configure SMBASE.\r
  //\r
  CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
  CpuState->x86.SMBASE = CpuHotPlugData->SmBase[CpuIndex];\r
\r
  //\r
  // SMRR size cannot be less than 4-KBytes\r
  // SMRR size must be of length 2^n\r
  // SMRR base alignment cannot be less than SMRR length\r
  //\r
  if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||\r
      (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||\r
      ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase)) {\r
    DEBUG ((EFI_D_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));\r
    CpuDeadLoop ();\r
  }\r
\r
  //\r
  // Use QNC to initialize SMRR on Quark\r
  //\r
  QNCPortWrite(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE, CpuHotPlugData->SmrrBase);\r
  QNCPortWrite(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK) | EFI_MSR_SMRR_PHYS_MASK_VALID);\r
}\r
\r
/**\r
  This function updates the SMRAM save state on the currently executing CPU\r
  to resume execution at a specific address after an RSM instruction.  This\r
  function must evaluate the SMRAM save state to determine the execution mode\r
  the RSM instruction resumes and update the resume execution address with\r
  either NewInstructionPointer32 or NewInstructionPoint.  The auto HALT restart\r
  flag in the SMRAM save state must always be cleared.  This function returns\r
  the value of the instruction pointer from the SMRAM save state that was\r
  replaced.  If this function returns 0, then the SMRAM save state was not\r
  modified.\r
\r
  This function is called during the very first SMI on each CPU after\r
  SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode\r
  to signal that the SMBASE of each CPU has been updated before the default\r
  SMBASE address is used for the first SMI to the next CPU.\r
\r
  @param[in] CpuIndex                 The index of the CPU to hook.  The value\r
                                      must be between 0 and the NumberOfCpus\r
                                      field in the System Management System Table\r
                                      (SMST).\r
  @param[in] CpuState                 Pointer to SMRAM Save State Map for the\r
                                      currently executing CPU.\r
  @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to\r
                                      32-bit execution mode from 64-bit SMM.\r
  @param[in] NewInstructionPointer    Instruction pointer to use if resuming to\r
                                      same execution mode as SMM.\r
\r
  @retval 0    This function did modify the SMRAM save state.\r
  @retval > 0  The original instruction pointer value from the SMRAM save state\r
               before it was replaced.\r
**/\r
UINT64\r
EFIAPI\r
SmmCpuFeaturesHookReturnFromSmm (\r
  IN UINTN                 CpuIndex,\r
  IN SMRAM_SAVE_STATE_MAP  *CpuState,\r
  IN UINT64                NewInstructionPointer32,\r
  IN UINT64                NewInstructionPointer\r
  )\r
{\r
  return 0;\r
}\r
\r
/**\r
  Hook point in normal execution mode that allows the one CPU that was elected\r
  as monarch during System Management Mode initialization to perform additional\r
  initialization actions immediately after all of the CPUs have processed their\r
  first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE\r
  into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesSmmRelocationComplete (\r
  VOID\r
  )\r
{\r
}\r
\r
/**\r
  Return the size, in bytes, of a custom SMI Handler in bytes.  If 0 is\r
  returned, then a custom SMI handler is not provided by this library,\r
  and the default SMI handler must be used.\r
\r
  @retval 0    Use the default SMI handler.\r
  @retval > 0  Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()\r
               The caller is required to allocate enough SMRAM for each CPU to\r
               support the size of the custom SMI handler.\r
**/\r
UINTN\r
EFIAPI\r
SmmCpuFeaturesGetSmiHandlerSize (\r
  VOID\r
  )\r
{\r
  return 0;\r
}\r
\r
/**\r
  Install a custom SMI handler for the CPU specified by CpuIndex.  This function\r
  is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater\r
  than zero and is called by the CPU that was elected as monarch during System\r
  Management Mode initialization.\r
\r
  @param[in] CpuIndex   The index of the CPU to install the custom SMI handler.\r
                        The value must be between 0 and the NumberOfCpus field\r
                        in the System Management System Table (SMST).\r
  @param[in] SmBase     The SMBASE address for the CPU specified by CpuIndex.\r
  @param[in] SmiStack   The stack to use when an SMI is processed by the\r
                        the CPU specified by CpuIndex.\r
  @param[in] StackSize  The size, in bytes, if the stack used when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] GdtBase    The base address of the GDT to use when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] GdtSize    The size, in bytes, of the GDT used when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] IdtBase    The base address of the IDT to use when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] IdtSize    The size, in bytes, of the IDT used when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] Cr3        The base address of the page tables to use when an SMI\r
                        is processed by the CPU specified by CpuIndex.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesInstallSmiHandler (\r
  IN UINTN   CpuIndex,\r
  IN UINT32  SmBase,\r
  IN VOID    *SmiStack,\r
  IN UINTN   StackSize,\r
  IN UINTN   GdtBase,\r
  IN UINTN   GdtSize,\r
  IN UINTN   IdtBase,\r
  IN UINTN   IdtSize,\r
  IN UINT32  Cr3\r
  )\r
{\r
}\r
\r
/**\r
  Determines if MTRR registers must be configured to set SMRAM cache-ability\r
  when executing in System Management Mode.\r
\r
  @retval TRUE   MTRR registers must be configured to set SMRAM cache-ability.\r
  @retval FALSE  MTRR registers do not need to be configured to set SMRAM\r
                   cache-ability.\r
**/\r
BOOLEAN\r
EFIAPI\r
SmmCpuFeaturesNeedConfigureMtrrs (\r
  VOID\r
  )\r
{\r
  return TRUE;\r
}\r
\r
/**\r
  Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
  returns TRUE.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesDisableSmrr (\r
  VOID\r
  )\r
{\r
  //\r
  // Use QNC to disable SMRR on Quark\r
  //\r
  QNCPortWrite(\r
    QUARK_NC_HOST_BRIDGE_SB_PORT_ID,\r
    QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK,\r
    QNCPortRead(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK) & ~EFI_MSR_SMRR_PHYS_MASK_VALID\r
    );\r
}\r
\r
/**\r
  Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
  returns TRUE.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesReenableSmrr (\r
  VOID\r
  )\r
{\r
  //\r
  // Use QNC to enable SMRR on Quark\r
  //\r
  QNCPortWrite(\r
    QUARK_NC_HOST_BRIDGE_SB_PORT_ID,\r
    QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK,\r
    QNCPortRead(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK) | EFI_MSR_SMRR_PHYS_MASK_VALID\r
    );\r
}\r
\r
/**\r
  Processor specific hook point each time a CPU enters System Management Mode.\r
\r
  @param[in] CpuIndex  The index of the CPU that has entered SMM.  The value\r
                       must be between 0 and the NumberOfCpus field in the\r
                       System Management System Table (SMST).\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesRendezvousEntry (\r
  IN UINTN  CpuIndex\r
  )\r
{\r
}\r
\r
/**\r
  Processor specific hook point each time a CPU exits System Management Mode.\r
\r
  @param[in] CpuIndex  The index of the CPU that is exiting SMM.  The value must\r
                       be between 0 and the NumberOfCpus field in the System\r
                       Management System Table (SMST).\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesRendezvousExit (\r
  IN UINTN  CpuIndex\r
  )\r
{\r
}\r
\r
/**\r
  Check to see if an SMM register is supported by a specified CPU.\r
\r
  @param[in] CpuIndex  The index of the CPU to check for SMM register support.\r
                       The value must be between 0 and the NumberOfCpus field\r
                       in the System Management System Table (SMST).\r
  @param[in] RegName   Identifies the SMM register to check for support.\r
\r
  @retval TRUE   The SMM register specified by RegName is supported by the CPU\r
                 specified by CpuIndex.\r
  @retval FALSE  The SMM register specified by RegName is not supported by the\r
                 CPU specified by CpuIndex.\r
**/\r
BOOLEAN\r
EFIAPI\r
SmmCpuFeaturesIsSmmRegisterSupported (\r
  IN UINTN         CpuIndex,\r
  IN SMM_REG_NAME  RegName\r
  )\r
{\r
  return FALSE;\r
}\r
\r
/**\r
  Returns the current value of the SMM register for the specified CPU.\r
  If the SMM register is not supported, then 0 is returned.\r
\r
  @param[in] CpuIndex  The index of the CPU to read the SMM register.  The\r
                       value must be between 0 and the NumberOfCpus field in\r
                       the System Management System Table (SMST).\r
  @param[in] RegName   Identifies the SMM register to read.\r
\r
  @return  The value of the SMM register specified by RegName from the CPU\r
           specified by CpuIndex.\r
**/\r
UINT64\r
EFIAPI\r
SmmCpuFeaturesGetSmmRegister (\r
  IN UINTN         CpuIndex,\r
  IN SMM_REG_NAME  RegName\r
  )\r
{\r
  return 0;\r
}\r
\r
/**\r
  Sets the value of an SMM register on a specified CPU.\r
  If the SMM register is not supported, then no action is performed.\r
\r
  @param[in] CpuIndex  The index of the CPU to write the SMM register.  The\r
                       value must be between 0 and the NumberOfCpus field in\r
                       the System Management System Table (SMST).\r
  @param[in] RegName   Identifies the SMM register to write.\r
                       registers are read-only.\r
  @param[in] Value     The value to write to the SMM register.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesSetSmmRegister (\r
  IN UINTN         CpuIndex,\r
  IN SMM_REG_NAME  RegName,\r
  IN UINT64        Value\r
  )\r
{\r
}\r
\r
/**\r
  Read an SMM Save State register on the target processor.  If this function\r
  returns EFI_UNSUPPORTED, then the caller is responsible for reading the\r
  SMM Save Sate register.\r
\r
  @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The\r
                        value must be between 0 and the NumberOfCpus field in\r
                        the System Management System Table (SMST).\r
  @param[in]  Register  The SMM Save State register to read.\r
  @param[in]  Width     The number of bytes to read from the CPU save state.\r
  @param[out] Buffer    Upon return, this holds the CPU register value read\r
                        from the save state.\r
\r
  @retval EFI_SUCCESS           The register was read from Save State.\r
  @retval EFI_INVALID_PARAMTER  Buffer is NULL.\r
  @retval EFI_UNSUPPORTED       This function does not support reading Register.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmCpuFeaturesReadSaveStateRegister (\r
  IN  UINTN                        CpuIndex,\r
  IN  EFI_SMM_SAVE_STATE_REGISTER  Register,\r
  IN  UINTN                        Width,\r
  OUT VOID                         *Buffer\r
  )\r
{\r
  return EFI_UNSUPPORTED;\r
}\r
\r
/**\r
  Writes an SMM Save State register on the target processor.  If this function\r
  returns EFI_UNSUPPORTED, then the caller is responsible for writing the\r
  SMM Save Sate register.\r
\r
  @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The\r
                       value must be between 0 and the NumberOfCpus field in\r
                       the System Management System Table (SMST).\r
  @param[in] Register  The SMM Save State register to write.\r
  @param[in] Width     The number of bytes to write to the CPU save state.\r
  @param[in] Buffer    Upon entry, this holds the new CPU register value.\r
\r
  @retval EFI_SUCCESS           The register was written to Save State.\r
  @retval EFI_INVALID_PARAMTER  Buffer is NULL.\r
  @retval EFI_UNSUPPORTED       This function does not support writing Register.\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmCpuFeaturesWriteSaveStateRegister (\r
  IN UINTN                        CpuIndex,\r
  IN EFI_SMM_SAVE_STATE_REGISTER  Register,\r
  IN UINTN                        Width,\r
  IN CONST VOID                   *Buffer\r
  )\r
{\r
  return EFI_UNSUPPORTED;\r
}\r
\r
/**\r
  This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r
  notification is completely processed.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesCompleteSmmReadyToLock (\r
  VOID\r
  )\r
{\r
}\r
\r
/**\r
  This API provides a method for a CPU to allocate a specific region for storing page tables.\r
\r
  This API can be called more once to allocate memory for page tables.\r
\r
  Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
  allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL\r
  is returned.  If there is not enough memory remaining to satisfy the request, then NULL is\r
  returned.\r
\r
  This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.\r
\r
  @param  Pages                 The number of 4 KB pages to allocate.\r
\r
  @return A pointer to the allocated buffer for page tables.\r
  @retval NULL      Fail to allocate a specific region for storing page tables,\r
                    Or there is no preference on where the page tables are allocated in SMRAM.\r
\r
**/\r
VOID *\r
EFIAPI\r
SmmCpuFeaturesAllocatePageTableMemory (\r
  IN UINTN           Pages\r
  )\r
{\r
  return NULL;\r
}\r
Commit	Line	Data
9b6bbcdb MK	1	/** @file\r
	2	The Quark CPU specific programming for PiSmmCpuDxeSmm module.\r
	3	\r
4be1fbc2	4	Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
c9f231d0	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
9b6bbcdb MK	6	\r
	7	**/\r
	8	\r
	9	#include <PiSmm.h>\r
	10	#include <Library/SmmCpuFeaturesLib.h>\r
	11	#include <Register/SmramSaveStateMap.h>\r
4be1fbc2 MK	12	#include <Library/BaseLib.h>\r
4be1fbc2 MK	13	#include <Library/DebugLib.h>\r
9b6bbcdb MK	14	#include <Library/QNCAccessLib.h>\r
	15	\r
	16	#define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11\r
	17	#define EFI_MSR_SMRR_MASK 0xFFFFF000\r
	18	\r
	19	/**\r
	20	Called during the very first SMI into System Management Mode to initialize\r
	21	CPU features, including SMBASE, for the currently executing CPU. Since this\r
	22	is the first SMI, the SMRAM Save State Map is at the default address of\r
	23	SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing\r
	24	CPU is specified by CpuIndex and CpuIndex can be used to access information\r
	25	about the currently executing CPU in the ProcessorInfo array and the\r
	26	HotPlugCpuData data structure.\r
	27	\r
	28	@param[in] CpuIndex The index of the CPU to initialize. The value\r
	29	must be between 0 and the NumberOfCpus field in\r
	30	the System Management System Table (SMST).\r
	31	@param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that\r
	32	was elected as monarch during System Management\r
	33	Mode initialization.\r
	34	FALSE if the CpuIndex is not the index of the CPU\r
	35	that was elected as monarch during System\r
	36	Management Mode initialization.\r
	37	@param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION\r
	38	structures. ProcessorInfo[CpuIndex] contains the\r
	39	information for the currently executing CPU.\r
	40	@param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that\r
	41	contains the ApidId and SmBase arrays.\r
	42	**/\r
	43	VOID\r
	44	EFIAPI\r
	45	SmmCpuFeaturesInitializeProcessor (\r
	46	IN UINTN CpuIndex,\r
	47	IN BOOLEAN IsMonarch,\r
	48	IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,\r
	49	IN CPU_HOT_PLUG_DATA *CpuHotPlugData\r
	50	)\r
	51	{\r
	52	SMRAM_SAVE_STATE_MAP *CpuState;\r
	53	\r
	54	//\r
	55	// Configure SMBASE.\r
	56	//\r
	57	CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
	58	CpuState->x86.SMBASE = CpuHotPlugData->SmBase[CpuIndex];\r
	59	\r
4be1fbc2 MK	60	//\r
	61	// SMRR size cannot be less than 4-KBytes\r
	62	// SMRR size must be of length 2^n\r
	63	// SMRR base alignment cannot be less than SMRR length\r
	64	//\r
	65	if ((CpuHotPlugData->SmrrSize < SIZE_4KB) \|\|\r
	66	(CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) \|\|\r
	67	((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase)) {\r
	68	DEBUG ((EFI_D_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));\r
	69	CpuDeadLoop ();\r
	70	}\r
	71	\r
9b6bbcdb MK	72	//\r
	73	// Use QNC to initialize SMRR on Quark\r
	74	//\r
	75	QNCPortWrite(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE, CpuHotPlugData->SmrrBase);\r
	76	QNCPortWrite(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK) \| EFI_MSR_SMRR_PHYS_MASK_VALID);\r
	77	}\r
	78	\r
	79	/**\r
	80	This function updates the SMRAM save state on the currently executing CPU\r
	81	to resume execution at a specific address after an RSM instruction. This\r
	82	function must evaluate the SMRAM save state to determine the execution mode\r
	83	the RSM instruction resumes and update the resume execution address with\r
	84	either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart\r
	85	flag in the SMRAM save state must always be cleared. This function returns\r
	86	the value of the instruction pointer from the SMRAM save state that was\r
	87	replaced. If this function returns 0, then the SMRAM save state was not\r
	88	modified.\r
	89	\r
	90	This function is called during the very first SMI on each CPU after\r
	91	SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode\r
	92	to signal that the SMBASE of each CPU has been updated before the default\r
	93	SMBASE address is used for the first SMI to the next CPU.\r
	94	\r
	95	@param[in] CpuIndex The index of the CPU to hook. The value\r
	96	must be between 0 and the NumberOfCpus\r
	97	field in the System Management System Table\r
	98	(SMST).\r
	99	@param[in] CpuState Pointer to SMRAM Save State Map for the\r
	100	currently executing CPU.\r
	101	@param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
	102	32-bit execution mode from 64-bit SMM.\r
	103	@param[in] NewInstructionPointer Instruction pointer to use if resuming to\r
	104	same execution mode as SMM.\r
	105	\r
	106	@retval 0 This function did modify the SMRAM save state.\r
	107	@retval > 0 The original instruction pointer value from the SMRAM save state\r
	108	before it was replaced.\r
	109	**/\r
	110	UINT64\r
	111	EFIAPI\r
	112	SmmCpuFeaturesHookReturnFromSmm (\r
	113	IN UINTN CpuIndex,\r
	114	IN SMRAM_SAVE_STATE_MAP *CpuState,\r
	115	IN UINT64 NewInstructionPointer32,\r
	116	IN UINT64 NewInstructionPointer\r
	117	)\r
	118	{\r
	119	return 0;\r
	120	}\r
	121	\r
	122	/**\r
	123	Hook point in normal execution mode that allows the one CPU that was elected\r
	124	as monarch during System Management Mode initialization to perform additional\r
	125	initialization actions immediately after all of the CPUs have processed their\r
	126	first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE\r
	127	into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().\r
	128	**/\r
	129	VOID\r
	130	EFIAPI\r
	131	SmmCpuFeaturesSmmRelocationComplete (\r
	132	VOID\r
	133	)\r
	134	{\r
	135	}\r
136	\r
137	/**\r
138	Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is\r
139	returned, then a custom SMI handler is not provided by this library,\r
140	and the default SMI handler must be used.\r
141	\r
142	@retval 0 Use the default SMI handler.\r
143	@retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()\r
144	The caller is required to allocate enough SMRAM for each CPU to\r
145	support the size of the custom SMI handler.\r
146	**/\r
147	UINTN\r
148	EFIAPI\r
149	SmmCpuFeaturesGetSmiHandlerSize (\r
150	VOID\r
151	)\r
152	{\r
153	return 0;\r
154	}\r
155	\r
156	/**\r
157	Install a custom SMI handler for the CPU specified by CpuIndex. This function\r
158	is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater\r
159	than zero and is called by the CPU that was elected as monarch during System\r
160	Management Mode initialization.\r
161	\r
162	@param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r
163	The value must be between 0 and the NumberOfCpus field\r
164	in the System Management System Table (SMST).\r
165	@param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r
166	@param[in] SmiStack The stack to use when an SMI is processed by the\r
167	the CPU specified by CpuIndex.\r
168	@param[in] StackSize The size, in bytes, if the stack used when an SMI is\r
169	processed by the CPU specified by CpuIndex.\r
170	@param[in] GdtBase The base address of the GDT to use when an SMI is\r
171	processed by the CPU specified by CpuIndex.\r
172	@param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r
173	processed by the CPU specified by CpuIndex.\r
174	@param[in] IdtBase The base address of the IDT to use when an SMI is\r
175	processed by the CPU specified by CpuIndex.\r
176	@param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r
177	processed by the CPU specified by CpuIndex.\r
178	@param[in] Cr3 The base address of the page tables to use when an SMI\r
179	is processed by the CPU specified by CpuIndex.\r
180	**/\r
181	VOID\r
182	EFIAPI\r
183	SmmCpuFeaturesInstallSmiHandler (\r
184	IN UINTN CpuIndex,\r
185	IN UINT32 SmBase,\r
186	IN VOID *SmiStack,\r
187	IN UINTN StackSize,\r
188	IN UINTN GdtBase,\r
189	IN UINTN GdtSize,\r
190	IN UINTN IdtBase,\r
191	IN UINTN IdtSize,\r
192	IN UINT32 Cr3\r
193	)\r
194	{\r
195	}\r
196	\r
197	/**\r
198	Determines if MTRR registers must be configured to set SMRAM cache-ability\r
199	when executing in System Management Mode.\r
200	\r
201	@retval TRUE MTRR registers must be configured to set SMRAM cache-ability.\r
202	@retval FALSE MTRR registers do not need to be configured to set SMRAM\r
203	cache-ability.\r
204	**/\r
205	BOOLEAN\r
206	EFIAPI\r
207	SmmCpuFeaturesNeedConfigureMtrrs (\r
208	VOID\r
209	)\r
210	{\r
211	return TRUE;\r
212	}\r
213	\r
214	/**\r
215	Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
216	returns TRUE.\r
217	**/\r
218	VOID\r
219	EFIAPI\r
220	SmmCpuFeaturesDisableSmrr (\r
221	VOID\r
222	)\r
223	{\r
224	//\r
225	// Use QNC to disable SMRR on Quark\r
226	//\r
227	QNCPortWrite(\r
228	QUARK_NC_HOST_BRIDGE_SB_PORT_ID,\r
229	QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK,\r
230	QNCPortRead(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK) & ~EFI_MSR_SMRR_PHYS_MASK_VALID\r
231	);\r
232	}\r
233	\r
234	/**\r
235	Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
236	returns TRUE.\r
237	**/\r
238	VOID\r
239	EFIAPI\r
240	SmmCpuFeaturesReenableSmrr (\r
241	VOID\r
242	)\r
243	{\r
244	//\r
245	// Use QNC to enable SMRR on Quark\r
246	//\r
247	QNCPortWrite(\r
248	QUARK_NC_HOST_BRIDGE_SB_PORT_ID,\r
249	QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK,\r
250	QNCPortRead(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK) \| EFI_MSR_SMRR_PHYS_MASK_VALID\r
251	);\r
252	}\r
253	\r
254	/**\r
255	Processor specific hook point each time a CPU enters System Management Mode.\r
256	\r
257	@param[in] CpuIndex The index of the CPU that has entered SMM. The value\r
258	must be between 0 and the NumberOfCpus field in the\r
259	System Management System Table (SMST).\r
260	**/\r
261	VOID\r
262	EFIAPI\r
263	SmmCpuFeaturesRendezvousEntry (\r
264	IN UINTN CpuIndex\r
265	)\r
266	{\r
267	}\r
268	\r
269	/**\r
270	Processor specific hook point each time a CPU exits System Management Mode.\r
271	\r
272	@param[in] CpuIndex The index of the CPU that is exiting SMM. The value must\r
273	be between 0 and the NumberOfCpus field in the System\r
274	Management System Table (SMST).\r
275	**/\r
276	VOID\r
277	EFIAPI\r
278	SmmCpuFeaturesRendezvousExit (\r
279	IN UINTN CpuIndex\r
280	)\r
281	{\r
282	}\r
283	\r
284	/**\r
285	Check to see if an SMM register is supported by a specified CPU.\r
286	\r
287	@param[in] CpuIndex The index of the CPU to check for SMM register support.\r
288	The value must be between 0 and the NumberOfCpus field\r
289	in the System Management System Table (SMST).\r
290	@param[in] RegName Identifies the SMM register to check for support.\r
291	\r
292	@retval TRUE The SMM register specified by RegName is supported by the CPU\r
293	specified by CpuIndex.\r
294	@retval FALSE The SMM register specified by RegName is not supported by the\r
295	CPU specified by CpuIndex.\r
296	**/\r
297	BOOLEAN\r
298	EFIAPI\r
299	SmmCpuFeaturesIsSmmRegisterSupported (\r
300	IN UINTN CpuIndex,\r
301	IN SMM_REG_NAME RegName\r
302	)\r
303	{\r
304	return FALSE;\r
305	}\r
306	\r
307	/**\r
308	Returns the current value of the SMM register for the specified CPU.\r
309	If the SMM register is not supported, then 0 is returned.\r
310	\r
311	@param[in] CpuIndex The index of the CPU to read the SMM register. The\r
312	value must be between 0 and the NumberOfCpus field in\r
313	the System Management System Table (SMST).\r
314	@param[in] RegName Identifies the SMM register to read.\r
315	\r
316	@return The value of the SMM register specified by RegName from the CPU\r
317	specified by CpuIndex.\r
318	**/\r
319	UINT64\r
320	EFIAPI\r
321	SmmCpuFeaturesGetSmmRegister (\r
322	IN UINTN CpuIndex,\r
323	IN SMM_REG_NAME RegName\r
324	)\r
325	{\r
326	return 0;\r
327	}\r
328	\r
329	/**\r
330	Sets the value of an SMM register on a specified CPU.\r
331	If the SMM register is not supported, then no action is performed.\r
332	\r
333	@param[in] CpuIndex The index of the CPU to write the SMM register. The\r
334	value must be between 0 and the NumberOfCpus field in\r
335	the System Management System Table (SMST).\r
336	@param[in] RegName Identifies the SMM register to write.\r
337	registers are read-only.\r
338	@param[in] Value The value to write to the SMM register.\r
339	**/\r
340	VOID\r
341	EFIAPI\r
342	SmmCpuFeaturesSetSmmRegister (\r
343	IN UINTN CpuIndex,\r
344	IN SMM_REG_NAME RegName,\r
345	IN UINT64 Value\r
346	)\r
347	{\r
348	}\r
349	\r
350	/**\r
351	Read an SMM Save State register on the target processor. If this function\r
352	returns EFI_UNSUPPORTED, then the caller is responsible for reading the\r
353	SMM Save Sate register.\r
354	\r
355	@param[in] CpuIndex The index of the CPU to read the SMM Save State. The\r
356	value must be between 0 and the NumberOfCpus field in\r
357	the System Management System Table (SMST).\r
358	@param[in] Register The SMM Save State register to read.\r
359	@param[in] Width The number of bytes to read from the CPU save state.\r
360	@param[out] Buffer Upon return, this holds the CPU register value read\r
361	from the save state.\r
362	\r
363	@retval EFI_SUCCESS The register was read from Save State.\r
364	@retval EFI_INVALID_PARAMTER Buffer is NULL.\r
365	@retval EFI_UNSUPPORTED This function does not support reading Register.\r
366	\r
367	**/\r
368	EFI_STATUS\r
369	EFIAPI\r
370	SmmCpuFeaturesReadSaveStateRegister (\r
371	IN UINTN CpuIndex,\r
372	IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
373	IN UINTN Width,\r
374	OUT VOID *Buffer\r
375	)\r
376	{\r
377	return EFI_UNSUPPORTED;\r
378	}\r
379	\r
380	/**\r
381	Writes an SMM Save State register on the target processor. If this function\r
382	returns EFI_UNSUPPORTED, then the caller is responsible for writing the\r
383	SMM Save Sate register.\r
384	\r
385	@param[in] CpuIndex The index of the CPU to write the SMM Save State. The\r
386	value must be between 0 and the NumberOfCpus field in\r
387	the System Management System Table (SMST).\r
388	@param[in] Register The SMM Save State register to write.\r
389	@param[in] Width The number of bytes to write to the CPU save state.\r
390	@param[in] Buffer Upon entry, this holds the new CPU register value.\r
391	\r
392	@retval EFI_SUCCESS The register was written to Save State.\r
393	@retval EFI_INVALID_PARAMTER Buffer is NULL.\r
394	@retval EFI_UNSUPPORTED This function does not support writing Register.\r
395	**/\r
396	EFI_STATUS\r
397	EFIAPI\r
398	SmmCpuFeaturesWriteSaveStateRegister (\r
399	IN UINTN CpuIndex,\r
400	IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
401	IN UINTN Width,\r
402	IN CONST VOID *Buffer\r
403	)\r
404	{\r
405	return EFI_UNSUPPORTED;\r
406	}\r
407	\r
408	/**\r
409	This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r
410	notification is completely processed.\r
411	**/\r
412	VOID\r
413	EFIAPI\r
414	SmmCpuFeaturesCompleteSmmReadyToLock (\r
415	VOID\r
416	)\r
417	{\r
418	}\r
419	\r
420	/**\r
421	This API provides a method for a CPU to allocate a specific region for storing page tables.\r
422	\r
423	This API can be called more once to allocate memory for page tables.\r
424	\r
425	Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
426	allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r
427	is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r
428	returned.\r
429	\r
430	This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.\r
431	\r
432	@param Pages The number of 4 KB pages to allocate.\r
433	\r
434	@return A pointer to the allocated buffer for page tables.\r
435	@retval NULL Fail to allocate a specific region for storing page tables,\r
436	Or there is no preference on where the page tables are allocated in SMRAM.\r
437	\r
438	**/\r
439	VOID *\r
440	EFIAPI\r
441	SmmCpuFeaturesAllocatePageTableMemory (\r
442	IN UINTN Pages\r
443	)\r
444	{\r
445	return NULL;\r
446	}\r