QuarkSocPkg/SmmCpuFeaturesLib: Add SMRR PhysBase/PhysMask fields check
[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / Library / SmmCpuFeaturesLib / SmmCpuFeaturesLib.c
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1/** @file\r
2The Quark CPU specific programming for PiSmmCpuDxeSmm module.\r
3\r
4be1fbc2 4Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
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5This program and the accompanying materials\r
6are licensed and made available under the terms and conditions of the BSD License\r
7which accompanies this distribution. The full text of the license may be found at\r
8http://opensource.org/licenses/bsd-license.php\r
9\r
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include <PiSmm.h>\r
16#include <Library/SmmCpuFeaturesLib.h>\r
17#include <Register/SmramSaveStateMap.h>\r
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18#include <Library/BaseLib.h>\r
19#include <Library/DebugLib.h>\r
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20#include <Library/QNCAccessLib.h>\r
21\r
22#define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11\r
23#define EFI_MSR_SMRR_MASK 0xFFFFF000\r
24\r
25/**\r
26 Called during the very first SMI into System Management Mode to initialize\r
27 CPU features, including SMBASE, for the currently executing CPU. Since this\r
28 is the first SMI, the SMRAM Save State Map is at the default address of\r
29 SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing\r
30 CPU is specified by CpuIndex and CpuIndex can be used to access information\r
31 about the currently executing CPU in the ProcessorInfo array and the\r
32 HotPlugCpuData data structure.\r
33\r
34 @param[in] CpuIndex The index of the CPU to initialize. The value\r
35 must be between 0 and the NumberOfCpus field in\r
36 the System Management System Table (SMST).\r
37 @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that\r
38 was elected as monarch during System Management\r
39 Mode initialization.\r
40 FALSE if the CpuIndex is not the index of the CPU\r
41 that was elected as monarch during System\r
42 Management Mode initialization.\r
43 @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION\r
44 structures. ProcessorInfo[CpuIndex] contains the\r
45 information for the currently executing CPU.\r
46 @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that\r
47 contains the ApidId and SmBase arrays.\r
48**/\r
49VOID\r
50EFIAPI\r
51SmmCpuFeaturesInitializeProcessor (\r
52 IN UINTN CpuIndex,\r
53 IN BOOLEAN IsMonarch,\r
54 IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,\r
55 IN CPU_HOT_PLUG_DATA *CpuHotPlugData\r
56 )\r
57{\r
58 SMRAM_SAVE_STATE_MAP *CpuState;\r
59\r
60 //\r
61 // Configure SMBASE.\r
62 //\r
63 CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
64 CpuState->x86.SMBASE = CpuHotPlugData->SmBase[CpuIndex];\r
65\r
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66 //\r
67 // SMRR size cannot be less than 4-KBytes\r
68 // SMRR size must be of length 2^n\r
69 // SMRR base alignment cannot be less than SMRR length\r
70 //\r
71 if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||\r
72 (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||\r
73 ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase)) {\r
74 DEBUG ((EFI_D_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));\r
75 CpuDeadLoop ();\r
76 }\r
77\r
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78 //\r
79 // Use QNC to initialize SMRR on Quark\r
80 //\r
81 QNCPortWrite(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE, CpuHotPlugData->SmrrBase);\r
82 QNCPortWrite(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK) | EFI_MSR_SMRR_PHYS_MASK_VALID);\r
83}\r
84\r
85/**\r
86 This function updates the SMRAM save state on the currently executing CPU\r
87 to resume execution at a specific address after an RSM instruction. This\r
88 function must evaluate the SMRAM save state to determine the execution mode\r
89 the RSM instruction resumes and update the resume execution address with\r
90 either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart\r
91 flag in the SMRAM save state must always be cleared. This function returns\r
92 the value of the instruction pointer from the SMRAM save state that was\r
93 replaced. If this function returns 0, then the SMRAM save state was not\r
94 modified.\r
95\r
96 This function is called during the very first SMI on each CPU after\r
97 SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode\r
98 to signal that the SMBASE of each CPU has been updated before the default\r
99 SMBASE address is used for the first SMI to the next CPU.\r
100\r
101 @param[in] CpuIndex The index of the CPU to hook. The value\r
102 must be between 0 and the NumberOfCpus\r
103 field in the System Management System Table\r
104 (SMST).\r
105 @param[in] CpuState Pointer to SMRAM Save State Map for the\r
106 currently executing CPU.\r
107 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
108 32-bit execution mode from 64-bit SMM.\r
109 @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r
110 same execution mode as SMM.\r
111\r
112 @retval 0 This function did modify the SMRAM save state.\r
113 @retval > 0 The original instruction pointer value from the SMRAM save state\r
114 before it was replaced.\r
115**/\r
116UINT64\r
117EFIAPI\r
118SmmCpuFeaturesHookReturnFromSmm (\r
119 IN UINTN CpuIndex,\r
120 IN SMRAM_SAVE_STATE_MAP *CpuState,\r
121 IN UINT64 NewInstructionPointer32,\r
122 IN UINT64 NewInstructionPointer\r
123 )\r
124{\r
125 return 0;\r
126}\r
127\r
128/**\r
129 Hook point in normal execution mode that allows the one CPU that was elected\r
130 as monarch during System Management Mode initialization to perform additional\r
131 initialization actions immediately after all of the CPUs have processed their\r
132 first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE\r
133 into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().\r
134**/\r
135VOID\r
136EFIAPI\r
137SmmCpuFeaturesSmmRelocationComplete (\r
138 VOID\r
139 )\r
140{\r
141}\r
142\r
143/**\r
144 Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is\r
145 returned, then a custom SMI handler is not provided by this library,\r
146 and the default SMI handler must be used.\r
147\r
148 @retval 0 Use the default SMI handler.\r
149 @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()\r
150 The caller is required to allocate enough SMRAM for each CPU to\r
151 support the size of the custom SMI handler.\r
152**/\r
153UINTN\r
154EFIAPI\r
155SmmCpuFeaturesGetSmiHandlerSize (\r
156 VOID\r
157 )\r
158{\r
159 return 0;\r
160}\r
161\r
162/**\r
163 Install a custom SMI handler for the CPU specified by CpuIndex. This function\r
164 is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater\r
165 than zero and is called by the CPU that was elected as monarch during System\r
166 Management Mode initialization.\r
167\r
168 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r
169 The value must be between 0 and the NumberOfCpus field\r
170 in the System Management System Table (SMST).\r
171 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r
172 @param[in] SmiStack The stack to use when an SMI is processed by the\r
173 the CPU specified by CpuIndex.\r
174 @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r
175 processed by the CPU specified by CpuIndex.\r
176 @param[in] GdtBase The base address of the GDT to use when an SMI is\r
177 processed by the CPU specified by CpuIndex.\r
178 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r
179 processed by the CPU specified by CpuIndex.\r
180 @param[in] IdtBase The base address of the IDT to use when an SMI is\r
181 processed by the CPU specified by CpuIndex.\r
182 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r
183 processed by the CPU specified by CpuIndex.\r
184 @param[in] Cr3 The base address of the page tables to use when an SMI\r
185 is processed by the CPU specified by CpuIndex.\r
186**/\r
187VOID\r
188EFIAPI\r
189SmmCpuFeaturesInstallSmiHandler (\r
190 IN UINTN CpuIndex,\r
191 IN UINT32 SmBase,\r
192 IN VOID *SmiStack,\r
193 IN UINTN StackSize,\r
194 IN UINTN GdtBase,\r
195 IN UINTN GdtSize,\r
196 IN UINTN IdtBase,\r
197 IN UINTN IdtSize,\r
198 IN UINT32 Cr3\r
199 )\r
200{\r
201}\r
202\r
203/**\r
204 Determines if MTRR registers must be configured to set SMRAM cache-ability\r
205 when executing in System Management Mode.\r
206\r
207 @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.\r
208 @retval FALSE MTRR registers do not need to be configured to set SMRAM\r
209 cache-ability.\r
210**/\r
211BOOLEAN\r
212EFIAPI\r
213SmmCpuFeaturesNeedConfigureMtrrs (\r
214 VOID\r
215 )\r
216{\r
217 return TRUE;\r
218}\r
219\r
220/**\r
221 Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
222 returns TRUE.\r
223**/\r
224VOID\r
225EFIAPI\r
226SmmCpuFeaturesDisableSmrr (\r
227 VOID\r
228 )\r
229{\r
230 //\r
231 // Use QNC to disable SMRR on Quark\r
232 //\r
233 QNCPortWrite(\r
234 QUARK_NC_HOST_BRIDGE_SB_PORT_ID,\r
235 QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK,\r
236 QNCPortRead(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK) & ~EFI_MSR_SMRR_PHYS_MASK_VALID\r
237 );\r
238}\r
239\r
240/**\r
241 Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
242 returns TRUE.\r
243**/\r
244VOID\r
245EFIAPI\r
246SmmCpuFeaturesReenableSmrr (\r
247 VOID\r
248 )\r
249{\r
250 //\r
251 // Use QNC to enable SMRR on Quark\r
252 //\r
253 QNCPortWrite(\r
254 QUARK_NC_HOST_BRIDGE_SB_PORT_ID,\r
255 QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK,\r
256 QNCPortRead(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK) | EFI_MSR_SMRR_PHYS_MASK_VALID\r
257 );\r
258}\r
259\r
260/**\r
261 Processor specific hook point each time a CPU enters System Management Mode.\r
262\r
263 @param[in] CpuIndex The index of the CPU that has entered SMM. The value\r
264 must be between 0 and the NumberOfCpus field in the\r
265 System Management System Table (SMST).\r
266**/\r
267VOID\r
268EFIAPI\r
269SmmCpuFeaturesRendezvousEntry (\r
270 IN UINTN CpuIndex\r
271 )\r
272{\r
273}\r
274\r
275/**\r
276 Processor specific hook point each time a CPU exits System Management Mode.\r
277\r
278 @param[in] CpuIndex The index of the CPU that is exiting SMM. The value must\r
279 be between 0 and the NumberOfCpus field in the System\r
280 Management System Table (SMST).\r
281**/\r
282VOID\r
283EFIAPI\r
284SmmCpuFeaturesRendezvousExit (\r
285 IN UINTN CpuIndex\r
286 )\r
287{\r
288}\r
289\r
290/**\r
291 Check to see if an SMM register is supported by a specified CPU.\r
292\r
293 @param[in] CpuIndex The index of the CPU to check for SMM register support.\r
294 The value must be between 0 and the NumberOfCpus field\r
295 in the System Management System Table (SMST).\r
296 @param[in] RegName Identifies the SMM register to check for support.\r
297\r
298 @retval TRUE The SMM register specified by RegName is supported by the CPU\r
299 specified by CpuIndex.\r
300 @retval FALSE The SMM register specified by RegName is not supported by the\r
301 CPU specified by CpuIndex.\r
302**/\r
303BOOLEAN\r
304EFIAPI\r
305SmmCpuFeaturesIsSmmRegisterSupported (\r
306 IN UINTN CpuIndex,\r
307 IN SMM_REG_NAME RegName\r
308 )\r
309{\r
310 return FALSE;\r
311}\r
312\r
313/**\r
314 Returns the current value of the SMM register for the specified CPU.\r
315 If the SMM register is not supported, then 0 is returned.\r
316\r
317 @param[in] CpuIndex The index of the CPU to read the SMM register. The\r
318 value must be between 0 and the NumberOfCpus field in\r
319 the System Management System Table (SMST).\r
320 @param[in] RegName Identifies the SMM register to read.\r
321\r
322 @return The value of the SMM register specified by RegName from the CPU\r
323 specified by CpuIndex.\r
324**/\r
325UINT64\r
326EFIAPI\r
327SmmCpuFeaturesGetSmmRegister (\r
328 IN UINTN CpuIndex,\r
329 IN SMM_REG_NAME RegName\r
330 )\r
331{\r
332 return 0;\r
333}\r
334\r
335/**\r
336 Sets the value of an SMM register on a specified CPU.\r
337 If the SMM register is not supported, then no action is performed.\r
338\r
339 @param[in] CpuIndex The index of the CPU to write the SMM register. The\r
340 value must be between 0 and the NumberOfCpus field in\r
341 the System Management System Table (SMST).\r
342 @param[in] RegName Identifies the SMM register to write.\r
343 registers are read-only.\r
344 @param[in] Value The value to write to the SMM register.\r
345**/\r
346VOID\r
347EFIAPI\r
348SmmCpuFeaturesSetSmmRegister (\r
349 IN UINTN CpuIndex,\r
350 IN SMM_REG_NAME RegName,\r
351 IN UINT64 Value\r
352 )\r
353{\r
354}\r
355\r
356/**\r
357 Read an SMM Save State register on the target processor. If this function\r
358 returns EFI_UNSUPPORTED, then the caller is responsible for reading the\r
359 SMM Save Sate register.\r
360\r
361 @param[in] CpuIndex The index of the CPU to read the SMM Save State. The\r
362 value must be between 0 and the NumberOfCpus field in\r
363 the System Management System Table (SMST).\r
364 @param[in] Register The SMM Save State register to read.\r
365 @param[in] Width The number of bytes to read from the CPU save state.\r
366 @param[out] Buffer Upon return, this holds the CPU register value read\r
367 from the save state.\r
368\r
369 @retval EFI_SUCCESS The register was read from Save State.\r
370 @retval EFI_INVALID_PARAMTER Buffer is NULL.\r
371 @retval EFI_UNSUPPORTED This function does not support reading Register.\r
372\r
373**/\r
374EFI_STATUS\r
375EFIAPI\r
376SmmCpuFeaturesReadSaveStateRegister (\r
377 IN UINTN CpuIndex,\r
378 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
379 IN UINTN Width,\r
380 OUT VOID *Buffer\r
381 )\r
382{\r
383 return EFI_UNSUPPORTED;\r
384}\r
385\r
386/**\r
387 Writes an SMM Save State register on the target processor. If this function\r
388 returns EFI_UNSUPPORTED, then the caller is responsible for writing the\r
389 SMM Save Sate register.\r
390\r
391 @param[in] CpuIndex The index of the CPU to write the SMM Save State. The\r
392 value must be between 0 and the NumberOfCpus field in\r
393 the System Management System Table (SMST).\r
394 @param[in] Register The SMM Save State register to write.\r
395 @param[in] Width The number of bytes to write to the CPU save state.\r
396 @param[in] Buffer Upon entry, this holds the new CPU register value.\r
397\r
398 @retval EFI_SUCCESS The register was written to Save State.\r
399 @retval EFI_INVALID_PARAMTER Buffer is NULL.\r
400 @retval EFI_UNSUPPORTED This function does not support writing Register.\r
401**/\r
402EFI_STATUS\r
403EFIAPI\r
404SmmCpuFeaturesWriteSaveStateRegister (\r
405 IN UINTN CpuIndex,\r
406 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
407 IN UINTN Width,\r
408 IN CONST VOID *Buffer\r
409 )\r
410{\r
411 return EFI_UNSUPPORTED;\r
412}\r
413\r
414/**\r
415 This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r
416 notification is completely processed.\r
417**/\r
418VOID\r
419EFIAPI\r
420SmmCpuFeaturesCompleteSmmReadyToLock (\r
421 VOID\r
422 )\r
423{\r
424}\r
425\r
426/**\r
427 This API provides a method for a CPU to allocate a specific region for storing page tables.\r
428\r
429 This API can be called more once to allocate memory for page tables.\r
430\r
431 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
432 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r
433 is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r
434 returned.\r
435\r
436 This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.\r
437\r
438 @param Pages The number of 4 KB pages to allocate.\r
439\r
440 @return A pointer to the allocated buffer for page tables.\r
441 @retval NULL Fail to allocate a specific region for storing page tables,\r
442 Or there is no preference on where the page tables are allocated in SMRAM.\r
443\r
444**/\r
445VOID *\r
446EFIAPI\r
447SmmCpuFeaturesAllocatePageTableMemory (\r
448 IN UINTN Pages\r
449 )\r
450{\r
451 return NULL;\r
452}\r