projects / mirror_edk2.git / blame
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1 | /** @file\r |
| 2 | Header file for QuarkSCSocId Ioh.\r | |
| 3 | Copyright (c) 2013-2015 Intel Corporation.\r | |
| 4 | \r | |
| 5 | This program and the accompanying materials\r | |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 7 | which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | http://opensource.org/licenses/bsd-license.php\r | |
| 9 | \r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | \r | |
| 13 | \r | |
| 14 | **/\r | |
| 15 | #ifndef _IOH_H_\r | |
| 16 | #define _IOH_H_\r | |
| 17 | \r | |
| 18 | #ifndef BIT0\r | |
| 19 | #define BIT0 0x01\r | |
| 20 | #define BIT1 0x02\r | |
| 21 | #define BIT2 0x04\r | |
| 22 | #define BIT3 0x08\r | |
| 23 | #define BIT4 0x10\r | |
| 24 | #define BIT5 0x20\r | |
| 25 | #define BIT6 0x40\r | |
| 26 | #define BIT7 0x80\r | |
| 27 | #define BIT8 0x100\r | |
| 28 | #define BIT9 0x200\r | |
| 29 | #define BIT00 0x00000001\r | |
| 30 | #define BIT01 0x00000002\r | |
| 31 | #define BIT02 0x00000004\r | |
| 32 | #define BIT03 0x00000008\r | |
| 33 | #define BIT04 0x00000010\r | |
| 34 | #define BIT05 0x00000020\r | |
| 35 | #define BIT06 0x00000040\r | |
| 36 | #define BIT07 0x00000080\r | |
| 37 | #define BIT08 0x00000100\r | |
| 38 | #define BIT09 0x00000200\r | |
| 39 | #define BIT10 0x00000400\r | |
| 40 | #define BIT11 0x00000800\r | |
| 41 | #define BIT12 0x00001000\r | |
| 42 | #define BIT13 0x00002000\r | |
| 43 | #define BIT14 0x00004000\r | |
| 44 | #define BIT15 0x00008000\r | |
| 45 | #define BIT16 0x00010000\r | |
| 46 | #define BIT17 0x00020000\r | |
| 47 | #define BIT18 0x00040000\r | |
| 48 | #define BIT19 0x00080000\r | |
| 49 | #define BIT20 0x00100000\r | |
| 50 | #define BIT21 0x00200000\r | |
| 51 | #define BIT22 0x00400000\r | |
| 52 | #define BIT23 0x00800000\r | |
| 53 | #define BIT24 0x01000000\r | |
| 54 | #define BIT25 0x02000000\r | |
| 55 | #define BIT26 0x04000000\r | |
| 56 | #define BIT27 0x08000000\r | |
| 57 | #define BIT28 0x10000000\r | |
| 58 | #define BIT29 0x20000000\r | |
| 59 | #define BIT30 0x40000000\r | |
| 60 | #define BIT31 0x80000000\r | |
| 61 | #endif\r | |
| 62 | \r | |
| 63 | #define IOH_PCI_CFG_ADDRESS(bus,dev,func,reg) \\r | |
| 64 | ((UINT32) ( (((UINTN)bus) << 24) + (((UINTN)dev) << 16) + \\r | |
| 65 | (((UINTN)func) << 8) + ((UINTN)reg) ))& 0x00000000ffffffff\r | |
| 66 | \r | |
| 67 | //----------------------------------------------------------------------------\r | |
| 68 | \r | |
| 69 | #define INTEL_VENDOR_ID 0x8086 // Intel Vendor ID\r | |
| 70 | \r | |
| 71 | //----------------------------------------------------------------------------\r | |
| 72 | // Pci Configuration Map Register Offsets\r | |
| 73 | //----------------------------------------------------------------------------\r | |
| 74 | #define PCI_REG_VID 0x00 // Vendor ID Register\r | |
| 75 | #define PCI_REG_DID 0x02 // Device ID Register\r | |
| 76 | #define PCI_REG_PCICMD 0x04 // PCI Command Register\r | |
| 77 | #define PCI_REG_PCISTS 0x06 // PCI Status Register\r | |
| 78 | #define PCI_REG_RID 0x08 // PCI Revision ID Register\r | |
| 79 | #define PCI_REG_PI 0x09 // Programming Interface\r | |
| 80 | #define PCI_REG_SCC 0x0a // Sub Class Code Register\r | |
| 81 | #define PCI_REG_BCC 0x0b // Base Class Code Register\r | |
| 82 | #define PCI_REG_PMLT 0x0d // Primary Master Latnecy Timer\r | |
| 83 | #define PCI_REG_HDR 0x0e // Header Type Register\r | |
| 84 | #define PCI_REG_PBUS 0x18 // Primary Bus Number Register\r | |
| 85 | #define PCI_REG_SBUS 0x19 // Secondary Bus Number Register\r | |
| 86 | #define PCI_REG_SUBUS 0x1a // Subordinate Bus Number Register\r | |
| 87 | #define PCI_REG_SMLT 0x1b // Secondary Master Latnecy Timer\r | |
| 88 | #define PCI_REG_IOBASE 0x1c // I/O base Register\r | |
| 89 | #define PCI_REG_IOLIMIT 0x1d // I/O Limit Register\r | |
| 90 | #define PCI_REG_SECSTATUS 0x1e // Secondary Status Register\r | |
| 91 | #define PCI_REG_MEMBASE 0x20 // Memory Base Register\r | |
| 92 | #define PCI_REG_MEMLIMIT 0x22 // Memory Limit Register\r | |
| 93 | #define PCI_REG_PRE_MEMBASE 0x24 // Prefretchable memory Base register\r | |
| 94 | #define PCI_REG_PRE_MEMLIMIT 0x26 // Prefretchable memory Limit register\r | |
| 95 | #define PCI_REG_SVID0 0x2c // Subsystem Vendor ID low byte\r | |
| 96 | #define PCI_REG_SVID1 0x2d // Subsystem Vendor ID high byte\r | |
| 97 | #define PCI_REG_SID0 0x2e // Subsystem ID low byte\r | |
| 98 | #define PCI_REG_SID1 0x2f // Subsystem ID high byte\r | |
| 99 | #define PCI_REG_IOBASE_U 0x30 // I/O base Upper Register\r | |
| 100 | #define PCI_REG_IOLIMIT_U 0x32 // I/O Limit Upper Register\r | |
| 101 | #define PCI_REG_INTLINE 0x3c // Interrupt Line Register\r | |
| 102 | #define PCI_REG_BRIDGE_CNTL 0x3e // Bridge Control Register\r | |
| 103 | \r | |
| 104 | //---------------------------------------------------------------------------\r | |
| 105 | // QuarkSCSocId Packet Hub definitions\r | |
| 106 | //---------------------------------------------------------------------------\r | |
| 107 | \r | |
| 108 | #define PCIE_BRIDGE_VID_DID 0x88008086\r | |
| 109 | \r | |
| 110 | //---------------------------------------------------------------------------\r | |
| 111 | // Quark South Cluster definitions.\r | |
| 112 | //---------------------------------------------------------------------------\r | |
| 113 | \r | |
| 114 | #define IOH_BUS 0\r | |
| 115 | #define IOH_PCI_IOSF2AHB_0_DEV_NUM 0x14\r | |
| 116 | #define IOH_PCI_IOSF2AHB_0_MAX_FUNCS 7\r | |
| 117 | #define IOH_PCI_IOSF2AHB_1_DEV_NUM 0x15\r | |
| 118 | #define IOH_PCI_IOSF2AHB_1_MAX_FUNCS 3\r | |
| 119 | \r | |
| 120 | //---------------------------------------------------------------------------\r | |
| 121 | // Quark South Cluster USB definitions.\r | |
| 122 | //---------------------------------------------------------------------------\r | |
| 123 | \r | |
| 124 | #define IOH_USB_BUS_NUMBER IOH_BUS\r | |
| 125 | #define IOH_USB_CONTROLLER_MMIO_RANGE 0x1000\r | |
| 126 | #define IOH_MAX_OHCI_USB_CONTROLLERS 1\r | |
| 127 | #define IOH_MAX_EHCI_USB_CONTROLLERS 1\r | |
| 128 | #define IOH_MAX_USBDEVICE_USB_CONTROLLERS 1\r | |
| 129 | \r | |
| 130 | #define R_IOH_USB_VENDOR_ID 0x00\r | |
| 131 | #define V_IOH_USB_VENDOR_ID INTEL_VENDOR_ID\r | |
| 132 | #define R_IOH_USB_DEVICE_ID 0x02\r | |
| 133 | #define R_IOH_USB_COMMAND 0x04\r | |
| 134 | #define B_IOH_USB_COMMAND_BME BIT2\r | |
| 135 | #define B_IOH_USB_COMMAND_MSE BIT1\r | |
| 136 | #define B_IOH_USB_COMMAND_ISE BIT0\r | |
| 137 | #define R_IOH_USB_MEMBAR 0x10\r | |
| 138 | #define B_IOH_USB_MEMBAR_ADDRESS_MASK 0xFFFFF000 // [31:12].\r | |
| 139 | #define R_IOH_USB_OHCI_HCCABAR 0x18\r | |
| 140 | \r | |
| 141 | //---------------------------------------------------------------------------\r | |
| 142 | // Quark South Cluster OHCI definitions\r | |
| 143 | //---------------------------------------------------------------------------\r | |
| 144 | #define IOH_USB_OHCI_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM\r | |
| 145 | #define IOH_OHCI_FUNCTION_NUMBER 0x04\r | |
| 146 | \r | |
| 147 | //---------------------------------------------------------------------------\r | |
| 148 | // Quark South Cluster EHCI definitions\r | |
| 149 | //---------------------------------------------------------------------------\r | |
| 150 | #define IOH_USB_EHCI_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM\r | |
| 151 | #define IOH_EHCI_FUNCTION_NUMBER 0x03\r | |
| 152 | \r | |
| 153 | //\r | |
| 154 | // EHCI memory mapped registers offset from memory BAR0.\r | |
| 155 | //\r | |
| 156 | #define R_IOH_EHCI_CAPLENGTH 0x00\r | |
| 157 | #define R_IOH_EHCI_INSNREG01 0x94\r | |
| 158 | #define B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP (16)\r | |
| 159 | #define B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK (0xff << B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP)\r | |
| 160 | #define B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP (0)\r | |
| 161 | #define B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK (0xff << B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP)\r | |
| 162 | \r | |
| 163 | //\r | |
| 164 | // EHCI memory mapped registers offset from memory BAR0 + Cap length value.\r | |
| 165 | //\r | |
| 166 | #define R_IOH_EHCI_CONFIGFLAGS 0x40\r | |
| 167 | \r | |
| 168 | //---------------------------------------------------------------------------\r | |
| 169 | // Quark South Cluster USB Device definitions\r | |
| 170 | //---------------------------------------------------------------------------\r | |
| 171 | #define IOH_USBDEVICE_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM\r | |
| 172 | #define IOH_USBDEVICE_FUNCTION_NUMBER 0x02\r | |
| 173 | \r | |
| 174 | //\r | |
| 175 | // USB Device memory mapped registers offset from memory BAR0.\r | |
| 176 | //\r | |
| 177 | #define R_IOH_USBDEVICE_D_INTR_UDC_REG 0x40c\r | |
| 178 | #define R_IOH_USBDEVICE_D_INTR_MSK_UDC_REG 0x410\r | |
| 179 | #define B_IOH_USBDEVICE_D_INTR_MSK_UDC_REG_MASK1_MASK 0xff\r | |
| 180 | #define R_IOH_USBDEVICE_EP_INTR_UDC_REG 0x414\r | |
| 181 | #define R_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG 0x418\r | |
| 182 | #define B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_OUT_EP_MASK 0x000f0000\r | |
| 183 | #define B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_IN_EP_MASK 0x0000000f\r | |
| 184 | \r | |
| 185 | //---------------------------------------------------------------------------\r | |
| 186 | // Quark South Cluster 10/100 Mbps Ethernet Device definitions.\r | |
| 187 | //---------------------------------------------------------------------------\r | |
| 188 | #define IOH_MAC0_BUS_NUMBER IOH_BUS\r | |
| 189 | #define IOH_MAC0_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM\r | |
| 190 | #define IOH_MAC0_FUNCTION_NUMBER 0x06\r | |
| 191 | #define IOH_MAC1_BUS_NUMBER IOH_BUS\r | |
| 192 | #define IOH_MAC1_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM\r | |
| 193 | #define IOH_MAC1_FUNCTION_NUMBER 0x07\r | |
| 194 | \r | |
| 195 | //\r | |
| 196 | // MAC Device PCI config registers.\r | |
| 197 | //\r | |
| 198 | #define R_IOH_MAC_DEVICE_ID 0x02\r | |
| 199 | #define V_IOH_MAC_VENDOR_ID INTEL_VENDOR_ID\r | |
| 200 | #define R_IOH_MAC_DEVICE_ID 0x02\r | |
| 201 | #define V_IOH_MAC_DEVICE_ID 0x0937\r | |
| 202 | #define R_IOH_MAC_COMMAND 0x04\r | |
| 203 | #define B_IOH_MAC_COMMAND_BME BIT2\r | |
| 204 | #define B_IOH_MAC_COMMAND_MSE BIT1\r | |
| 205 | #define B_IOH_MAC_COMMAND_ISE BIT0\r | |
| 206 | #define R_IOH_MAC_MEMBAR 0x10\r | |
| 207 | #define B_IOH_MAC_MEMBAR_ADDRESS_MASK 0xFFFFF000\r | |
| 208 | \r | |
| 209 | //\r | |
| 210 | // LAN Device memory mapped registers offset from memory BAR0.\r | |
| 211 | //\r | |
| 212 | #define R_IOH_MAC_GMAC_REG_8 0x20\r | |
| 213 | #define B_IOH_MAC_USERVER_MASK 0x0000FF00\r | |
| 214 | #define B_IOH_MAC_SNPSVER_MASK 0x000000FF\r | |
| 215 | #define R_IOH_MAC_GMAC_REG_16 0x40\r | |
| 216 | #define B_IOH_MAC_ADDRHI_MASK 0x0000FFFF\r | |
| 217 | #define B_IOH_MAC_AE BIT31\r | |
| 218 | #define R_IOH_MAC_GMAC_REG_17 0x44\r | |
| 219 | #define B_IOH_MAC_ADDRLO_MASK 0xFFFFFFFF\r | |
| 220 | \r | |
| 221 | //---------------------------------------------------------------------------\r | |
| 222 | // Quark I2C / GPIO definitions\r | |
| 223 | //---------------------------------------------------------------------------\r | |
| 224 | \r | |
| 225 | #define V_IOH_I2C_GPIO_VENDOR_ID INTEL_VENDOR_ID\r | |
| 226 | #define V_IOH_I2C_GPIO_DEVICE_ID 0x0934\r | |
| 227 | \r | |
| 228 | #define R_IOH_I2C_MEMBAR 0x10\r | |
| 229 | #define B_IOH_I2C_GPIO_MEMBAR_ADDR_MASK 0xFFFFF000 // [31:12].\r | |
| 230 | \r | |
| 231 | #define GPIO_SWPORTA_DR 0x00\r | |
| 232 | #define GPIO_SWPORTA_DDR 0x04\r | |
| 233 | #define GPIO_INTEN 0x30\r | |
| 234 | #define GPIO_INTMASK 0x34\r | |
| 235 | #define GPIO_INTTYPE_LEVEL 0x38\r | |
| 236 | #define GPIO_INT_POLARITY 0x3C\r | |
| 237 | #define GPIO_INTSTATUS 0x40\r | |
| 238 | #define GPIO_RAW_INTSTATUS 0x44\r | |
| 239 | #define GPIO_DEBOUNCE 0x48\r | |
| 240 | #define GPIO_PORTA_EOI 0x4C\r | |
| 241 | #define GPIO_EXT_PORTA 0x50\r | |
| 242 | #define GPIO_EXT_PORTB 0x54\r | |
| 243 | #define GPIO_LS_SYNC 0x60\r | |
| 244 | #define GPIO_CONFIG_REG2 0x70\r | |
| 245 | #define GPIO_CONFIG_REG1 0x74\r | |
| 246 | \r | |
| 247 | //---------------------------------------------------------------------------\r | |
| 248 | // Quark South Cluster UART definitions.\r | |
| 249 | //---------------------------------------------------------------------------\r | |
| 250 | \r | |
| 251 | #define R_IOH_UART_MEMBAR 0x10\r | |
| 252 | #define B_IOH_UART_MEMBAR_ADDRESS_MASK 0xFFFFF000 // [31:12].\r | |
| 253 | \r | |
| 254 | #endif\r |