QuarkSocPkg: Replace BSD License with BSD+Patent License

[mirror_edk2.git] / QuarkSocPkg / QuarkSouthCluster / Library / IohLib / IohLib.c

/** @file\r
Lib function for Pei Quark South Cluster.\r
\r
Copyright (c) 2013-2016 Intel Corporation.\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
#include "CommonHeader.h"\r
\r
/**\r
  Program SVID/SID the same as VID/DID*\r
**/\r
EFI_STATUS\r
EFIAPI\r
InitializeIohSsvidSsid (\r
   IN UINT8   Bus,\r
   IN UINT8   Device,\r
   IN UINT8   Func\r
   )\r
{\r
  UINTN       Index;\r
\r
  for (Index = 0; Index <= IOH_PCI_IOSF2AHB_0_MAX_FUNCS; Index++) {\r
    if (((Device == IOH_PCI_IOSF2AHB_1_DEV_NUM) && (Index >= IOH_PCI_IOSF2AHB_1_MAX_FUNCS))) {\r
      continue;\r
    }\r
\r
    IohMmPci32(0, Bus, Device, Index, PCI_REG_SVID0) = IohMmPci32(0, Bus, Device, Index, PCI_REG_VID);\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/* Enable memory, io, and bus master for USB controller */\r
VOID\r
EFIAPI\r
EnableUsbMemIoBusMaster (\r
  IN UINT8   UsbBusNumber\r
  )\r
{\r
  UINT16 CmdReg;\r
\r
  CmdReg = PciRead16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_OHCI_DEVICE_NUMBER, IOH_OHCI_FUNCTION_NUMBER, PCI_REG_PCICMD));\r
  CmdReg = (UINT16) (CmdReg | EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_IO_SPACE | EFI_PCI_COMMAND_BUS_MASTER);\r
  PciWrite16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_OHCI_DEVICE_NUMBER, IOH_OHCI_FUNCTION_NUMBER, PCI_REG_PCICMD), CmdReg);\r
\r
  CmdReg = PciRead16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_EHCI_DEVICE_NUMBER, IOH_EHCI_FUNCTION_NUMBER, PCI_REG_PCICMD));\r
  CmdReg = (UINT16) (CmdReg | EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_IO_SPACE | EFI_PCI_COMMAND_BUS_MASTER);\r
  PciWrite16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_EHCI_DEVICE_NUMBER, IOH_EHCI_FUNCTION_NUMBER, PCI_REG_PCICMD), CmdReg);\r
}\r
\r
/**\r
  Read south cluster GPIO input from Port A.\r
\r
**/\r
UINT32\r
EFIAPI\r
ReadIohGpioValues (\r
  VOID\r
  )\r
{\r
  UINT32  GipData;\r
  UINT32  GipAddr;\r
  UINT32  TempBarAddr;\r
  UINT16  SaveCmdReg;\r
  UINT32  SaveBarReg;\r
\r
  TempBarAddr = (UINT32) PcdGet64(PcdIohGpioMmioBase);\r
\r
  GipAddr = PCI_LIB_ADDRESS(\r
      PcdGet8 (PcdIohGpioBusNumber),\r
      PcdGet8 (PcdIohGpioDevNumber),\r
      PcdGet8 (PcdIohGpioFunctionNumber), 0);\r
\r
  //\r
  // Save current settings for PCI CMD/BAR registers.\r
  //\r
  SaveCmdReg = PciRead16 (GipAddr + PCI_COMMAND_OFFSET);\r
  SaveBarReg = PciRead32 (GipAddr + PcdGet8 (PcdIohGpioBarRegister));\r
\r
  DEBUG ((EFI_D_INFO, "SC GPIO temporary enable  at %08X\n", TempBarAddr));\r
\r
  // Use predefined temporary memory resource.\r
  PciWrite32 ( GipAddr + PcdGet8 (PcdIohGpioBarRegister), TempBarAddr);\r
  PciWrite8 ( GipAddr + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);\r
\r
  // Read GPIO configuration\r
  GipData = MmioRead32(TempBarAddr + GPIO_EXT_PORTA);\r
\r
  //\r
  // Restore settings for PCI CMD/BAR registers.\r
  //\r
  PciWrite32 ((GipAddr + PcdGet8 (PcdIohGpioBarRegister)), SaveBarReg);\r
  PciWrite16 (GipAddr + PCI_COMMAND_OFFSET, SaveCmdReg);\r
\r
  // Only 8 bits valid.\r
  return GipData & 0x000000FF;\r
}\r